JPH05233478A - Flash memory rewriting circuit - Google Patents

Abstract

PURPOSE:To reduce the amount of downloaded data, and shorten a necessary time and reduce the load on a bus by saving information temporarily and downloading only rewritten information. CONSTITUTION:This circuit consists of a CPU 1, an EPROM 2, an SRAM 3, an FRAM(flash memory) 4, a register 5, and an address bus 9 and a data bus 10 which connect them. The register 5 is used to save the information of the FRAM 4. Further, the CPU 1 is connected to an FRAM rewritten information transfer terminal 7 and an FRAM rewritten information file 8 through an RS232C line 6, and the terminal 7 is operated to sends the rewritten information in the file 8 to the CPU 1. Further, information before the FRAM 4 is all erased or rewritten is saved in the register 5 temporarily and the saved information is put back from the register 5 after the FRAM 4 is rewritten.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory rewriting circuit, and more particularly to a flash memory rewriting circuit.

[0002]

2. Description of the Related Art A flash memory (FRAM) is generally non-volatile but can be erased / written by applying a constant voltage to an erase pin. Then, as shown in FIG. 2, the conventional flash memory rewriting circuit has a CPU
(Central processing unit) 21, FRAM 24, EPROM
(Erasable and Programmable
e Read Only Memory) 22 and SR
AM (Static Random Access M)
23). CPU21 and EPRO
The M22 and the like are connected by the address bus 16 and the data bus 30, and the CPU 21 uses the RS23.
F through 2C line (American Electronics Association EIA) 26
It is connected to the RAM rewriting information transfer terminal 27 and the FRAM rewriting information file 28.

After the FRAM clear program on the EPROM 22 completely erases the contents of the FRAM 24, the rewrite information is downloaded to the SRAM 23 by the download control program on the EPROM 22 as well. Then, the contents of the FRAM 24 are rewritten by copying the information on the SRAM 23 to the FRAM 24.

[0004]

In the conventional flash memory rewriting circuit, all the contents of the FRAM 24 are erased by clearing the FRAM before rewriting.
It is necessary to download all of the information written in M24 onto the SRAM 23. For this reason, there is a problem that the required time is extended by this amount. In addition, when downloading is performed by a common bus between devices, there is a problem that the bus is burdened.

The present invention has been made in view of the above problems. Even when only a part of a flash memory is rewritten, the amount of information to be downloaded is reduced to shorten the time required and the load on the flash memory is not increased. For the purpose of providing.

[0006]

In order to achieve the above object, the present invention according to claim 1 provides an EPROM for holding a rewriting program, an SRAM in which rewriting information is downloaded, and rewriting information copied from the SRAM. Flash memory and the above EPROM, S
For a rewrite circuit configured with a CPU that controls RAM and flash memory and that is connected by a common bus,
The information on the flash memory before rewriting is temporarily saved, and after copying to the flash memory, a register is added to return the temporarily saved information to the flash memory. Further, the present invention according to claim 2 is configured such that the register is a register in which information in an area that does not need to be rewritten is temporarily saved before full erasing of the flash memory and the copied information is returned after copying.

[0007]

In the present invention configured as described above, the information before the entire erasing and rewriting of the flash memory is temporarily saved in the register. Next, after rewriting the flash memory, the saved information is returned from the register.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram showing a flash memory rewriting circuit of this embodiment. This flash memory rewriting circuit is composed of CPU1, EPROM2, SRAM3,
It is composed of an FRAM (flash memory) 4, a register 5, and an address bus 9 and a data bus 10 connecting these. Here, the register 5 is used for saving information in the FRAM 4.

Further, the CPU 1 is connected to the FRAM rewriting information transfer terminal 7 and the FRAM rewriting information file 8 through the RS232C line 6, and operates the FRAM rewriting information transfer terminal 7 to rewrite information of the FRAM rewriting information file 8. Is transmitted to the CPU 1.

Next, the operation of the above flash memory rewriting circuit will be described. FRAM on SRAM3 by the download control program in EPROM2
Download the rewrite information of 4. The information of the area that is not rewritten on the FRAM4 is copied to the register 5, and the contents of the FRAM4 are completely erased by the FRAM clear program in the EPROM2. And SRA
The FRAM rewriting information downloaded on M3 is copied to the area to be rewritten on the FRAM4 after erasing. Furthermore, the information saved in the register 5 is saved in the FR.
Copy to the original non-rewritable area on AM4.

As a result, the information saved in the register 5 does not need to be downloaded to the SRAM 3, the amount of downloaded information can be greatly reduced, the required time can be shortened, and the load on the bus can be reduced.

[0012]

As described above, according to the present invention, the information is temporarily saved and only the rewriting information is downloaded. Therefore, the amount of downloaded information is greatly reduced, the required time is shortened, and the load on the bus is reduced. Can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a flash memory rewriting circuit according to an embodiment.

FIG. 2 is a block diagram of a conventional flash memory rewriting circuit.

[Explanation of symbols]

 1,21 CPU 2,22 EPROM 3,23 SRAM 4,24 FRAM 5 register 9,29 address bus 10,30 data bus

Claims (2)

[Claims] 1. An EPR holding a rewriting program.
A rewriting circuit composed of an OM, an SRAM in which rewriting information is downloaded, a flash memory in which the rewriting information is copied from the SRAM, and a CPU which controls the EPROM, SRAM, and flash memory and is connected by a common bus. On the other hand, the flash memory rewriting circuit is characterized in that the information in the flash memory before rewriting is temporarily saved, and after copying to the flash memory, a register is added to return the temporarily saved information to the flash memory. 2. The register according to claim 1, wherein the information in the area that does not need to be rewritten is temporarily saved before full erasing of the flash memory, and the saved information is returned after copying. Flash memory rewriting circuit.