JP2903846B2 - Multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for multiplying an analog signal, and more particularly to a multiplier configured on a bipolar integrated circuit.

[0002]

2. Description of the Related Art As a conventional multiplier, a Gilbert multiplier is generally used. For example, as shown in FIG. 25, a transistor pair is formed by stacking two pairs of transistors. Hereinafter, the operation of this circuit will be described.

In FIG. 25, a current (emitter current) _IE of a junction diode constituting a transistor is expressed by the following equation (1). Incidentally, in Equation 1, I _S is the saturation current, k is Boltzmann's constant, q is the charge of an electron, the V _BE between the base and emitter voltage, T is the absolute temperature.

[0004]

(Equation 1)

Now, if V _T = kT / q, V _BE >> V _T
Therefore, in Expression 1, exp (V _BE / V _T ) >> 1
Then, the emitter current _IE can be approximated by the following equation (2).

[0006]

(Equation 2)

Then, the collector current of each transistor in FIG. 25 can be expressed by the following equations (3), (4), (5), (6), (7) and (8). Here, α _F is a current amplification factor.

[0008]

(Equation 3)

[0009]

(Equation 4)

[0010]

(Equation 5)

[0011]

(Equation 6)

[0012]

(Equation 7)

[0013]

(Equation 8)

Therefore, the collector currents I _C43 , I _C44 ,
I _C45 and I _C46 are given by the following equations (9) and (10), respectively.
11 and 12 are shown.

[0015]

(Equation 9)

[0016]

(Equation 10)

[0017]

[Equation 11]

[0018]

(Equation 12)

Therefore, the difference current ΔI between the output currents I _C43-45 and I _C44-46 is expressed by the following equation (13).

[0020]

(Equation 13)

On the other hand, since tanhx is series-expanded as in the following equation 14, when | x | << 1, tanhx ≒ x
Can be approximated.

[0022]

[Equation 14]

Therefore, | V ₄₁ | << 2V _T , | V ₄₂ | << 2
When the V _T, the difference current ΔI can be approximated by Equation 15, the voltage V ₄₁ of the small signal, it is seen that a multiplier for the same V ₄₂ (multiplier).

[0024]

(Equation 15)

[0025]

The above-mentioned conventional Gilbert multiplier has a problem that the power supply voltage cannot be reduced because a two-stage transistor pair is used.

An object of the present invention is to provide a multiplier capable of reducing a power supply voltage.

[0027]

In order to achieve the above object, a multiplier according to the present invention has the following configuration. That is, the multiplier of the first invention includes two sets of squaring circuits each formed of two sets of unbalanced differential pairs. Two input voltage signals are applied to the differential input pair of one squaring circuit. The two input voltage signals are applied to the differential input pair of the other squaring circuit in an in-phase relationship with each other;
Between the two sets of squaring circuits, those having different polarities of the respective differential output pairs are commonly connected to each other to form an output terminal pair;

The multiplier according to the second invention is a three-square circuit composed of two sets of unbalanced differential pairs, wherein the first input terminal and the second input terminal are connected to a differential input pair. A first squaring circuit, a second squaring circuit having a first input terminal and a third input terminal as a differential input pair, and a second input terminal and a third input terminal.
And a third squaring circuit having a pair of input terminals as a differential input pair; a first input voltage signal is provided between the first input terminal and the third input terminal, and a second input circuit is provided between the first input terminal and the third input terminal. A second input voltage signal is applied between the terminal and the third input terminal in the same phase, respectively. Between the three sets of squaring circuits, the differential output of each of the second and third squaring circuits is applied. The same polarity of the pair and the different polarity of the differential output pair of the first squaring circuit are commonly connected to form an output terminal pair;

The multiplier of the third invention is a four-square circuit composed of two sets of unbalanced differential pairs, wherein the first input terminal and the second input terminal are connected to a differential input pair. A first squaring circuit, a second input circuit having a first input terminal and a third input terminal as a differential input pair, and a second input circuit and a third input terminal being differential. A third squaring circuit as an input pair;
A fourth squaring circuit having an input terminal as a differential input pair; a first input voltage signal is provided between the first input terminal and the third input terminal; A second input voltage signal is applied in phase between the first input terminal and the third input terminal. Between the four sets of squaring circuits, a differential output pair of each of the second and third squaring circuits is applied. Are connected in common with each other and have different polarities of the differential output pair of the first squaring circuit to form an output terminal pair, and the differential output pair of the fourth squaring circuit is Are respectively connected to the same polarity side of the differential output pair of the squaring circuit.

A multiplier according to a fourth aspect of the present invention is the multiplier according to the first aspect, the second aspect, or the third aspect of the present invention;
Two transistors each having a different emitter size; between the two sets, the base of the transistor with the larger emitter size and the base of the transistor with the smaller emitter size are connected in common to each other to provide a differential input. A pair of transistors; the collectors of transistors having a larger emitter size and the collectors of transistors having a smaller emitter size are commonly connected to each other to form a differential output pair.

The multiplier of the fifth invention is the multiplier of the first invention, the second invention or the third invention; two sets of unbalanced differential pairs forming the squaring circuit are:
Two transistors each having a different emitter size and having an emitter resistance added to each emitter in inverse proportion to the ratio of the emitter size; and between the two sets, the base and emitter size of the larger emitter size transistor The bases of the smaller transistors are commonly connected to each other to form a differential input pair; the collectors of the larger-emitter transistors and the collectors of the smaller-emitter transistors are commonly connected to each other. A dynamic output pair.

The multiplier of the sixth invention is the multiplier of the first invention, the second invention or the third invention; two sets of unbalanced differential pairs forming the squaring circuit are:
Two transistors having different emitter sizes, one having an emitter resistance and the other having no emitter resistance; and between the two sets, the base of the transistor having the larger emitter size and the smaller transistor having the smaller emitter size. And the bases of the transistors are commonly connected to form a differential input pair; the collectors of the transistors having the larger emitter size and the collectors of the transistors having the smaller emitter size are commonly connected to each other to form a differential output pair. Which is characterized by the following.

The multiplier of the seventh invention is the multiplier of the first invention, the second invention or the third invention; two sets of unbalanced differential pairs forming the squaring circuit are:
Two transistors each having the same emitter size, one having an emitter resistance and the other having no emitter resistance; between the two sets, the base and the emitter of the transistor having the emitter resistance The bases of transistors having no resistance are connected together to form a differential input pair; the collectors of transistors having emitter resistance and the collectors of transistors without emitter resistance are connected together to form a differential output pair. Which is characterized by the following.

The multiplier according to an eighth aspect of the present invention is the multiplier according to the first aspect, the second aspect or the third aspect of the present invention;
A transistor having an emitter resistance and a Darlington-connected transistor; and between the two sets, the base of the transistor having the emitter resistance and the base of the Darlington-connected transistor are connected in common to each other to form a differential input pair. The collectors of transistors having emitter resistance and the collectors of Darlington-connected transistors are commonly connected to each other to form a differential output pair.

A multiplier according to a ninth aspect of the present invention comprises: two sets of squaring circuits composed of two sets of unbalanced differential pairs; the first and second unbalanced differential pairs of one of the squaring circuits. First in
A first input voltage signal is applied between one input terminal of the unbalanced differential pair and one input terminal of the second unbalanced differential pair;
A second input voltage signal is applied between the other input terminal of the first unbalanced differential pair and the other input terminal of the second unbalanced differential pair; A second input voltage signal is applied between one input terminal of the third unbalanced differential pair and one input terminal of the fourth unbalanced differential pair in the fourth unbalanced differential pair; A first input voltage signal is applied between the other input terminal of the third unbalanced differential pair and the other input terminal of the fourth unbalanced differential pair; Wherein the differential output pairs having different polarities are commonly connected to each other to form an output terminal pair;

A multiplier according to a tenth aspect is the multiplier according to the ninth aspect, wherein the two sets of unbalanced differential pairs forming the squaring circuit each include two transistors having different emitter sizes. Between the two sets, the collectors of the transistors with the larger emitter size and the collectors of the transistors with the smaller emitter size are connected in common to each other to form a differential output pair; And the other input terminal is a base of a transistor having a smaller emitter size.

The multiplier according to an eleventh aspect of the present invention is the multiplier according to the ninth aspect, wherein the two sets of unbalanced differential pairs forming the squaring circuit have different emitter sizes, respectively, and each emitter has a different emitter size ratio. Two transistors each having an emitter resistance inversely proportional to the two transistors. The collectors of the transistors having the larger emitter size and the collectors of the transistors having the smaller emitter size are connected in common between the two sets. The one input terminal is a base of a transistor having a larger emitter size, and the other input terminal is a base of a transistor having a smaller emitter size. Things.

A multiplier according to a twelfth aspect is the multiplier according to the ninth aspect, wherein the two sets of unbalanced differential pairs forming the squaring circuit have different emitter sizes, one has an emitter resistance, and the other has an emitter resistance. Comprises two transistors having no emitter resistance; between the two sets, the collectors of the larger-emitter-sized transistors and the collectors of the smaller-emitter-sized transistors are connected in common to each other to provide a differential. An output pair is formed; the one input terminal is a base of a transistor having a larger emitter size, and the other input terminal is a base of a transistor having a smaller emitter size. .

A multiplier according to a thirteenth aspect is the multiplier according to the ninth aspect, wherein the two sets of unbalanced differential pairs forming the squaring circuit are two transistors having the same emitter size. Two transistors having an emitter resistance and the other having no emitter resistance; between the two sets, the collectors of the transistors having the emitter resistance and the collectors of the transistors having no emitter resistance are connected in common. Wherein the one input terminal is a base of a transistor having an emitter resistance, and the other input terminal is a base of a transistor having no emitter resistance. .

A multiplier according to a fourteenth aspect of the present invention is the multiplier according to the ninth aspect of the present invention; wherein the two sets of unbalanced differential pairs forming the squaring circuit are a transistor having an emitter resistance and a Darlington-connected transistor, respectively. Between the two sets, the collectors of the transistors having emitter resistance and the collectors of the Darlington-connected transistors are commonly connected to each other to form a differential output pair; And the other input terminal is a base of a Darlington-connected transistor.

[0041]

Next, the operation of the multiplier of the present invention configured as described above will be described. In the multiplier of the present invention, the squaring circuit is constituted by two unbalanced differential pairs, and two sets (first invention, ninth invention), three sets (second invention) or four sets of the squaring circuit are provided. The (third invention) is arranged so as to be in a horizontal row, rather than being stacked as in the prior art, and is operated with the same power supply voltage. Therefore, it can be operated with a power supply voltage lower than the conventional one.

[0042]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a multiplier according to the first invention.
In FIG. 1, the multiplier basically includes two squaring circuits A and B. Both squaring circuits are:
It is composed of two sets of so-called unbalanced differential pairs, and has differential input / output pairs.

The differential input pairs of the two-square circuit are respectively
Two input voltage signals (V _1, V ₂₎ but is applied, the two input voltage signals (V _1, V _2), the opposite phases of the differential input pair of one square circuit A And applied to the differential input pair of the other squaring circuit B in the same phase relationship.

That is, in one squaring circuit A, a signal obtained by inverting the polarity of the input voltage signal V ₁ on the positive polarity side of the differential input pair and the polarity of the input voltage signal V ₂ on the negative polarity side (−V ₂ ) is obtained. Applied. In the other squaring circuit B, the input voltage signal V ₂ is applied to the positive polarity side of the differential input pair, and the input voltage signal V ₁ is applied to the negative polarity side of the differential input pair in an in-phase relationship.

Between the two sets of squaring circuits, those having different polarities of the respective differential output pairs are commonly connected to form an output terminal pair. That is, the positive side of the differential output pair of one squaring circuit A and the negative side of the differential output pair of the other squaring circuit B are connected in common, and
The negative side of the differential output pair of the squaring circuit A and the positive side of the differential output pair of the other squaring circuit B are commonly connected, and the output is taken out from each.

In short, the differential input voltage of _one squaring circuit A is V ₁ + V ₂ and the differential input voltage of the other squaring circuit B is V ₂ −V ₁ , so that the output terminal pair The output voltage V _OUT appearing in the above equation is obtained by subtracting the output of the bi-square circuit, that is,
As shown in Expression 16, this is expressed by the product of the input voltage V ₁ and the input voltage V ₂ , and the characteristics of the multiplier (multiplier) are obtained.

[0047]

(Equation 16)

Next, specific examples of the configuration of the squaring circuit (unbalanced differential pair) will be sequentially described with reference to FIGS. 2, 7, 10, 13, and 16. FIG. FIG. 2 shows an embodiment of the multiplier according to the first invention in the case where the unbalanced differential pair mainly includes two transistors having different emitter sizes. FIG.
In (Q1, Q2) (Q3, Q4) (Q5, Q
The four sets of pairs transistor 6) (Q7, Q8), respectively, with parallel supplied with power, the differential pair emitter each other are driven by a constant current source I ₀ equal commonly connected to values However, assuming that one transistor (Q2, Q3, Q6, Q7) is 1, the other transistor (Q1, Q4, Q5, Q8) is k (k> 1).
Doubled. That is, each differential pair is than has become unbalanced, constitute the two pairs and the constant current source I ₀ is one of the square circuit (Q1, Q2) and (Q3, Q4), (Q
5, Q6) (Q7, Q8) and its constant current source I ₀
Constitute the other squaring circuit.

Each of the two squaring circuits 2
In the pair of unbalanced differential pairs, transistors having unequal emitter sizes (Q1 and Q3, Q
2 and Q4, Q6 and Q8, Q5 and Q7) are commonly connected, and the bases of Q1 and Q3 are connected to one input terminal 1 of one differential input terminal pair (1, 2). The bases of Q2 and Q4 are connected to the other input terminal 2 of one differential input terminal pair (1, 2). Also, Q
5 and Q7 are connected to the other differential input terminal pair (3,
4), and the bases of Q6 and Q8 are connected to the other input terminal 4 of the other differential input terminal pair (3, 4). The four transistors (Q2, Q3, Q6, Q7) and the collectors (Q1, Q4, Q5, Q8) having the same emitter size are commonly connected to each other, and the differential output currents ( _Ip , _Iq ) are respectively connected. ) Is formed.

Here, one differential input terminal pair (1, 2)
Is applied with an input signal (voltage V _A ), and the other differential input terminal pair (3, 4) is applied with an input signal (voltage V _B ). Has become. The input voltage signal V _A and the input voltage signal V and the V _B
1 and relationship between the V ₂ is as shown in Equation 31, the 32 that will be described later.

In the above configuration, first, the collector currents I _C1 and I _C1 of Q1 and Q2 of one unbalanced differential pair, respectively.
_C2 is represented by the following Expressions 17 and 18.

[0052]

[Equation 17]

[0053]

(Equation 18)

However, in Equations 17 and 18, α _F
I ₀ is expressed by Expression 19.

[0055]

[Equation 19]

Therefore, the difference between the two collector currents is expressed by the following equation (20).

[0057]

(Equation 20)

Here, V _K is set as in the following Expression 21.

[0059]

(Equation 21)

Then, k is obtained as in the following equation (22).

[0061]

(Equation 22)

The difference between the two collector currents at this time (Equation 2)
0) becomes the following Expression 23.

[0063]

(Equation 23)

Next, the same applies to Q3 and Q4 of the other unbalanced differential pair, and the respective collector currents I _C3 ,
The difference of I _C4 is expressed by the following equation (24).

[0065]

(Equation 24)

Here, assuming that ΔI _A is the sum of Expressions 23 and 24, this is given by Expression 25 below.

[0067]

(Equation 25)

When | x | << 1, tanhx is expressed by Expression 14. Therefore, | V _A + V _K | << 2
V _T, when the │V _A -V _K │ "2V _T is formula 25 becomes Equation 26, a differential current proportional to the square of the input voltage V _A is obtained.

[0069]

(Equation 26)

That is, one squaring circuit can be obtained by using two sets of unbalanced differential pairs mainly composed of two transistors whose emitter size ratio is k. FIG. 3 shows the output current characteristics of this squaring circuit (SPICE simulation values).
Is shown with k as a parameter, it can be understood that a good square characteristic is obtained. In FIG. 3, I _k is the sum of the collector current multiplied by k (I _C1 + I _C4 ), and I _u is the sum of the collector current multiplied by one (I _C2 + I _C3 ). Formula 25
In is obtained by the ΔI _A = I _k -I _u.

The above is because the unbalanced differential pair (Q5, Q5
The same applies to (6) and (Q7, Q8). The following equations (27), (28) and (29) are obtained, and the differential current ΔI _B of both unbalanced differential pairs is the square of the input voltage V _B. It turns out that it is proportional to.

[0072]

[Equation 27]

[0073]

[Equation 28]

[0074]

(Equation 29)

Therefore, in FIG. 2, both differential currents (ΔI
_A , ΔI _B ), where ΔI is the sum of
Becomes

[0076]

[Equation 30]

Here, the input voltages V _A and V _B are represented by the following equations 31 and 32, respectively.

[0078]

(Equation 31)

[0079]

(Equation 32)

Then, Expression 30 becomes Expression 33, and the differential current (ΔI) proportional to the product of the voltage V ₁ and the voltage V ₂ is obtained.
Is obtained. That is, a multiplier (multiplier) was obtained. 4 to 6 show characteristic diagrams.

[0081]

[Equation 33]

FIG. 4 shows the characteristics of the differential output current ΔI calculated using the hyperbolic tangent function. It can be understood that good multiplier (multiplier) characteristics are obtained when the input voltage range is smaller than V _K. FIG.
An output conductance characteristic obtained by differentiating the differential output current ΔI calculated using the hyperbolic tangent function with the input voltage V ₁ ,
It shows a gain characteristic of a multiplier (multiplier).

FIG. 6 shows an experimental result when k = 7 and individual components (transistor 2SC2785) are used. That is, in FIG. 2, the transistors (Q2, Q3, Q6, Q7) of k = 1 are one 2SC278.
5, k = 7 transistors (Q1, Q4, Q5,
Q8) uses seven 2SC2785s connected in parallel. The other input voltage V is used as a parameter.
₂ is adopted, this is changed from 0 mV to 100 mV in steps of 20 mV, and the relationship between _one input voltage V1 and the output voltage (VM1, VM2) is plotted. In FIG. 6, the output voltages (VM1, V1
M2) is the two differential output currents (I _p , I _q ) in FIG.
Line resistance R _L is inserted into _{the, VM1 = V CC -R L ·} I
_p, is obtained by voltage conversion as _{VM2 = V CC -R L · I} q.

Since the output is realized by the individual components, an offset appears in the output to some extent, but it can be understood that good multiplier (multiplier) output characteristics are obtained.

Next, FIG. 2 shows a case in which each of the main components is composed of only two transistors having different emitter sizes as two sets of unbalanced differential pairs forming a squaring circuit. Balanced differential pair (ie, one squaring circuit)
Can be configured as shown in FIG. 7, FIG. 10, FIG. 13 and FIG.

The squaring circuit shown in FIG. 7 is obtained by adding an emitter resistance in inverse proportion to the emitter size ratio to the emitter of each transistor of the two unbalanced differential pairs shown in FIG. Specifically, an unbalanced pair transistor (Q1,
In Q2), a resistor R / k is added to the emitter of Q1, and a resistor R is added to the emitter of Q2. Similarly,
In an unbalanced pair transistor (Q3, Q4), a resistor R is added to the emitter of Q3, and a resistor R / k is added to the emitter of Q4. Other configurations are the same as those shown in FIG. The differential output current (I _k , I _u ) has been described above.

[0087] squaring circuit shown in FIG. 7, since includes an emitter resistor to a transistor of the unbalanced differential pairs, it is difficult to understand the operation analytically, the emitter resistor R and the driving current I ₀ When the relationship between the differential output current (I _k , I _u ) and the input voltage _VA when k = 3 with the product RI ₀ as a parameter is obtained by SPICE simulation, the result is as shown in FIG. It can be understood that it can be obtained. At this time, it should be noted that FIG. 8 shows that by appropriately selecting the value of the product RI ₀ , the input voltage range can be expanded while maintaining good square characteristics.

This is clearly shown in FIG. FIG. 9 shows an experimental result in a case where k = 3 and RI ₀ ≒ 8.6 V _T are used by using individual components (transistor 2SC2785). Although an offset appears in the output, good multiplier (multiplier) output characteristics can be obtained, and the input voltage range is expanded to about three times as compared with FIG.

FIG. 9 employs the other input voltage V ₂ as a parameter, and sets this to 0 m in steps of 100 mV.
mV to 400 mV, and one input voltage V ₁
7 is a plot of the relationship between the output voltages (VM1, VM2).

Next, the squaring circuit shown in FIG. 10 is obtained by adding an emitter resistor to only one of the paired transistors in the two unbalanced differential pairs shown in FIG. Specifically, in Q1 and Q2, for example, a resistor R is added only to the emitter of Q2, and in Q3 and Q4, a resistor R is added only to the emitter of Q3, for example. Other configurations are the same as those shown in FIG.

Since the squaring circuit shown in FIG. 10 has an emitter resistor in the transistor of the unbalanced differential pair similarly to the squaring circuit shown in FIG. 7, it is difficult to analytically understand the operation. Using the product RI ₀ of the emitter resistance R and the drive current I ₀ as a parameter, the differential output current (I _k ,
When the relationship between I _u ) and the input voltage V _A is obtained by SPICE simulation, the result is as shown in FIG. 11, and it can be understood that good square characteristics can be obtained similarly to the square circuit shown in FIG. At this time, it should be noted that the effect of expanding the input voltage range is greater than that of the square circuit shown in FIG.

FIG. 12 is similar to FIG. 9 except that k = 3 and RI ₀ ≒
Discrete components as 8.6V _T (transistor 2SC278
The experimental results in the case of using 5) are shown. Since the realization is realized by individual components, a good output characteristic of the multiplier (multiplier) can be obtained although an offset appears in the output to some extent. The voltage range is expanded about four times as compared with FIG.

FIG. 12 employs the other input voltage V ₂ as a parameter as in FIG.
Varied in steps from 0mV to 400 mV, plots the relationship between one of the input voltages V ₁ and the output voltage (VM1, VM2).

Next, in the squaring circuit shown in FIG. 13, each of the two unbalanced differential pairs has the same emitter size.
One is mainly composed of two transistors having no emitter resistance and the other is having no emitter resistance.

Here, it should be noted that the reference numerals of the transistors are merely identification codes valid only in the figure and do not mean that they are the same as the transistors having the same reference numerals in other drawings.

That is, in FIG. 13, Q1, Q2, Q
3, Q4 are transistors having the same emitter size, and Q1 and Q2, and Q3 and Q4 are constant current sources I and I, respectively.
_Although a differential pair driven by ₀ is formed, an emitter resistor R is added to only one transistor (Q2, Q3) in each differential pair. That is, it is an unbalanced differential pair.

Then, between the two unbalanced differential pairs, a transistor Q2 (Q
3) Transistor Q without base and emitter resistance
4 (Q1) are commonly connected to each other to form a differential input pair to which an input voltage _VA is applied, and the collectors of transistors (Q2, Q3) having an emitter resistance and a transistor (not having an emitter resistance) ( Q1, Q4)
Are commonly connected to each other to form a differential output pair in which differential output currents (I _k , I _u ) flow.

Since the squaring circuit shown in FIG. 13 has an emitter resistor in the transistor of the unbalanced differential pair similarly to the squaring circuit shown in FIG. 7, it is difficult to analytically understand the operation, but , Product RI of emitter resistance R and drive current I _0
0 as a parameter k = 3 in the case of the differential output current (I
_k , I _u ) and the input voltage _VA are obtained by SPICE simulation as shown in FIG.
It can be understood that good square characteristics can be obtained similarly to the square circuit shown in FIG. At this time, the effect of expanding the input voltage range is
As shown in FIG. 15, the same degree as the squaring circuit shown in FIG.
Times).

FIG. 15 shows an experimental result when an individual component (transistor 2SC2785) is used for RI ₀ ≒ 8.6 V _T , which is the same as FIGS. 9 and 12 because it is realized by an individual component. However, although an offset appears in the output to some extent, a good multiplier (multiplier) output characteristic is obtained, and the input voltage range is expanded to about three times as compared with FIG.

FIG. 15 employs the other input voltage V ₂ as a parameter, as in FIGS.
In 0mV steps is changed from 0mV to 400 mV, one input voltages V ₁ and the output voltage (VM1, VM2)
This is a plot of the relationship with.

Next, the squaring circuit shown in FIG.
In the square circuit shown in (2), (Q1, Q2) and (Q3, Q
In each of the paired transistors 4), the transistors (Q1, Q4) having no emitter resistance R are replaced with Darlington-connected transistors. In the illustrated example, Q1
Is replaced by one in which two of Q1a and Q1b are connected in Darlington, and Q4 is replaced by one in which two of Q4a and Q4b are connected by Darlington.

Then, between the two unbalanced differential pairs, a transistor Q2 (Q
The base (3) and the base of the input stage transistor Q4a (Q4b) of the Darlington connection transistor are commonly connected to form a differential input pair to which the input voltage _VA is applied, and the transistors (Q2, Q2)
The collectors of 3) and the collectors of the Darlington connection transistors are commonly connected to each other to form a differential output pair from which differential output currents (I _k , I _u ) are taken out.

The squaring circuit shown in FIG. 16 has an emitter resistance in the transistor of the unbalanced differential pair similarly to the squaring circuit shown in FIG. 7 and the like, so that it is difficult to analytically understand the operation. Is the product R of the emitter resistance R and the drive current I ₀
When the relationship between the differential output current (I _k , I _u ) and the input voltage V _A is obtained by SPICE simulation using I ₀ as a parameter, the result is as shown in FIG. 17, which is as good as the square circuit shown in FIG. It can be understood that a square characteristic is obtained. At this time, the effect of expanding the input voltage range is larger than that of the square circuit shown in FIG. 7 as shown in FIG.

FIG. 18 shows an experimental result when an individual component (transistor 2SC2785) is used for RI ₀ ≒ 8.6 V _T , but since it is realized by an individual component, it is somewhat similar to FIG. Although an offset appears in the output, good multiplier (multiplier) output characteristics can be obtained, and the input voltage range is expanded to about 5 times as compared with FIG.

In FIG. 18, similarly to FIG. 9, etc., the other input voltage V ₂ is adopted as a parameter, and this is set to 100 mV.
Varied in steps from 0mV to 400 mV, plots the relationship between one of the input voltages V ₁ and the output voltage (VM1, VM2).

Next, FIG. 19 shows a multiplier according to an embodiment of the ninth invention. This multiplier basically has a constant current source I having emitters connected in common and having the same value, as shown in FIG. 2 which is an embodiment of the first invention.
_The paired transistors (Q1, Q2) driven by ₀ ,
3, Q4), same (Q5, Q6), same (Q7, Q8)
It is composed mainly of pairs.

As in the multiplier shown in FIG. 2, each pair of transistors receives the power supply in parallel, but one of the transistors (Q2, Q3, Q6,
Assuming that the emitter size of Q7) is 1, the emitter size of the other transistor (Q1, Q4, Q5, Q8) is k
(K> 1) times. That is, each of the four pairs of transistors constitutes an unbalanced differential pair.

The difference from the multiplier shown in FIG.
Two input signals (voltages V ₁ and V ₂ ) are applied in full differential to the differential input terminal pairs (1, 2) and (3, 4), and the above four sets of unbalances The connection between the transistors forming the main part of the differential pair is as follows.

Between the transistors constituting the main components of the four unbalanced differential pairs, transistors having unequal emitter sizes (Q1 and Q7, Q2 and Q5, Q3 and Q8,
The bases of Q4 and Q6) are commonly connected to each other,
1 and Q7 have one differential input terminal pair (1,
2) connected to the input terminal 1 of one polarity, and Q2 and Q5
Are connected to the other polarity input terminal 2 of one differential input terminal pair (1, 2). The bases of Q3 and Q8 are connected to the input terminal 3 of one polarity of the other differential input terminal pair (3, 4), and the bases of Q4 and Q6 are connected to the other differential input terminal pair (3, 4). 4) is connected to the input terminal 4 of the other polarity. The four transistors (Q1, Q4, Q5, Q8) and the collectors (Q2, Q3, Q6, Q7) having the same emitter size are commonly connected to each other, and the differential output currents (I _p , I _q ) are respectively provided. ) Is formed.

Now, each transistor (Q1, Q2) of the (first) unbalanced differential pair, each transistor (Q3, Q4) of the (second) unbalanced differential pair, (third) unbalanced The respective base voltages (V _B1 , V _B2 , V _B3 , V _B4 , V _B5 ) of each transistor (Q7, Q8) of the differential pair and each transistor (Q5, Q6) of the (fourth) unbalanced differential pair V _B6 , V _B7 , V
_B8), when the reference voltage is V _R, the following equation 34, 3
5, 36 and 37.

[0111]

(Equation 34)

[0112]

(Equation 35)

[0113]

[Equation 36]

[0114]

(37)

At this time, the base-to-base voltage of each transistor (Q1, Q2) of the (first) unbalanced differential pair and each transistor (Q3, Q2) of the (second) unbalanced differential pair
The voltage between bases in 4) is expressed by the following equation 38, respectively.
The result is 39, which is equal to the expression 40. This is V
_A.

[0116]

(38)

[0117]

[Equation 39]

[0118]

(Equation 40)

Similarly, the base-to-base voltage of each transistor (Q7, Q8) of the (third) unbalanced differential pair and each transistor (Q5, Q5) of the (fourth) unbalanced differential pair
The base-to-base voltage in 6) is given by
42 is obtained, and both are equally represented by Expression 43. This is V
_B.

[0120]

[Equation 41]

[0121]

(Equation 42)

[0122]

[Equation 43]

Therefore, if V _A and V _B are substituted into Expression 30, the following Expression 44 is obtained, and a differential current proportional to the product of the input voltage V ₁ and V ₂ is obtained. That is, a multiplier was obtained.

[0124]

[Equation 44]

In FIGS. 2 and 19, the differential current Δ
I is expressed as [Delta] I = I _p -I _q, include current components I _p and I _q and the product of the voltages V ₁ and the V ₂ in any of these from is opposite phases. However, its magnitude is only half of the differential current ΔI.

As is clear from the above description,
The unbalanced differential pairs shown in FIG. 19 correspond to FIGS.
0, and can be replaced with the unbalanced differential pairs shown in FIGS.

Next, FIG. 20 shows a multiplier according to the second invention. In FIG. 20, the multiplier basically includes three squaring circuits A, B, and C. Each squaring circuit, as in the first invention, has a so-called unbalanced differential pair of two.
It has a differential input / output pair because it is configured as a set, but since the two input signals are multiplied by the cooperation of three squaring circuits,
The positive side of the differential input pairs of the three squaring circuits is commonly connected to the input terminal 10, the negative side of the differential input pair of the squaring circuit A is connected to the input terminal 11, and B and C The negative side of the differential input pairs of the two squaring circuits is commonly connected to the input terminal 12.

That is, the differential input pair of the (first) squaring circuit A is composed of the (first) input terminal 10 and the (second) input terminal 11
The differential input pair of the (second) squaring circuit B and the differential input pair of the (third) squaring circuit C are respectively (first
1) and (third) input terminal 12).

Then, between the three squaring circuits, 2
The positive side of the differential output pair of the squaring circuit A is connected to the negative side of the differential output pair of the squaring circuit of B and C, and the squaring circuit A
Are connected to the positive side of the differential output pair of the squaring circuit of B and C, and are respectively connected to the output terminal pair (13, 14) of the multiplier.

That is, the (second) squaring circuit B and the (third)
) Of the differential output pair of the squaring circuit C and the different polarity of the differential output pair of the (first) squaring circuit A are connected in common to form the output terminal pair (13, 14). It is composed.

In the above configuration, the (first) input voltage signal V ₁ is applied between the (first) input terminal 10 and the (third) input terminal 12, and the (second) input terminal 11 and the (second) input terminal A second input voltage signal V ₂ is applied between the (third) input terminals 12 in the same phase. Therefore, the differential input voltage of the squaring circuit A is V ₁ −V ₂ . On the other hand, the differential input voltage of the square circuit of B and C becomes V ₂ .

As is clear from the connection relationship between the output terminal pairs of the three squaring circuits, the output of the squaring circuit A is subtracted from the sum of the outputs of the squaring circuits of B and C. The output voltage V _OUT appearing in the pair is expressed by the product of the input voltage V ₁ and the same voltage V ₂ as shown in Expression 45, and a characteristic of a multiplier (multiplier) is obtained.

[0133]

[Equation 45]

Next, FIG. 21 shows an embodiment of the multiplier according to the second invention in the case where the unbalanced differential pair is constituted mainly by two transistors having different emitter sizes.
In FIG. 21, (Q1, Q2) (Q3, Q4) (Q
5, Q6) (Q7, Q8) (Q9, Q10) (Q11,
Six sets of pairs transistor Q12), respectively, with parallel supplied with power, is a differential pair whose emitters each other is driven by a constant current source I ₀ equal commonly connected with values, the emitter size Is one transistor (Q2,
Assuming that Q3, Q6, Q7, Q10, Q11) is 1, the other transistors (Q1, Q4, Q5, Q8, Q9, Q
12) is k (k> 1) times. That is, each differential pair is unbalanced, and two sets of (Q1, Q2) and (Q3, Q4) are (Q5, Q6) (Q7, Q
8), and two sets of (Q9, Q10) and (Q11, Q12) each constitute a main part of the squaring circuit.

Each of the above-mentioned three squaring circuits 2
The transistors having the same emitter size (Q1 and Q4, Q2 and Q3, Q5 and Q8, Q6 and Q7, Q9 and Q12, Q10)
And Q11) have commonly connected collectors and unequal emitter sizes (Q1 and Q3, Q2 and Q11).
4, Q5 and Q7, Q6 and Q8, Q9 and Q11, and Q10 and Q12) are commonly connected.

The input relationship between the three squaring circuits is as follows. That is, the base of one transistor (Q1, Q3) of the paired transistors ((Q1 and Q2) and (Q3 and Q4)) of the two unbalanced differential pairs forming the first square circuit and the second transistor The paired transistors of the two unbalanced differential pairs ((Q5
, Q6) and (Q7 and Q8)), the base of one transistor (Q5, Q7) is commonly connected to the input terminal 1, and the other transistor (Q5) in the first squaring circuit.
2, Q4) and two unbalanced differential pair pair transistors ((Q10 and Q9) forming a third squaring circuit).
(Q12 and Q11)) in the other transistor (Q
9, Q11) are commonly connected to the input terminal 2;
The other transistors (Q6, Q6) in the second square circuit
The base of 8) and the base of one of the transistors (Q10, Q12) in the third squaring circuit are commonly connected to the input terminal 3.

The output relationship between the three squaring circuits is as follows. That is, in the second and third squaring circuits, the collectors of Q5, Q8, Q9, and Q12 having the same emitter size and the collectors of Q6, Q7, Q10, and Q11 are connected in common, respectively, In the circuit, the differential output current (I
_p ', _Iq ').

One input voltage signal V ₁ is applied between the input terminals 1 and 3, and the other input voltage signal V ₂ is applied between the input terminals 2 and 3. As shown in the drawing, one polarity of two input signals is applied to input terminals 1 and 2 respectively, and the other polarity is commonly applied to input terminal 3.

In the above configuration, ((Q1, Q2)
(Q3, Q4)), ((Q5, Q6) (Q7, Q
8)), ((Q9, Q10) (Q11, Q12))
The two sets of unbalanced pair transistors are the main components of the squaring circuit (two sets of unbalanced differential pairs).
2) (Q3, Q4)) and ((Q5, Q6) (Q7, Q
8)) is the same as that described above (FIG. 2), so that (Q9, Q10) and (Q11, Q1)
2) will be described.

The collector current of each transistor (Q9, Q10, Q11, Q12) of the two mismatched differential pairs is represented by I
_Assuming that _C9 , I _C10 , I _C11 , and I _C12 , I _C9 -I _C10 is obtained by Expression 46, and I _C11 -I _C12 is obtained by Expression 47, and the differential current ΔI _C of both mismatched differential pairs is obtained by Expression 48. As shown,
Proportional to the square of the input voltage V _2.

[0141]

[Equation 46]

[0142]

[Equation 47]

[0143]

[Equation 48]

Therefore, assuming that the difference (I _p ′, I _q ′) between the differential output currents in FIG. 21 is ΔI ′, this is represented by the following equation (49), which can be approximated to equation (50).

[0145]

[Equation 49]

[0146]

[Equation 50]

That is, a differential current (ΔI ′) proportional to the product of the input voltage V ₁ and the input voltage V ₂ was obtained, and a multiplier (multiplier) was obtained.

Next, FIG. 22 shows a multiplier according to the third invention. In FIG. 22, this multiplier is obtained by adding a fourth squaring circuit D to the configuration of the multiplier (second invention) shown in FIG.

The additional squaring circuit D is for positively canceling the DC component in the multiplier of the second invention, and the differential input pair of the additional squaring circuit D is the negative polarity of the third squaring circuit C. And the differential output pair is connected to the same polarity side of the first squaring circuit, that is, the positive side is connected to the output terminal 13 and the negative side is connected to the output terminal 14. Connected.

Next, FIG. 23 shows an embodiment of the multiplier according to the third invention in the case where the unbalanced differential pair mainly includes two transistors having different emitter sizes.
In FIG. 23, (Q1, Q2) (Q3, Q4) (Q
5, Q6) (Q7, Q8) (Q9, Q10) (Q11,
Q12) (Q13, Q14) ( Q15, Q16 8 sets of pairs transistor), respectively, with parallel supplied with power, the emitters of is driven by a constant current source I ₀ equal commonly connected to values However, the emitter size of one of the transistors (Q2, Q3, Q6, Q
7, Q10, Q11, Q14, Q15) as 1,
The other transistor (Q1, Q4, Q5, Q8, Q9,
Q12, Q13, and Q16) are k times (k> 1). That is, each differential pair is unbalanced, and two sets of (Q1, Q2) and (Q3, Q4) are represented by (Q
5, Q6) and (Q7, Q8) are (Q9, Q1
0) and (Q11, Q12) are (Q13, Q1
The two sets of 4) and (Q15, Q16) respectively constitute the main part of the squaring circuit.

As is apparent from comparison with FIG.
The multiplier shown in FIG. 23 includes two sets of unbalance differences between the transistor Q8 in the second square circuit and the transistor Q12 in the third square circuit in FIG. Dynamic pair transistor ((Q1
3, Q14) and (Q15, Q16)).

Each of the four squaring circuits 2
Each transistor of the set of mismatched differential pairs is composed of transistors having the same emitter size (Q1 and Q4, Q2 and Q3, Q5
Q8, Q6 and Q7, Q9 and Q12, Q10 and Q11,
Q13 and Q16, Q14 and Q15 collectors and transistors having unequal emitter sizes (Q1 and Q15)
3, Q2 and Q4, Q5 and Q7, Q6 and Q8, Q9 and Q1
1, Q10 and Q12, Q13 and Q15, Q14 and Q1
6) The bases are commonly connected to each other.

The input relationship between the four squaring circuits is as follows. The paired transistors ((Q1, Q2) of the two mismatched differential pairs forming the first squaring circuit
2) and (Q3, Q4)), the bases of one transistor (Q1, Q3) and two mismatched differential pair pair transistors ((Q5, Q5) forming a second squaring circuit.
6) and the bases of one of the transistors (Q5, Q7) in (Q7, Q8)) are commonly connected to the input terminal 1. The bases of the other transistors (Q2, Q4) in the first square circuit and the paired transistors ((Q9, Q1) of two mismatched differential pairs forming the third square circuit
0) and the bases of the other transistors (Q9, Q11) in (Q11, Q12)) are commonly connected to the input terminal 2. The bases of the other transistors (Q6, Q8) in the second squaring circuit and the paired transistors ((Q13,
Q14) and the base of one of the transistors (Q14, Q16) in (Q15, Q16))
Connected in common. The bases of one transistor (Q12, Q10) in the third squaring circuit and the bases of the other transistors (Q13, Q15) in the fourth squaring circuit are commonly connected.

The output relation between the four squaring circuits is as follows. That is, between the first to third squaring circuits, as in FIG.
Q5 and Q8 having the same emitter size in the squared circuit of
, Q9 and Q12 collectors and Q6, Q7 and Q10
And Q11 are commonly connected to each other, each is connected to the collector of a transistor having a different emitter size in the first squaring circuit, and an additional fourth squaring circuit has a transistor (( The collectors of Q14 and Q15) (Q13 and Q16)) are similarly connected in common, but the collectors of Q14 and Q15 having an emitter size of 1 are Q2 and Q3.
, Q5, Q8, Q9, and Q12 are commonly connected to each other, and the collectors of Q13 and Q16 whose emitter size is k are connected to Q1, Q4, Q6, Q7, Q10, and Q11.
Are connected in common to each other to form differential output currents (I _p ″, I _q ″), respectively.

One input signal (voltage V ₁ ) is applied between the input terminals 1 and 3, and the other input signal (voltage V ₂ ) is applied between the input terminals 2 and 3. ,
As in the case of FIG. 21, one polarity of two input signals is respectively applied to the input terminals 1 and 2 and the other polarity is commonly applied to the input terminal 3.

In the above configuration, the fourth 2
In the multiplication circuit, the paired transistors (Q
13, Q14), for the same (Q15, Q16), the collector current (I _C13, I _C14), the (I _C15, the difference in I _C16) current (I _C13 -I _C14), the (I _C16 -I _C15) Is
Equation 51, Motomari the same 52, the difference current [Delta] I _D of both the formula 53.

[0157]

(Equation 51)

[0158]

(Equation 52)

[0159]

(Equation 53)

Therefore, in FIG. 23, the output current I
_p ", the I _q" when the difference of (I _p "-I _q") to [Delta] I ", which is next to the following formula 54, can be canceled dc term in the equation 50, it eventually approximate formula 55.

[0161]

(Equation 54)

[0162]

[Equation 55]

That is, similarly to the second invention, a differential current (ΔI ″) proportional to the product of the input voltage V ₁ and the input voltage V ₂ is obtained,
A multiplier (multiplier) was obtained. In addition,
The characteristic of the circuit according to the third invention (FIG. 23) is shown in FIG.
As shown in FIG. FIG. 24 is a plot of calculated values using a hyperbolic tangent function.

Each of the unbalanced differential pairs shown in FIGS. 21 and 23 can be replaced with the unbalanced differential pairs shown in FIGS. 7, 10, 13 and 16, respectively. Is apparent from the above description.

[0165]

As described above, in the multiplier of the present invention, the squaring circuit is constituted by two unbalanced differential pairs,
The two sets (first invention, ninth invention) or three sets (second invention) or four sets (third invention) of the squaring circuit are arranged so as to be in a horizontal row rather than stacked as in the prior art,
Since the operation is performed at the same power supply voltage, there is an effect that the operation can be performed at a power supply voltage lower than the conventional one. And
In the case where two sets (fourth and tenth inventions) of unbalanced differential pairs mainly composed of two transistors having different emitter sizes are used as the squaring circuit, the fifth invention, the eleventh invention, the sixth invention and The twelfth invention, the seventh invention and the thirteenth invention, and the eighth invention and the fourteenth invention can obtain the effect of expanding the input voltage range.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a multiplier of a first invention.

FIG. 2 is a circuit diagram of a multiplier according to an embodiment of the first invention (first embodiment of a squaring circuit (two unbalanced differential pairs) of the present invention);
It is a circuit diagram of an Example).

FIG. 3 is an output characteristic diagram of the squaring circuit (FIG. 2) according to the first embodiment;

FIG. 4 is an output characteristic diagram (calculated value) of the multiplier (FIG. 2) according to one embodiment of the first invention.

FIG. 5 is an output conductance characteristic diagram (calculated value) of the multiplier (FIG. 2) according to one embodiment of the first invention.

FIG. 6 is an output characteristic diagram (experimental value) of the multiplier (FIG. 2) according to the embodiment of the first invention.

FIG. 7 is a circuit diagram of a second embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention.

8 is an output characteristic diagram (simulation value) of the circuit (FIG. 7) of the second embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention.

FIG. 9 is an output characteristic diagram (experimental value) of the multiplier of the first invention configured using the circuit (FIG. 7) of the second embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention; is there.

FIG. 10 is a circuit diagram of a third embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention.

FIG. 11 is an output characteristic diagram (simulation value) of the circuit (FIG. 10) of the third embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention.

12 is an output characteristic diagram (experimental value) of the multiplier of the first invention configured using the circuit (FIG. 10) of the third embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention; is there.

FIG. 13 is a circuit diagram of a fourth embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention.

FIG. 14 is an output characteristic diagram (simulation value) of the circuit (FIG. 13) of the fourth embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention.

FIG. 15 is an output characteristic diagram (experimental value) of the multiplier of the first invention configured using the circuit (FIG. 13) of the fourth embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention; is there.

FIG. 16 is a circuit diagram of a fifth embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention.

17 is an output characteristic diagram (simulation value) of the circuit (FIG. 16) of the fifth embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention.

FIG. 18 is an output characteristic diagram (experimental value) of the multiplier of the first invention configured using the circuit (FIG. 16) of the fifth embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention; is there.

FIG. 19 is a configuration block diagram of a multiplier according to an embodiment of the ninth invention.

FIG. 20 is a block diagram showing a configuration of a multiplier according to the second invention.

FIG. 21 is a circuit diagram in which the multiplier of the second invention is configured using the circuit of the first embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention.

FIG. 22 is a configuration block diagram of a multiplier of the third invention.

FIG. 23 is a circuit diagram in which the multiplier of the third invention is configured using the circuit (FIG. 2) of the first embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention.

24 is an output characteristic diagram (FIG. 23) of the multiplier (FIG. 23) of the third invention configured using the circuit (FIG. 2) of the first embodiment of the squaring circuit (two sets of unbalanced differential pairs) of the present invention; (Calculated value).

FIG. 25 is a circuit diagram of a conventional multiplier.

[Explanation of symbols]

1 to 3 input terminals 10 to 12 input terminals 13 output terminals 14 output terminals A square circuit B square circuit C square circuit D square circuit I ₀ constant current source Q1 to Q16 Transistor

Claims (14)

(57) [Claims] A pair of squaring circuits composed of two sets of unbalanced differential pairs; and a differential input pair of one of the squaring circuits has a relationship between two input voltage signals having phases opposite to each other. Applied at;
The two input voltage signals are applied to the differential input pair of the other squaring circuit in an in-phase relationship with each other; A common connection to form an output terminal pair; 2. A three-square circuit comprising two sets of unbalanced differential pairs, wherein a first input terminal and a second input terminal are differential input pairs. A squared circuit, a second squared circuit having a first input terminal and a third input terminal as a differential input pair,
And a third squaring circuit having a second input terminal and a third input terminal as a differential input pair; and a first input between the first input terminal and the third input terminal. A voltage signal is applied between the second input terminal and the third input terminal in a second input voltage signal, respectively, in phase; between the three sets of squaring circuits, the second and third input signals are applied; The same polarity of the differential output pair of each of the squared circuits and the different polarity of the differential output pair of the first squared circuit are commonly connected to form an output terminal pair; . 3. A four-square circuit comprising two sets of unbalanced differential pairs, wherein the first and second input terminals have a first input terminal and a second input terminal as a differential input pair. A squared circuit, a second squared circuit having a first input terminal and a third input terminal as a differential input pair,
A third squaring circuit having a second input terminal and a third input terminal as a differential input pair, and a fourth squaring circuit having the third input terminal as a differential input pair. A first input voltage signal is applied between a first input terminal and the third input terminal, and a second input voltage signal is applied between the second input terminal and the third input terminal in the same phase. Between the four sets of squaring circuits, the same polarity of the differential output pairs of the second and third squaring circuits and the different polarity of the differential output pairs of the first squaring circuit. Are connected in common to form an output terminal pair, and the differential output pair of the fourth square circuit is the first 2
Respectively connected to the same polarity side of the differential output pair of the multiplying circuit;
A multiplier characterized by the following. 4. The method according to claim 1, 2 or 3.
Wherein the two sets of unbalanced differential pairs forming the squaring circuit each include two transistors having different emitter sizes; and between the two sets, one having a larger emitter size is used. And the bases of the transistors with smaller emitter sizes are connected together to form a differential input pair; the collectors of transistors with larger emitter sizes and the collectors of transistors with smaller emitter sizes Are commonly connected to each other to form a differential output pair; 5. The method according to claim 1, 2 or 3.
Wherein the two sets of unbalanced differential pairs forming the squaring circuit are two transistors each having a different emitter size and having an emitter resistance added to each emitter which is inversely proportional to the emitter size ratio. Between the two sets, the base of the transistor with the larger emitter size and the base of the transistor with the smaller emitter size are commonly connected to each other to form a differential input pair; A collector of the other transistor and a collector of the transistor having a smaller emitter size are commonly connected to each other to form a differential output pair; 6. The method according to claim 1, wherein the first and second embodiments are arranged in parallel with each other.
The two sets of unbalanced differential pairs forming the squaring circuit each include two transistors having different emitter sizes, one having an emitter resistance and the other having no emitter resistance. Between the two sets, the base of the transistor with the larger emitter size and the base of the transistor with the smaller emitter size are commonly connected to each other to form a differential input pair; the transistor with the larger emitter size And the collectors of the transistors having the smaller emitter size are commonly connected to each other to form a differential output pair. 7. The method according to claim 1, 2 or 3.
Wherein the two sets of unbalanced differential pairs forming the squaring circuit are respectively two transistors having the same emitter size, one having an emitter resistance and the other having no emitter resistance. Two transistors; between the two sets, a base of a transistor having an emitter resistance and a base of a transistor having no emitter resistance are commonly connected to each other to form a differential input pair; and having an emitter resistance. A multiplier, wherein the collectors of the transistors and the collectors of the transistors having no emitter resistance are commonly connected to each other to form a differential output pair; 8. The method of claim 1 or claim 2 or claim 3.
Wherein the two sets of unbalanced differential pairs forming the squaring circuit each include a transistor having an emitter resistance and a Darlington-connected transistor; The base of the transistor having a resistance and the base of the Darlington-connected transistor are connected in common to form a differential input pair; the collectors of the transistors having the emitter resistance and the collectors of the Darlington-connected transistors are connected in common, respectively. A multiplier comprising: a differential output pair; 9. Two sets of squaring circuits each comprising two sets of unbalanced differential pairs; and a first unbalance in the first and second unbalanced differential pairs of one of the squaring circuits. A first input voltage signal is applied between one input terminal of the differential pair and one input terminal of the second unbalanced differential pair, and the other input terminal of the first unbalanced differential pair is connected to the other input terminal. A second input voltage signal is applied between the second input terminal of the second unbalanced differential pair and a third input terminal of the other unbalanced differential pair;
And a second input voltage signal is applied between one input terminal of the third unbalanced differential pair and one input terminal of the fourth unbalanced differential pair in the fourth unbalanced differential pair. , A first input voltage signal is applied between the other input terminal of the third unbalanced differential pair and the other input terminal of the fourth unbalanced differential pair; Among them, those having different polarities of the respective differential output pairs are commonly connected to form an output terminal pair;
A multiplier characterized by the following. 10. The multiplier according to claim 9, wherein each of the two sets of unbalanced differential pairs forming the squaring circuit includes two transistors having different emitter sizes. Between the collectors of the transistors having the larger emitter size and the collectors of the transistors having the smaller emitter size are commonly connected to each other to form a differential output pair; A base of a transistor, wherein the other input terminal is a base of a transistor having a smaller emitter size; 11. The multiplier according to claim 9, wherein the two sets of unbalanced differential pairs forming the squaring circuit have different emitter sizes, respectively, and are inversely proportional to the ratio of the emitter size to each emitter. Two transistors each having an emitter resistor added thereto; and between the two sets, the collectors of the transistors having the larger emitter size and the collectors of the transistors having the smaller emitter size are connected in common to each other so that a differential output is obtained. A pair, wherein the one input terminal is a base of a transistor having a larger emitter size, and the other input terminal is a base of a transistor having a smaller emitter size. 12. The multiplier according to claim 9, wherein the two sets of unbalanced differential pairs forming the squaring circuit have different emitter sizes, one having an emitter resistance, and the other having an emitter resistance. A collector having a larger emitter size and a collector having a smaller emitter size are commonly connected to form a differential output pair between the two sets. The one input terminal is a base of a transistor having a larger emitter size, and the other input terminal is a base of a transistor having a smaller emitter size. 13. The multiplier according to claim 9, wherein the two sets of unbalanced differential pairs forming the squaring circuit are two transistors having the same emitter size, and one of the two sets has an emitter resistance. And two transistors having no emitter resistance;
Between the pairs, the collectors of the transistors having emitter resistance and the collectors of the transistors having no emitter resistance are commonly connected to each other to form a differential output pair; the one input terminal is connected to the transistor having the emitter resistance. A base, wherein the other input terminal is a base of a transistor having no emitter resistance; 14. The multiplier according to claim 9, wherein each of the two sets of the unbalanced differential pairs forming the squaring circuit includes a transistor having an emitter resistance and a Darlington-connected transistor; Between the pairs, the collectors of the transistors having emitter resistance and the collectors of the Darlington-connected transistors are connected together to form a differential output pair; the one input terminal is the base of the transistor having emitter resistance. Wherein the other input is the base of a Darlington-connected transistor;