JP2901548B2 - 1-bit DAC control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a DAC used for voice, video, communication, etc.
The present invention relates to a tDAC control circuit.

[0002]

2. Description of the Related Art FIG. 9 shows an example of a conventional 1-bit DAC, and its operation is shown in FIG.

[0003] Data input from an input terminal 1 for inputting a digital signal is supplied to a digital filter (hereinafter referred to as DF) 2 for oversampling.

In the DF2, the supplied digital data is oversampled, and the sampling frequency is raised to a positive multiple.

[0005] The data oversampled by the DF 2 is supplied to the NS 5 via the adder 4 to compress the number of bits per sample.

[0006] By this noise shaping processing, the reduced quantization noise is driven to a higher frequency, and the S / N ratio in the audible band is improved.

In the adder 4, the over-sampled data is supplied from the DC offset generation circuit 11 by the DC offset generation circuit 11.
A process of adding a constant DC component (DC value) is performed.

This addition processing is used for stably performing the bit compression processing in NS5, and always adds a small-level DC value.

(If this process is not performed, a noise that generates a whirlpool when a minute signal is input is generated.) The digital data to which the DC offset is added is bit-compressed by NS5 and 1-bit D / A conversion is performed. Circuit 6
And converted to 1-bit (binary 0 and 1) pulse data, which is supplied to a pulse data output terminal 9.

In this NS, if digital data 0
.. Are not alternated with 101010..., For example, 0011100011010
.., And the integrated value becomes 0, resulting in a poor S / N ratio. As a remedy, when digital data 0 continues, the output is 010
A circuit (duty 50%)
Generation circuit), but in the NS that already has a DC offset, if the level is switched from the 0 level with the offset to the original 0 level with a duty of 50%, a large noise such as “BOT !!” is generated. There was a problem that it would. (See FIG. 10) However, as a countermeasure against this, Japanese Patent Laid-Open No.
There are five.

The structure and operation will be described below with reference to FIG.
14195 (FIG. 14195) and FIG. 12 will be briefly described.

Dither (pseudo noise) is injected into the input side of the noise shaper, and when the input level becomes 0, 1 bit D
It is an object of the present invention to provide a D / A converter capable of fixing the duty of the output pulse of the / A converter to 50% and effectively preventing transient noise.

A digital signal from an oversampling digital filter is supplied to an input terminal 1. The input signal is sent to a noise shaper 5 via an adder 4 and subjected to a noise shaping process. The output from the 1-bit D / A converter 6 is input through an output terminal 9.

The dither from the dither generator 15 is supplied to the adder 4, and the dither is added to the digital data from the input terminal 1. This adds dither (pseudo noise) to prevent a fixed pattern from being generated for a minute input signal.

The 1-bit D / A converter 6 outputs a pulse with a duty of 50% when the input data is 0.

Here, measures against the above pop noise will be described.

This D / A conversion circuit has added dither to stably perform NS bit compression processing.

This dither is a pseudo noise generated from the dither generator 15, and is therefore a direct current component (DC component) and an alternating current component (A
C component). The DC component is gradually reduced, and then the AC component is gradually attenuated. As a method of muting a DC component, for example, a down counter is provided and 1 L
The counter is down-counted by SB (this is included in the control circuit 16).

The AC component is configured to control the quantization step width inside the NS5. When the quantization step is multiplied by k, the output is controlled to be 1 / k times and the 1-bit D / A is controlled. The input of the converter 6 is attenuated to eliminate pseudo noise.

As a result, the duty is smoothly switched to 50% as shown in FIG.

[0021]

The first problem is that the conventional technique has a DC offset to switch to a duty of 50% in order to sacrifice or improve the S / N ratio. I had to put up with it even if there was a click.

On the other hand, Japanese Patent Laid-Open Publication No.
As can be seen from FIG. 12, no noise is generated when the duty is switched to 50%, but noise is generated when the mute is released.

The reason is that the down counter is conventionally used when the DC offset is attenuated, but when the mute is released, the DC offset is restored instantaneously because the audio data is interrupted. However, the actual input signal is
It is unlikely that the mute will immediately start at a loud volume, and if it is assumed that a small signal is input, if the signal returns to 0 offset from 50% duty at the time of a small signal, the noise generated there cannot be said to be negligible. .

The second problem is described in Japanese Patent Laid-Open No. 5-1419.
In the case of "5", noise is generated when the mute is released while the DC offset value is transiently attenuated.

The reason is that, while the DC offset is being attenuated, the DC offset is suddenly returned to its original state.
Generates noise. This is because such a mute setting is operated as a command input, and it is not considered that the operation is interrupted in a transitional state from a state once set.

The third problem is that when there is no sound, the duty does not become 50% at the 0 level having a DC offset, so that the noise increases and the S / N ratio deteriorates compared to when the duty is fixed to 50%. .

The reason is that, in Japanese Patent Application Laid-Open No. 5-1195, a mute must be set in order to improve the S / N ratio because the setting is input as a command.

[0028]

Means for Solving the Problems 1-bit D / A of the present invention
The control circuit automatically switches the 1-bit D / A output pulse to 50% duty after automatically attenuating the internal DC offset value when the input is silent for a certain period of time.

More specifically, means 2 for detecting digital data silence, means 7 for attenuating the DC offset value in response to the silence state,
In response to the change, the output pulse of 1-bit D / A6 is switched to a duty of 50%, and the output of 1-bit D / A6 has a silent state with good S / N characteristics.

The DC offset value can be smoothly changed to the original value even when the silence disappears during the detection of the silence and the DC offset value is attenuated, or when the duty is switched from 50% to the normal 1-bit D / A pulse output. Another feature is that it is attempted to return to the offset value.

More specifically, there are provided means 2 for detecting that the digital data is no longer silent, and means 8 for restoring the DC offset value in response to the loss of silence.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION

(1) Description of Configuration Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 shows an operation flow of the embodiment of the present invention.

Referring to FIG. 1, according to an embodiment of the present invention, an input terminal 1 for inputting a digital signal, and a silence detection for detecting a state of silence / speech to which data inputted from the input terminal 1 are inputted. A circuit 2, a DF3 for oversampling, and a DC offset for stabilizing the operation of the NS are generated. This DC offset is attenuated smoothly when there is no sound. DC offset control circuit 7 for smooth restoration
And an adder 4 for adding a DC offset to the oversampled data, and the added data is input to perform compression processing of the number of bits per sample.
NS5 generating 1-bit pulse output and 1-bit D / A
Generating unit 6 and a duty ratio of 50 to improve S / N.
And a 1-bit D / A mute circuit 8 for converting a 1-bit D / A output into a silent state with good S / N characteristics.
It comprises an output terminal 9 for outputting the output of A. (2) Description of Operation Next, the operation of the embodiment of the present invention will be described with reference to FIGS.

Digital data is input from the digital input terminal 1 and the silence detection circuit 2 constantly monitors the input data, and 1-bit D / A performs a normal operation until silence occurs (t0 to t1 in FIG. 2). period).

The moment the digital input becomes 0 (t in FIG. 2)
1) The silence detecting circuit 2 starts counting and detects that a silence state continues for a certain period of time (period t1 to t2 in FIG. 2).

When the silence state continues for a certain period of time, the DC offset control circuit 7 receives a control signal from the silence detection circuit 2 and starts attenuating the DC offset (period t2 to t3 in FIG. 2).

Here, if the input data is not silenced even for a moment (at the moment of t3 in FIG. 2), the silence detecting circuit 2 immediately supplies the DC offset control circuit 7 with a control signal in a sound state. The DC offset control circuit 7
The C offset is increased to the initial state of the DC offset (the period from t3 to t4 in FIG. 2).

Since the initial state is returned again, digital data is input from the digital input terminal 1 and the silence detecting circuit 2 constantly monitors the input data.
The bitD / A performs a normal operation (t3 to t3 in FIG. 2).
t4 period).

The moment the digital input becomes 0 (t in FIG. 2)
4) The silence detection circuit 2 starts counting and detects that the silence state continues for a certain period of time (period t4 to t5 in FIG. 2). When the silence state continues for a certain period of time, the DC offset control circuit 7 receives a control signal from the silence detection circuit 2 and starts attenuating the DC offset, and continues to attenuate while the silence state continues until the DC offset becomes zero. Decay. (Figure 2
Period of t5 to t6).

The DC offset control circuit 7 supplies a control signal to the mute circuit 8 at the moment when the DC offset becomes 0 (t6 in FIG. 2).
Pulse output and output terminal 9 outputs duty 5
A pulse of 0% is output (t6 to t7 in FIG. 2).

At the moment when the input signal becomes a sound state (t7 in FIG. 2), the DC offset control circuit supplies the mute circuit 8 with a control signal for switching the duty from 50% to the 1-bit D / A converter. 8 is 1 bit
The output of the D / A converter 6 is supplied to an output terminal 9.

Further (at the instant t7 in FIG. 2), the silence detecting circuit 2 immediately supplies the DC offset control circuit 7 with the sounded control signal, and the DC offset control circuit 7 converts the DC offset into the DC offset. It is increased to the initial state (period t7 to t8 in FIG. 2).

[0044]

【Example】

 (1) Description of Configuration An embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 4, an input terminal 1 for inputting a digital signal, a silence detection circuit 2 for detecting whether the input data is a silence or a sound, and a DF3 for oversampling. , NS for stable operation of NS
DC offset generation circuit 11 for generating C offset
An up / down counter 12 for increasing / decreasing the DC offset value; an up / down control circuit 10 for controlling the increasing / decreasing cycle and step; and an adder for adding a DC offset to the oversampled data. NS5 and 1bitD for performing compression processing of the number of bits per sample as input data 4 and the added data
/ A converter 6, duty 5 to improve S / N
A 50% duty generation circuit 13 for generating a 0% pulse output, and a detection circuit 22 for detecting that the output of the up / down counter 12 has become 0 and the offset value has become zero.
From the NS output by the detected signal and the duty 5
It comprises a switch 14 for switching to the output of the 0% generation circuit 13 and an output terminal 9 for outputting a pulse output selected by the switch 14. (2) Description of Operation First, the operation of the up / down counter will be described in detail with reference to FIGS.

The up / down counter 12 reads the offset initial value set by the DC offset generation circuit 11, and counts down if the control signal supplied from the silence detection circuit 2 is silent, and counts up if the control signal is sound.
Control the C offset value. At this time, the detection circuit 22 which detects that the output (DC offset value) of the up / down counter becomes zero detects that the DC offset value has become zero.

Then, the DC offset value and the digital data from the DF are added by the adder 4 and supplied to the NS 5.

At this time, when the output of the up / down counter 12 becomes 0, the up / down counter 12 terminates the down counting and outputs the output of the up / down counter 12 to 0.
Waiting for the digital input to be sounded, and when the output of the up-down counter 12 has reached the initial value of the DC offset, the up-counting is completed and the output of the up-down counter 12 is fixed at the initial value. It operates as if waiting until the digital input is silent.

The cycle and level of the up / down counting are controlled by the up / down control circuit 10 because the number of bits of the digital data of the amplifier and the input connected to the subsequent stage differs depending on the system.

The control signal supplied from the up / down control circuit 10 is a signal for controlling the cycle and level of the up / down counter 12, and the signal for controlling the cycle is a sound (noise) which increases or decreases the DC offset itself.
Audio band (2
(0 to 20 kHz) or less. (Period in FIG. 8) The level at which the DC offset is increased or decreased can be controlled by discarding the lower bits of the up / down counter, and if the bit length is increased, the fine step level 2 (a side in FIG. 8) bit length By shortening, the output of the counter can be changed at a rough step level 1 (b side in FIG. 8), but the coarser the step, the greater the level of the digital signal, and the more the sound can be heard as a sound. desirable.

When the output of the up / down counter becomes zero, the detector 22 supplies a 1-bit D / A signal to the switch 14.
50% duty generation circuit 1 from pulse output of converter 6
When a signal for switching to the pulse output of No. 3 is supplied and the output of the up / down counter becomes non-zero, the duty is 50%.
1-bit D / A converter 6 from pulse output of generation circuit 13
Is supplied to the switch 14 for control.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS.

Digital data is input from the digital input terminal 1 and the silence detection circuit 2 constantly monitors the input data, and 1-bit D / A performs a normal operation until silence occurs (t0 to t1 in FIG. 5). period).

The moment when the digital input becomes 0 (t in FIG. 5)
1) The silence detection circuit 2 starts counting and detects that a silence state continues for a certain period of time (period t1 to t2 in FIG. 5). Silence detection circuit 2 if silence continues for a certain period of time
Supplies a control signal to start down-counting to the up-down counter 12 (at the instant of t2 in FIG. 5).

The up / down counter 12 starts counting down from the offset data value input from the DC offset generation circuit 11 in response to the signal supplied from the silence detection circuit 2 (period t2 to t3 in FIG. 5).

If the input data is no longer silent (at the moment of t3 in FIG. 5), the silent detection circuit 2 immediately supplies the up-down counter 12 with the control signal in the sounded state, and the up-down counter 12 12 increases the DC offset to the initial state of the DC offset (FIG. 5).
Period from t3 to t4).

Since the state returns to the initial state again, digital data is input from the digital input terminal 1 and the silence detecting circuit 2 constantly monitors the input data.
The bit D / A performs a normal operation (t3 to t3 in FIG. 5).
t4 period).

The moment the digital input becomes 0 (t in FIG. 5)
4) The silence detection circuit 2 starts counting and detects that the silence state continues for a certain period of time (period t4 to t5 in FIG. 5).

When the silence state continues for a certain period of time, the up / down counter 12 receives a control signal from the silence detection circuit 2 and starts attenuating the DC offset. During the silence state, the attenuation continues and the DC offset becomes zero. (The period from t5 to t6 in FIG. 5). And the detection circuit 22
Detects that the DC offset value has become zero at the moment when the output of the up / down counter becomes zero (t6 in FIG. 5), sends a mute control signal to the switch 14 and sends
4 switches from the pulse output of the 1-bit D / A converter 6 to the pulse output of the 50% duty generation circuit 13, and outputs a pulse of 50% duty from the output terminal 9 (FIG. 5).
T6 to t7).

At the moment when the input signal becomes a sound state (t7 in FIG. 5), the silence detecting circuit 2 immediately supplies the up-down counter 12 with the sounded control signal.
The up / down counter 12 operates to increase the DC offset to the initial state of the DC offset (period t7 to t8 in FIG. 5).

Then, the detection circuit 22 detects that the up / down counter 12 is no longer zero, and outputs a 1-bit output pulse from the 50% duty generation circuit 13 to the switch 14.
A control signal for switching to an output pulse from the D / A converter 6 is supplied, and the switch 14 supplies the output of the 1-bit D / A converter 6 to the output terminal 9.

Therefore, in the present invention, it is automatically detected that silence DATA continues for a certain period of time or more, and the DC offset value is attenuated stepwise (this step takes into account the human audible band) to set the offset value to 0. The output is switched to a duty of 50%. For this reason, noise can be prevented from being generated without sacrificing characteristics.

Also, when the input data becomes data other than 0 and the DC offset is returned to the initial state, noise is not generated because the DC offset is increased stepwise.

Further, even when the input data changes from silence to sound during the transition in which the DC offset is attenuated, noise is not generated because the DC offset value is smoothly restored.

[0065]

The first effect is that the mute state can be set without generating noise, and no noise is generated when returning from the mute state to the normal operation state.

The reason is that the DC offset of 1-bit D / A is smoothly attenuated at a frequency lower than the audio band by using an up / down counter.
This is because no noise is generated due to the increase.

The second effect is that no noise is generated even if the state is changed to a sound state while the DC offset is attenuated by detecting silence.

The reason is that the DC offset is smoothly attenuated and increased at a frequency lower than the audio band by using an up / down counter.

The third effect is that the S / N ratio can be improved.

The reason is that silence detection is automatically performed,
This is because the DC offset is set to 0.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is an operation waveform diagram showing one embodiment of the present invention.

FIG. 3 is an operation flow showing an embodiment of the present invention.

FIG. 4 is a configuration diagram showing one embodiment of the present invention.

FIG. 5 is an operation waveform diagram showing one embodiment of the present invention.

FIG. 6 is a change operation waveform diagram of a DC offset showing one embodiment of the present invention.

FIG. 7 is a detailed configuration diagram of one embodiment of the present invention.

FIG. 8 is an operation waveform diagram showing one embodiment of the present invention.

FIG. 9 is a conventional configuration diagram.

FIG. 10 is a conventional operation waveform diagram.

FIG. 11 is a diagram showing a conventional configuration (FIG. 1 of Japanese Patent Application Laid-Open No. 5-14195).

FIG. 12 is a conventional operation waveform diagram.

[Explanation of symbols]

 Reference Signs List 1 digital input 2 silence detection circuit 3 DC (digital filter) 4 adder 5 NS (noise shaper) 6 1-bit D / A converter 7 DC offset control circuit 8 mute circuit 9 output terminal 10 up / down control circuit 11 DC offset generation circuit 12 Up-down counter 13 Duty 50% generation circuit 14 Switch 22 Detection circuit Below 15-Dither generator 16 Control circuit 17 Adder 18 Quantizer 19 Adder 20 Transfer function circuit (feedback means) 21 l / k times circuit (attenuator)

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-55924 (JP, A) JP-A-5-276048 (JP, A) JP-A-62-277814 (JP, A) 195585 (JP, A) JP-A-4-245717 (JP, A) JP-A-5-14195 (JP, A) JP-A-5-244010 (JP, A) JP-A-6-77825 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H04R 3/00 310 H03M 1/08 H03M 7/32

Claims (6)

(57) [Claims] A digital signal is input and oversampled.
Digital filter that outputs signals (hereinafter referred to as DF)
And DC offset generation that outputs a DC offset signal
Circuit, the oversampling signal and the DC off
An adder for adding a set signal and outputting an addition result;
Noise that inputs the addition result signal and outputs the bit compression signal
A shaper (hereinafter referred to as NS) and the bit-compressed signal
1-bit D / A conversion circuit that inputs and outputs pulse data
And the pulse signal is input to output a mute signal
And a 50% duty generation circuit.
Input the output signal of the 50% generation circuit and the pulse data
The output signal of the 50% duty generation circuit and the pulse
Mute times to output either the
Path, a silence detection circuit for detecting a silence state, and the DC
Up-down card between the offset generator and the adder
And the up / down of the silence detection signal.
Connect the output of the up-down counter
1-bit DAC input to the adder
Control circuit. 2. The 1-bit D according to claim 1,
In an AC control circuit, the up-down counter and the add-
A count value detection circuit is connected between the
Counter value reaches the preset value.
Output a mute control signal when the
Input to the mute circuit,
1bitDA characterized by switching to 50% signal
C control circuit. 3. The 1-bit D according to claim 1,
In the AC control circuit, the DC offset generation circuit
An up-down counter is used.
1b characterized by gradually reducing the offset value
itDAC control circuit. 4. The 1-bit D according to claim 1,
In the AC control circuit, the DC offset generation circuit
An up / down counter is used.
1b characterized by gradually increasing the offset value
itDAC control circuit. 5. The 1-bit D according to claim 1,
In the AC control circuit, the DC offset generation circuit
It consists of an up / down counter, and its clock and bit
1-bit DAC system characterized by arbitrarily controlling the length
Your circuit. 6. An input terminal to which a digital signal is input, and a non-signal state of the digital signal connected to the input terminal.
Output a detection signal by detecting that
In response to the digital signal silence being stopped.
A detection circuit for stopping the output of the detection signal, and oversampling the digital signal connected to the input terminal.
Output oversampled signal
A digital filter and a predetermined DC offset to the oversampled signal.
A DC offset generating circuit for applying a
While the detection signal is being input, the DC offset value is
0 and gradually attenuated to output.
Outputs the first control signal when the offset value becomes 0
Input stops when the detection signal is being input.
When the second control signal is output when the
The DC offset value attenuated to the predetermined offset
DC offset that is gradually increased toward the
And the DC offset is added to the oversampled signal.
Noise shaping for noise shaping the applied signal
And the noise- shaped signal is converted into pulse data.
And a conversion circuit for converting the pulse data, and receiving the first control signal.
Output pulse with 50% duty when power is applied
However, when the second control signal is mute input, the
A mute circuit for outputting pulse data.
1-bit DAC control circuit.