JP2893332B2 - Imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a removable storage device.
The present invention relates to an imaging device such as a camera having means. 2. Description of the Related Art Conventionally, image storage means has been configured to be detachable.
Video cameras have been considered. This kind of camera
Now, look at the viewfinder provided on the camera body.
Therefore, image storage means is installed in this viewfinder.
The state of whether or not it is displayed is displayed. [0003] However, this problem
In such a configuration, if you do not look into the viewfinder,
To check that the power is not turned on.
There was an inconvenience that the presence or absence of storage means was not displayed. The present invention has been made in view of the above circumstances.
Do not look in regardless of whether the power of the main unit is turned on or off.
No action is required, and at the same time watching the display
Display to check whether image storage means is installed
An object of the present invention is to provide a camera with a device. [0005] An image pickup lens and an image pickup device are provided.
And an imaging unit, which is rotatably connected to the imaging unit.
And an imaging device main unit having a display unit.
That an imaging device is capable of storing a plurality of images, before
Image storage means detachably configured from the imaging device.
Provided on the imaging device main body side, the image storage means is stored and arranged on the display unit side of the imaging device main body portion ,
It is configured such that the attachment / detachment state of the image storage unit can be checked simultaneously with the display unit. Embodiments of the present invention will be described below with reference to the drawings. First, the external configuration will be described with reference to FIGS. In FIG. 1, reference numeral 1 denotes a case body, and a television camera section 2 is detachably provided on one side. As shown in the drawing, the case body 1
Both the TV camera unit 2 and the TV camera unit 2 have a rectangular parallelepiped shape, and the overall shape of the case body 1 and the TV camera unit 2 is configured so that both the front surface and the rear surface are substantially flush. A liquid crystal display unit 3 and a tuning unit 4 are provided at the center on the front surface of the case body 1, and a cassette unit 5 and a speaker 6 are provided on the right side thereof. Also,
A key operation unit 7 and a rod antenna 8 are provided on an upper part of the case body 1. The key operation unit 7 is provided with, for example, a power switch, a knob for adjusting a television image, various operation keys for the cassette unit 5, and the like. Further, the camera section 2 is provided with a small-sized image pickup device (not shown) using, for example, a solid-state image pickup device CCD, and a lens 9 is attached to a tip end thereof. The camera unit 2 is detachably attached to the case main body 1 at a portion A near the lower end portion.
As shown in the figure, the upper end can rotate in the front-rear direction with the above-mentioned part A as a central axis. FIGS. 4 and 5 show a cross-sectional structure of a joint portion between the case main body 1 and the camera unit 2. FIG. The case main body 1 has a circular coupling window 11 formed at a position where the case main body 1 is coupled to the camera unit 2, and a coupling groove 12 is provided along an inner peripheral edge thereof. An annular elastic member 13 is provided in the coupling groove 12. On the other hand, the camera unit 2 has a case 1
4, the coupling groove 12 as shown in FIGS.
And a pair of engaging claws 15a, 15b is formed.
The engaging claws 15a and 15b are arranged in a substantially fan-like shape and are vertically opposed to each other.
Are formed narrower than the other engagement claws 15b. In this case, the engagement claw 15b is formed to protrude from the inner wall 14b of the case 14, but the engagement claw 15a is
It is formed at the tip of the lever 16 extending from 4a. The engaging claws 15a and 15b are inserted into the case main body 1 through the coupling window 11, and are located in the coupling grooves 12 to couple the camera unit 2 to the case main body 1. The lever 1
A push button 17 is integrally formed in the center of the case 6, and a tip end of the push button 17 protrudes outside through a hole 18 provided in a lower surface of the case 14. The lead wire 19 from the image pickup device in the camera section 2 is led out of the through hole formed between the engaging claws 15a and 15b, and is led out of the case main body 1 through the coupling window 11.
Is inserted into. Then, the lead wire 19 is connected to a terminal portion of a print base 20 provided in the case body 1. As described above, the camera unit 2 is
a, 15b are located in the annular coupling groove 11 and the case body 1
Can be rotated at the connecting portion. During this rotation, the engagement claws 15a and 15b slide within the annular coupling groove 11. When the camera unit 2 is to be removed from the case 1, the push button 17 is pressed to release the engagement between the engagement claw 15a and the engagement groove 11 as shown in FIG. The camera unit 2 and the case body 1 are separated such that the claws 15a are put out of the coupling window 11. in this case,
If a margin is provided for the length of the lead wire 19 and the margin is stored in the case body 1 or the camera unit 2, the camera unit 2 is separated from the case body 1 according to the length of the lead wire 19. be able to. Further, the camera unit 2 can be mounted on the case main body 1 by performing an operation reverse to the above-described separating operation. In the above-described embodiment, the case where the case is configured as a horizontal type is shown, but it may be configured as a vertical type as shown in FIG. Note that the same parts as those of the above-described embodiment are denoted by the same reference numerals, and detailed description is omitted. Next, the configuration of the electronic circuit will be described with reference to FIG. In the figure, reference numeral 2 denotes the above-described television camera unit,
Reference numeral 21 denotes a television receiver. Video signals are output from the TV camera unit 2 and the TV image receiving unit 21, selected by the selector 22, and sent to the video processing unit 23. The video processing unit 23 includes an A / D conversion circuit 24 and a memory circuit 2 for storing image data for one screen, as described in detail later.
5, a synchronization separation circuit 26, a switch unit 27, and a timing circuit 28, and the video signal from the selector 22 is A
/ D conversion circuit 24 and sync separation circuit 26. The A / D conversion circuit 24 converts an input video signal into a digital signal and stores the digital signal in a memory circuit 25. Further, the synchronization separation circuit 25 detects a vertical synchronization signal from the input video signal, outputs a timing signal φv, and supplies the timing signal φv to the memory circuit 25 and the switch unit 27.
The switch unit 27 includes a control switch for displaying a still image, a switch for controlling reading / writing of the cassette unit 5, and the like, and outputs various switch signals in synchronization with the timing signal φv. This switch unit 27
Is output to the memory circuit 25 and the timing circuit 28. This timing circuit 28
Always generates clock pulses φ1 and φ2,
The frequency of the clock pulses φ1 and φ2 is switched according to a switch signal from the switch unit 27. The clock pulses φ1 and φ2 output from the switch unit 27 are sent to the memory circuit 25. Normally, the memory circuit 25 outputs data from the A / D conversion circuit 24 to the display unit 3 and performs storage processing on the data. Write or read data. FIG. 9 shows the details of the video processing unit 23. The A / D conversion circuit 24 converts the input video signal into a 4-bit digital signal,
Output to The memory circuit 25 includes the A / D conversion circuit 2
4 is read into the flip-flop 31 in synchronization with the clock pulse φ2, output to the display unit 3 via the gate circuit 32, and input to the input terminals I1 to I4 of the RAM 35 via the gate circuit 34. The RAM 35 has a capacity capable of storing one frame of image data.
Data read from the cassette unit 5 by the MT control unit 36 is input to I4 via the gate circuit 37.
The operation mode of the sync separation circuit 26 is specified by the switch signal C from the switch unit 27. In the normal television display mode, the sync separation circuit 26 detects each vertical sync signal in the video signal as shown in FIG. The timing signal φv
In the write / read mode for the cassette section 5, the timing signal .phi.v having an n-times cycle is output. This timing signal φv is input to the clear terminal CL of the address counter 38. The address counter 38 counts up by the clock pulse φ2 from the timing circuit 28 and specifies an address of the RAM 35. The timing signal φv output from the sync separation circuit 26 is input to flip-flops 41a to 41c in the switch unit 27 as a read clock. The flip-flops 41a to 41c read the key input from the key input unit 43 latched by the latch circuits 42a to 42c in synchronization with the timing signal φv. The key input unit 43 includes a write key K1 for instructing data writing to the cassette unit 5, a cassette unit 5
A read key K2 for instructing data read from the memory, a stop key K3 for instructing the display of a still image, and a release key K4 for releasing the display of a still image are provided. One terminal of each of the keys K1 to K4 has a VDD power supply, That is, a “1” signal is given. The operation signal of the write key K1 is sent to the set terminal S of the latch circuit 42a, the operation signal of the read key K2 is sent to the set terminal S of the latch circuit 42b, and the operation signals of the read key K2 and the stop key K3 are sent to the OR circuit 44. The signal is input to the set terminal S of the latch circuit 42c. Also,
The operation signal of the release key K4 is transmitted to the latch circuits 42a and 42b.
Are input via OR circuits 45 and 46, respectively, and are also directly input to the reset terminal R of the latch circuit 42c. The outputs of the flip-flops 41a and 41b are further input to the OR circuits 45 and 46, respectively. Thus, the output of the flip-flop 41a is taken out as the switch signal D and is inputted to the NOR circuit 47 and the OR circuit 48. The output of the flip-flop 41b is taken out as a switch signal B, and is also input to a NOR circuit 49 and an OR circuit 48. The output of the OR circuit 48 becomes a switch signal C.
Then, the output of the flip-flop 41c is taken out as the switch signal E and is input to the NOR circuit 47 via the inverter 50 and the NOR circuit 49. The output of the NOR circuit 47 becomes the switch signal A. As described above, the switch unit 27 outputs the switch signals A to E. The switch signal A is output together with the clock pulse φ1 through the NAND circuit 51 through the RA.
It is input to the read / write terminal R / W of M35. The switch signal B is input to the MT control unit 36 as a read command R, and is also input directly to the gate circuit 37 and to the gate circuit 34 via an inverter 52 as a gate signal. The switch signal C is sent to the sync separation circuit 26 and the timing circuit 28 as a mode signal. The timing signal D is input to the MT control unit 36 as a write command W. The timing signal E is output from the inverter 53.
Is sent to the gate circuit 32 as a gate signal. The data read from the RAM 35 is input to the MT control unit 36. The timing signal φv and the clock pulses φ1 and φ2 are further input to the MT control unit 36. The MT control section 36 performs data read / write control on the cassette section 5 in accordance with signals B and D from the switch section 27. The data read from the RAM 35 is a switch signal E.
Is sent to the display unit 3 via the gate circuit 54, which is gate-controlled by the. Next, the operation of the above embodiment will be described. The selector 22 in FIG. 8 selects the television camera unit 2 or the television receiving unit 21 according to the operation of the selection switch provided on the key operation unit 7. Now, TV receiver 2
If 1 is selected, the video signal output from the television receiver 21 is sent to the A / D converter 24 and the sync separator 26 in the video processor 23. The television receiver 21 performs processes such as channel selection, frequency conversion, amplification, and detection on radio waves received by the rod antenna 8,
Output as a video signal. The A / D conversion circuit 24 converts the input video signal into a 4-bit digital signal,
The data is written into the flip-flop 31 in synchronization with the clock pulse φ2. In this case, the switch signals A to E output from the switch unit 17 in the normal television reception mode are A
Are held in a "1" state, and BE are held in a "0" state. Therefore, as shown in FIG.
A clock signal φ1 and φ2 of MHz are generated, and the synchronization separation circuit 26 outputs a timing signal φv every time each vertical synchronization signal is detected. The cycle of the timing signal φv at this time is 262.5H (1H is one horizontal scanning cycle). When the switch signals B and E are "0", the gates of the gate circuits 34 and 32 are opened and the gates of the gate circuits 37 and 54 are closed. Therefore, the flip-flop 31 reads the input data by the clock pulse φ2 of 3 MHz and outputs it to the display unit 3 through the gate circuit 32. The data held in the flip-flop 31 is sent to the RAM 35 and stored in the RAM 35 in accordance with the address specified by the address counter 38. The address counter 38 is cleared by the timing signal φv, and then counts the clock pulse φ2 to
Specify the address of M35. In this case, the switch unit 2
The switch signal A output from 7 opens the gate of the NAND circuit 51 at "1", and outputs an inverted signal of the clock pulse φ1 to the RAM 35. The RAM 35 performs a write operation in synchronization with the inverted signal of the clock pulse φ1.
The video signal sent via the. Thereafter, the same operation is performed, and an image for one field is always stored in the RAM 35. When the user wants to freeze the displayed image in the above-mentioned television receiving state, he operates the stop key K3 of the switch section 27. When the stop key K3 is operated, the "1" signal is latched in the latch circuit 42c, and the latch output is read into the flip-flop 41c in synchronization with the timing signal .phi.v output from the synchronization separation circuit 26. As a result, flip-flop 4
The switch signal E output from 1c becomes "1", and the gate of the gate circuit 54 opens and the gate of the gate circuit 32 closes. When the switch signal E becomes "1", the output of the inverter 50 becomes "0", the output of the NOR circuit 49 becomes "1", and the output of the NOR circuit 47 becomes "0". When the output of the NOR circuit 47, that is, the switch signal A becomes "0", the output of the NAND circuit 51 is held at the "1" signal state, and the RAM 35 enters the read mode. Therefore, the image data stored in the RAM 35 is sequentially read in accordance with the count content of the address counter 38 and sent to the display unit 3 via the gate circuit 54. The image data thus stored in the RAM 35 is displayed on the display unit 3.
And displayed as a still image. Then, in order to return from the still image display state to the normal television display state, the release key K4 of the switch section 27 is operated. When the release key K4 is operated, the latch circuit 42c is reset, and the synchronization separation circuit 2 is reset.
The "0" signal is read into the flip-flop 41c in synchronization with the timing signal .phi.v output next from 6. As a result, the switch signal A output from the switch circuit 27 is output.
ＥE return to the initial state, and each circuit section also returns to the initial state, so that the normal television image is displayed on the display unit 3 as described above. When the image displayed on the display section 3 is stored in the cassette section 5 in the above-described television receiving state, the write key K1 of the switch section 27 is operated. The latch circuit 4 is operated by operating the write key K1.
2a is set, and the latch output is set to the timing signal φ.
The data is read into the flip-flop 41a in synchronization with v. As a result, the output of the flip-flop 41a, that is, the switch signal D becomes "1", the latch circuit 42a is reset, and the MT control unit 36 enters the write mode.
When the switch signal D becomes "1", the switch signal A output from the NOR circuit 47 becomes "0" and the switch signal C output from the OR circuit 48 becomes "1" as shown in FIG. When the switch signal A becomes "0", the output of the NAND circuit 51 becomes "1" as described above, and RA
M35 is in the read mode. When the switch signal C becomes "1", the cycle of the timing signal .phi.1 output from the synchronization separation circuit 26 becomes n times as shown in FIG. 10, and the timing signals .phi.1 and .phi.2 output from the timing circuit 28. Becomes 1 / n. Therefore, the count-up speed of the address counter 38 is 1 / n of the normal time.
The image data stored in the RAM 35 is read out at 1 / n of the normal speed and sent to the MT control unit 36. When the switch signal D is given from the switch unit 27, the MT control unit 36 drives the cassette unit 5 and
The image data sent from 35 is written on a magnetic tape. While the image data is being written on the magnetic tape, a normal television image is displayed on the display unit 3. The image data for one field stored in the RAM 35 is stored in the MT control unit 36.
Is read out and written on the magnetic tape, a timing signal .phi.v is thereafter output from the synchronization separating circuit 26. The "0" signal is read into the flip-flop 41a by the timing signal .phi.v, the switch signals A to E return to the initial state, the respective circuit sections return to the initial state, and the writing of image data to the cassette section 5 is completed. When displaying the image data stored in the cassette unit 5 as a still image as described above,
The read key K2 in the switch unit 27 is operated. The operation of the read key K2 causes the latch circuits 42b, 42
c is set, and the "1" signal is read into the flip-flops 41b and 41c in synchronization with the timing signal φ2.
As a result, the switch signal B output from the flip-flop 41b becomes "1", the latch circuit 42b is reset, and the MT control unit 36 enters the read mode.
Further, the gate of the gate circuit 37 is opened and the gate circuit 3 is opened.
Gate 4 closes. When the switch signal B becomes "1", the switch signal C output from the OR circuit 48 becomes "1", and as described above, the synchronization separation circuit 2
6, the cycle of the timing signal .phi.v becomes n times, and the frequency of the clock pulses .phi.1, .phi.2 outputted from the timing circuit 28 becomes 1 / n. Therefore, the cycle of the write command W (clock pulse φ1) input to the RAM 35 via the NAND circuit 51 and the count-up speed of the address counter 38 become 1 / n of the normal. On the other hand, when the switch signal B is given, the MT control section 36 enters the read mode, and the cassette section 5
To sequentially read the image data stored in the magnetic tape, and input the read image data to the RAM 35 via the gate circuit 37. The RAM 35 sequentially stores the image data sent from the MT control unit 36 at the address specified by the address counter 38. The flip-flop 4
The output of 1c is output as the switch signal E, and the gate of the gate circuit 54 opens and the gate of the gate circuit 32 closes. In this case, when the switch signal E is output, the output of the inverter 50 becomes "0". At this time, since the switch signal B is output, the output of the NOR circuit 49 is held at "0" and , The output of the NOR circuit 47,
That is, the switch signal A is held in the “1” state,
Data writing to M35 is performed without any trouble. When the transfer of the image data for one field from the cassette unit 5 to the RAM 35 is completed, the timing signal φv is output from the synchronization separation circuit 26, and “0” is written into the flip-flop 41b. At this time, since the "1" signal is latched in the latch circuit 42c, the "1" signal is written into the flip-flop 41c again. Accordingly, the switch signals B and C become "0", the switch signal A outputted from the NOR circuit 47 becomes "0", the output of the NAND circuit 51 becomes "0", and the RAM 35 switches to the read mode. When the switch signal C returns to “0”, the synchronization separating circuit 26 and the timing circuit 28 return to the normal operation. Therefore, the address counter 38 performs a count-up operation at a normal speed, and sequentially designates a read address of the RAM 35. The data stored in the RAM 35 is sequentially read out via the gate circuit 54 according to the address designation, and displayed on the display unit 3. Thus, the image data stored in the cassette unit 5 is read out to the RAM 35 and displayed on the display unit 3. Then, in this still image display state, if the release switch K4 in the switch section 27 is operated,
As described above, the switch unit 27 and each circuit unit return to the initial state, and return to the normal television reception state. In the above embodiment, the RAM 35 stores the surface image data for one field. However, the RAM 35 may store one frame or more image data. In the above embodiment, the cassette 5
Although the description has been given of the case where the image data for one screen is written / read in the above, it is needless to say that image data for a plurality of screens can be recorded. As described above, the imaging lens and the imaging device are
When the imaging unit provided is rotatably connected to the imaging unit
An imaging apparatus, comprising: an imaging apparatus main body unit having a display unit , and capable of storing a plurality of images,
The image storage means detachably configured from the imaging device;
While being provided on the imaging device main body side, the image storage means
By being housed and arranged on the display unit side of the imaging device main unit so that the attachment / detachment state of the image storage unit can be checked at the same time as the display unit, regardless of whether the power of the main unit is turned on or off, and looking into the unit Thus, it is possible to provide an imaging device with a display device that does not require an operation such as the above and can simultaneously confirm whether or not the image storage unit is mounted while watching the display on the display unit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a front view showing an external configuration of an embodiment of the present invention. FIG. 2 is a perspective view showing an external configuration. FIG. 3 is a side view showing a rotating state of a camera unit. FIG. 4 is a cross-sectional view showing a coupling portion between a case body and a camera unit. FIG. 5 is a cross-sectional view showing a connection portion between a case body and a camera unit. FIGS. 6A to 6C are views showing a connection part of the camera unit to a case main body. FIG. 7 is a perspective view showing another embodiment of the external configuration. FIG. 8 is a block diagram illustrating a schematic configuration of the entire electronic circuit. FIG. 9 is a circuit configuration diagram showing details of a video processing unit in FIG. 7; FIG. 10 is a timing chart for explaining the operation of FIG. 9; [Description of Signs] 1 Case body 2 TV camera unit 3 Liquid crystal display unit 4 Tuning unit 5 Cassette unit 8 Rod antenna 21 TV receiving unit 23 Video processing unit 24 A / D conversion circuit 25 Memory circuit 26 Synchronization separation circuit 27 Switch unit 36 MT control units 41a to 41c Flip-flops 42a to 42c Latch circuit 43 Key input unit

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ identification code FI H04N 5/781 (58) Field of investigation (Int.Cl. ⁶ , DB name) H04N 5/225 H04N 5/232

Claims (1)

(57) [Claims] An image pickup apparatus comprising: an image pickup section having an image pickup lens and an image pickup element; and an image pickup apparatus main body section which is rotatably connected and has a display section, and stores a plurality of images. An image storage unit configured to be detachable from the imaging device, provided on the imaging device main body side, and the image storage unit is housed and arranged on the display unit side of the imaging device main body unit, An imaging apparatus characterized in that a detachable state of the storage means can be checked simultaneously with the display unit. 2. The imaging apparatus according to claim 1, wherein the image storage unit is housed on a side of the imaging apparatus main body opposite to the imaging section with the display section interposed therebetween. 3. Imaging lens, imaging device, and output from this imaging device
An image storage means for storing the image, the image storing hand
An image pickup apparatus comprising: a display section for displaying an image stored in a row; a receiving section for receiving an image signal; and a receiving section for receiving the image signal.
Semiconductor memory for storing an image based on a received image signal
Has the door, the image storing means can store a plurality of images, detachably constructed from the imaging device, wherein the display unit includes an image stored in the semiconductor memory
Displays, even when the image storage means is removed from the imaging device, using the semiconductor memory, the said display unit
An imaging apparatus characterized in that an image based on an image signal received by a receiving means can be displayed.