JPH08324U - Camera with display device - Google Patents

Abstract

(57) Abstract: A video camera having a display device and a video camera in which a camera unit is rotatable or detachable are considered, but they are large and have many irregularities. Therefore, it was inconvenient to carry. SOLUTION: The case body 1 is a rectangular parallelepiped case provided with a liquid crystal display section 3 and a TV camera section 2 is a rectangular parallelepiped. The TV camera section 2 is rotatably attached to the case body 1. When the case body 1 and the TV camera unit 2 are in a predetermined positional relationship, the case body 1 and the TV camera unit 2 are configured in such a manner that the entire shape of the case body 1 and the TV camera unit 2 is a rectangular parallelepiped whose front surface and back surface are flush with each other. The shape makes it easy to carry.

Description

[Detailed description of the device]

[0001]

[Technical field to which the device belongs]

 The present invention relates to a camera with a display device.

[0002]

[Prior art]

 2. Description of the Related Art Conventionally, a video camera including a display device and a video camera in which a camera unit is configured to be rotatable or detachable have been devised.

[0003]

[Problems to be solved by the device]

 The conventional video camera is large and has many irregularities, which makes it inconvenient to carry. The present invention has been made in view of the above circumstances, and an object thereof is to provide a camera with a display device that is small in size and easy to carry.

[0004]

[Means for Solving the Problems]

 It is composed of a substantially rectangular parallelepiped main body provided with an image display section and a substantially rectangular parallelepiped TV camera section. When in a positional relationship, the main body and the television camera section are configured so that the entire shapes thereof are substantially rectangular parallelepiped on the front surface and the back surface.

[0005]

[Embodiment of device]

 Embodiments of the present invention will be described below with reference to the drawings. First, the external structure will be described with reference to FIGS. 1 and 2. In the figure, reference numeral 1 is a case body, and a television camera section 2 is detachably provided on one side. As shown in the drawing, both the case body 1 and the TV camera unit 2 are in the shape of a rectangular parallelepiped, and the overall shape of the case body 1 and the TV camera unit 2 is a rectangular parallelepiped whose front surface and back surface are flush. It is composed of On the front surface of the case body 1, a liquid crystal display unit 3 and a tuning unit 4 are provided in the center, and a cassette unit 5 and a speaker 6 are provided on the right side of the liquid crystal display unit 3. A key operation unit 7 and a rod antenna 8 are provided on the upper side of the case body 1. The key operation unit 7 is provided with, for example, a power switch, a television image adjusting knob, various operation keys for the cassette unit 5, and the like.

Further, the camera unit 2 is provided with a small-sized image pickup device (not shown) using, for example, a solid-state image pickup device CCD, and a lens 9 is attached to the tip thereof. The camera unit 2 is detachably attached to the case body 1 at the A portion near the lower end, and the upper end can rotate in the front-rear direction about the A portion as a central axis as shown in FIG. It has become.

FIG. 4 and FIG. 5 show a cross-sectional structure of a joint portion between the case body 1 and the camera portion 2. A circular coupling window 11 is formed in the case body 1 at a portion to be coupled with the camera section 2, and a coupling groove 12 is provided along the inner peripheral edge of the circular coupling window 11. Then, the annular elastic member 13 is disposed in the coupling groove 12.

On the other hand, a pair of engaging claws 15a and 15b are formed in the case 14 of the camera section 2 so as to correspond to the coupling groove 12 as shown in FIGS. 6 (a) to 6 (c). . The engaging claws 15a and 15b are substantially fan-shaped and are vertically opposed to each other. The engaging claw 15a located on the end side is formed narrower than the other engaging claws 15b. In this case, the engaging claw 15b is formed so as to project from the inner side wall 14b of the case 14, while the engaging claw 15a is formed at the tip of the lever 16 extending from the outer side wall 14a of the case 14. The engaging claws 15a and 15b are inserted into the case body 1 through the coupling window 11 and are located in the coupling groove 12 to couple the camera unit 2 to the case body 1. A push button 17 is integrally formed at the center of the lever 16 described above, and the tip of the push button 17 is projected to the outside from a hole 18 provided in the lower side surface of the case 14.

Therefore, the lead wire 19 from the image pickup device in the camera section 2 is led out through a through hole formed between the engaging claws 15a and 15b, and inserted into the case body 1 through the coupling window 11. To be done. The lead wire 19 is connected to the terminal portion of the print base 20 provided in the case body 1. As described above, since the engagement claws 15a and 15b are located in the annular coupling groove 11 and are coupled to the case body 1, the camera section 2 can be rotated in the coupling section. During this rotation, the engaging claws 15a and 15b slide in the annular coupling groove 11.

When the camera unit 2 is removed from the case 1, the push button 17 is pressed to release the engagement between the engagement claw 15a and the engagement groove 11 as shown in FIG. 5, and the engagement is performed in this state. The camera portion 2 and the case body 1 are separated by causing the claws 15a to come out from the coupling window 11. In this case, if the lead wire 19 has an allowance and the allowance is stored in the case body 1 or the camera part 2, the camera part 2 can be adjusted according to the length of the lead wire 19. Can be separated from the case body 1. Further, the camera unit 2 can be mounted on the case body 1 by performing the operation opposite to the above separating operation.

In the above embodiment, the case is shown as a horizontal type, but it may be a vertical type as shown in FIG. The same parts as those in the above embodiment are designated by the same reference numerals and detailed description thereof will be omitted.

Next, the configuration of the electronic circuit section will be described with reference to FIG. In the figure, 2 is the above-mentioned TV camera unit, and 21 is a TV image receiving unit. Video signals are output from the television camera section 2 and the television image receiving section 21, selected by the selector 22 and sent to the video processing section 23. The video processing unit 23 includes an A / D conversion circuit 24, a memory circuit 25 for storing image data for one screen, a sync separation circuit 26, a switch unit 27, and a timing circuit 28, as will be described later in detail. The video signal from 22 is input to the A / D conversion circuit 24 and the sync separation circuit 26.

The A / D conversion circuit 24 converts the input video signal into a digital signal and stores it in the memory circuit 25. Further, the sync separation circuit 25 detects a vertical sync signal from the input video signal, outputs a timing signal φv, and supplies it to the memory circuit 25 and the switch unit 27. The switch unit 27 includes a control switch for displaying a still image, a switch for controlling reading / writing of the cassette unit 5, and outputs various switch signals in synchronization with the timing signal φv. The switch signal output from the switch unit 27 is sent to the memory circuit 25 and the timing circuit 28. The timing circuit 28 constantly generates clock pulses φ1 and φ2, but switches the frequencies of the clock pulses φ1 and φ2 in accordance with the switch signal from the switch unit 27. The clock pulses φ1 and φ2 output from the switch unit 27 are sent to the memory circuit 25. The memory circuit 25 normally outputs the data from the A / D conversion circuit 24 to the display unit 3 and stores the data, but in response to a command from the switch unit 27, the memory unit 25 sends the data to the cassette unit 5. , Write or read data.

FIG. 9 shows the details of the video processing unit 23. The A / D conversion circuit 24 converts the input video signal into a 4-bit digital signal and outputs it to the memory circuit 25. The memory circuit 25 reads the output of the A / D conversion circuit 24 into the flip-flop 31 in synchronization with the clock pulse φ 2 and outputs it to the display unit 3 via the gate circuit 32 and the RAM 35 via the gate circuit 34. Input to the input terminals I1 to I4 of.

The RAM 35 has a capacity capable of storing image data for one frame, and the data read from the cassette unit 5 by the MT control unit 36 is input to the input terminals I1 to I4 via the gate circuit 37. Is entered. The operation mode of the sync separation circuit 26 is designated by the switch signal C from the switch unit 27. When the vertical sync signal in the video signal is detected in the normal television display mode as shown in FIG. The timing signal .phi.v is outputted to the cassette section 5, and the timing signal .phi.v having a cycle of n times is outputted in the writing and reading modes to the cassette section 5.

The timing signal φv is input to the clear terminal CL of the address counter 38. The address counter 38 counts up by the clock pulse φ2 from the timing circuit 28 and designates the address of the RAM 35. The timing signal φv output from the sync separation circuit 26 is input to the flip-flops 41a to 4lc in the switch unit 27 as a read clock. The flip-flops 41a-4lc read the key input from the key input section 43 latched by the latch circuits 42a-42c in synchronization with the timing signal .phi.v.

The key input unit 43 includes a write key K1 for instructing data writing to the cassette unit 5, a read key K2 for instructing data reading from the cassette unit 5, a stop key K3 for instructing display of a still image, A cancel key K4 for canceling the display of a still image is provided, and the VDD power supply, that is, the "1" signal is applied to one terminal of each of the keys K1 to K4. The operation signal of the write key K1 is the set terminal S of the latch circuit 42a, the operation signal of the read key K2 is the set terminal S of the latch circuit 42b, and the operation signals of the read key K2 and stop key K3 are the OR circuit 44. It is input to the set terminal S of the latch circuit 42 c via the. The operation signal of the release key K4 is input to the reset terminals R of the latch circuits 42a and 42b via the OR circuits 45 and 46, respectively, and is also directly input to the reset terminal R of the latch circuit 42c. The outputs of the flip-flops 41a and 41b are input to the OR circuits 45 and 46, respectively.

Thus, the output of the flip-flop 41 a is taken out as the switch signal D and is also inputted to the NOR circuit 47 and the OR circuit 48. The output of the flip-flop 41b is taken out as the switch signal B and is also input to the NOR circuit 49 and the OR circuit 48, and the output of the OR circuit 48 becomes the switch signal C. Then, the output of the flip-flop 41c is taken out as the switch signal E and is also input to the NOR circuit 47 via the inverter 50 and the NOR circuit 49, and the output of the NOR circuit 47 becomes the switch signal A.

As described above, the switch section 27 outputs the switch signals A to E. The switch signal A is sent to the read / write terminal R / W of the RAM 35 through the NAND circuit 51 together with the clock pulse φ 1. Is entered. The switch signal B is input to the MT control unit 36 as a read command R, directly to the gate circuit 37, and also to the gate circuit 34 via the inverter 52 as a gate signal. The switch signal C is sent to the sync separation circuit 26 and the timing circuit 28 as a mode signal. The timing signal D is input to the MT control unit 36 as a write command W. Then, the timing signal E is sent as a gate signal to the gate circuit 32 via the inverter 53.

Then, the data read from the RAM 35 is input to the MT control unit 36. The timing signal φv and the clock pulses φ 1 and φ 2 are further input to the MT control unit 36. The MT control unit 36 controls data read / write with respect to the cassette unit 5 in accordance with the signals B and D from the switch unit 27. The data read from the RAM 35 is sent to the display unit 3 via the gate circuit 54 whose gate is controlled by the switch signal E.

Next, the operation of the above embodiment will be described. The selector 22 in FIG. 8 selects the television camera unit 2 or the television image receiving unit 21 according to the operation of the selection switch provided in the key operation unit 7. If the TV receiver 21 is selected, the video signal output from the TV receiver 21 is sent to the A / D conversion circuit 24 and the sync separation circuit 26 in the video processor 23. The television receiver 21 performs processing such as tuning, frequency conversion, amplification and detection on the radio wave received by the rod antenna 8 and outputs it as a video signal.

Then, the A / D conversion circuit 24 converts the input video signal into a 4-bit digital signal, and writes it in the flip-flop 31 in synchronization with the clock pulse φ 2. In this case, in the normal television receiving mode, in the switch signals A to E output from the switch unit 17, A is held at "1" and B to E are held at "0". Accordingly, as shown in FIG. 10, the timing circuit 28 generates clock pulses .phi.1 and .phi.2 of 3 MHz, for example, and the sync separation circuit 26 outputs a timing signal .phi.v every time each vertical sync signal is detected. At this time, the cycle of the timing signal φv is 262.5 H (1H is one horizontal scanning cycle).

When the switch signals B and E are “0”, the gates of the gate circuits 34 and 32 are opened and the gates of the gate circuits 37 and 54 are closed. Therefore, the flip-flop 31 reads the input data by the 3 MHz clock pulse φ 2 and outputs it to the display unit 3 via the gate circuit 32.

The data held in the flip-flop 31 is sent to the RAM 35 and stored in the RAM 35 according to the address designated by the address counter 38. The address counter 38 is cleared by the timing signal φv and then counts the clock pulse φ2 to specify the address of the RAM 35. In this case, the switch signal A output from the switch unit 27 is "1", the gate of the NAND circuit 51 is opened, and the inverted signal of the clock pulse φ1 is output to the RAM 35. The RAM 35 performs a write operation in synchronization with the inverted signal of the clock pulse φ1 and stores the video signal sent from the A / D converter 24 via the flip-flop 31. The same operation is performed thereafter, and an image for one field is always stored in the RAM 35.

However, in the above television receiving state, when it is desired to freeze the display image, the stop key K3 in the switch unit 27 is operated. When the stop key K3 is operated, the "1" signal is latched in the latch circuit 42c, and the latch output is read by the flip-flop 41c in synchronization with the timing signal .phi.v output from the sync separation circuit 26. As a result, the switch signal E output from the flip-flop 41c becomes "1", and the gate of the gate circuit 54 opens and the gate of the gate circuit 32 closes. When the switch signal E becomes "1", the output of the inverter 50 becomes "0", the output of the NOR circuit 49 becomes "1", and the output of the NOR circuit 47 becomes "0". When the output of the NOR circuit 47, that is, the switch signal A becomes "0", the output of the NAND circuit 51 is held in the "1" signal state, and the RAM 35 becomes the read mode. Therefore, the image data stored in the RAM 35 is sequentially read out according to the count content of the address counter 38 and sent to the display unit 3 via the gate circuit 54. In this way, the image data stored in the RAM 35 is read out to the display unit 3 and displayed as a still image.

Then, in order to return from the still image display state to the normal television display state, the release key K4 in the switch unit 27 is operated. When the release key K4 is operated, the latch circuit 42c is reset and the "0" signal is read into the flip-flop 41c in synchronization with the timing signal .phi.v output next from the sync separation circuit 26. As a result, the switch signals A to E output from the switch circuit 27 return to the initial state and each circuit section also returns to the initial state, so that the normal television image is displayed on the display section 3 as described above. Become.

When the image displayed on the display unit 3 is stored in the cassette unit 5 in the above television receiving state, the write key K1 in the switch unit 27 is operated. The operation of the write key K1 sets the latch circuit 42a, and the latch output is read into the flip-flop 41a in synchronization with the timing signal φv. As a result, the output of the flip-flop 41a, that is, the switch signal D becomes "1", the latch circuit 42a is reset, and the MT control unit 36 enters the write mode. When the switch signal D becomes "1", the switch signal A output from the NOR circuit 47 becomes "0" and the switch signal C output from the OR circuit 48 becomes "1" as shown in FIG. Become.

When the switch signal A becomes “0”, the output of the NAND circuit 51 becomes “1” as described above, and the RAM 35 enters the read mode. When the switch signal C becomes "1", the period of the timing signal φ1 output from the sync separation circuit 26 becomes n times as shown in FIG. 10, and the timing signal φ1 output from the timing circuit 28 The frequency of φ2 becomes 1 / n. Therefore, the count-up speed of the address counter 38 becomes 1 / n of the normal time, and the image data stored in the RAM 35 is read at a speed of 1 / n of the normal time and sent to the MT control section 36. When the switch signal D is given from the switch unit 27, the MT control unit 36 drives the cassette unit 5 and writes the image data sent from the RAM 35 on the magnetic tape.

While the image data is being written on the magnetic tape, a normal television image is displayed on the display unit 3. Then, when the image data for one field stored in the RAM 35 is read by the MT control unit 36 and written on the magnetic tape, the timing signal φv is then output from the sync separation circuit 26. A "0" signal is read into the flip-flop 41a by the timing signal .phi.v, the switch signals A to E are returned to the initial state, each circuit portion is returned to the initial state, and the writing of the image data to the cassette portion 5 is completed.

When the image data stored in the cassette unit 5 as described above is displayed as a still image, the read key K2 in the switch unit 27 is operated. By operating the read key K2, the latch circuits 42b and 42c are set, and the "1" signal is read into the flip-flops 41b and 41c in synchronization with the timing signal φ2. As a result, the switch signal B output from the flip-flop 41b becomes "1", the latch circuit 42b is reset, the MT control unit 36 enters the read mode, the gate of the gate circuit 37 opens, and the gate circuit 34 opens. The gate closes. Further, when the switch signal B becomes "1", the switch signal C output from the OR circuit 48 becomes "1", and the cycle of the timing signal φv output from the sync separation circuit 26 becomes n times as described above. At the same time, the frequencies of the clock pulses φ1 and φ2 output from the timing circuit 28 become 1 / n. Therefore, the cycle of the write command W (clock pulse φ1) input to the RAM 35 via the NAND circuit 51 and the count-up speed of the address counter 38 become 1 / n of the normal value.

On the other hand, when the switch signal B is applied, the MT control section 36 enters the read mode, drives the cassette section 5 to sequentially read the image data stored in the magnetic tape, and through the gate circuit 37. Input to the RAM 35. The RAM 35 sequentially stores the image data sent from the MT control unit 36 at the address designated by the address counter 38. The output of the flip-flop 41c is output as the switch signal E, and the gate of the gate circuit 54 is opened and the gate of the gate circuit 32 is closed. In this case, when the switch signal E is output, the output of the inverter 50 becomes "0", but since the switch signal B is being output at this time, the output of the NOR circuit 49 is held at "0". At the same time, the output of the NOR circuit 47, that is, the switch signal A is held in the "1" state, and the data writing to the RAM 35 is performed without any trouble.

When the transfer of the image data for one field from the cassette unit 5 to the RAM 35 is completed, the timing signal φv is output from the sync separation circuit 26 and “0” is written in the flip-flop 41b. At this time, since the "1" signal is latched in the latch circuit 42c, the "1" signal is written in the flip-flop 41c again. Therefore, the switch signals B and C become "0", the switch signal A output from the NOR circuit 47 becomes "0", the output of the NAND circuit 51 becomes "0", and the RAM 35 is switched to the read mode. Further, when the switch signal C returns to "0", the sync separation circuit 26 and the timing circuit 28 return to normal operation. Therefore, the address counter 38 counts up at a normal speed and sequentially specifies the read addresses of the RAM 35. In accordance with this address designation, the data stored in the RAM 35 are sequentially read out via the gate circuit 54 and displayed on the display unit 3. In this way, the image data stored in the cassette unit 5 is read out to the RAM 35 and displayed on the display unit 3. Then, in this still image display state, if the release switch K4 in the switch section 27 is operated, the switch section 27 and each circuit section return to the initial state and return to the normal television receiving state.

In the above embodiment, the RAM 35 stores the surface image data for one field, but the image data for one frame or more may be stored.

Further, in the above-described embodiment, the case where the image data for one screen is written / read out in the cassette unit 5 has been described, but it goes without saying that the image data for a plurality of screens can be recorded.

[0035]

[Effect of device]

 With the above configuration, when the video camera unit is rotatable but the main body equipped with the image display unit and the TV camera unit are in a predetermined positional relationship, the overall shape of the main unit and the TV camera unit Since the front surface and the back surface are formed in a substantially rectangular parallelepiped shape, it is possible to provide a camera with a display device that has no protrusion and is easy to carry.

[Brief description of drawings]

FIG. 1 is a front view showing an external configuration of an embodiment of the present invention.

FIG. 2 is a perspective view showing an external configuration.

FIG. 3 is a side view showing a rotated state of a camera unit.

FIG. 4 is a cross-sectional view showing a joint portion between a case body and a camera unit.

FIG. 5 is a cross-sectional view showing a joint portion between a case body and a camera unit.

FIG. 6A to FIG. 6C are views showing a connecting portion of the camera unit to the case main body.

FIG. 7 is a perspective view showing another embodiment of the external configuration.

FIG. 8 is a block diagram showing a schematic configuration of an entire electronic circuit.

9 is a circuit configuration diagram showing details of a video processing unit in FIG.

10 is a timing chart for explaining the operation of FIG.

[Explanation of symbols]

 1 Case Main Body 2 Television Camera Section 3 Liquid Crystal Display Section 4 Tuning Section 5 Cassette Section 8 Rod Antenna 21 Television Image Receiving Section 23 Video Processing Section 24 A / D Conversion Circuit 25 Memory Circuit 26 Sync Separation Circuit 27 Switch Section 36 MT Control Section 41a- 41c Flip-flop 42a-42c Latch circuit 43 Key input section

Claims (1)

[Scope of utility model registration request] 1. A display characterized in that a main body provided with an image display unit and a TV camera unit are integrally and rotatably configured, and are formed in a compact and easy-to-carry shape without projections. Camera with device.