JP2888834B2 - Image signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION   The present invention will be described in the following order. A Industrial application fields Summary of invention B C Conventional technology (Fig. 38) Problems to be solved by invention D (Fig. 38) Means for solving problem E (Figs. 1 and 2) F action (Figs. 1 and 2) G Example (G1) First Embodiment (FIG. 1, FIGS. 39-42) (G2) Image memory 13 (FIGS. 1 and 2) (G3) Prevention of passing of image memory 13 (Figs. 3 to 5) (G4) Writing and reading of image memory 13 (Figs. 2 and 6) (G5) Second embodiment (FIG. 7) (G6) Third embodiment (FIGS. 8 and 9) (G7) Fourth embodiment (FIGS. 10 to 22) (G8) Image display using enlarged read data (Figs. 23 to 31) (G9) Image display using reduced readout data (Figs. 32 to 37) (G10) Other embodiments Effect of H invention A Industrial application fields   The present invention relates to an image signal processing device, and more particularly to an input image signal.
As an output image signal while writing to the image memory.
Output to convert the input image signal to an output image signal.
Suitable for application to image signal processing devices that are designed to convert
Things. Summary of invention B   According to the present invention, while writing image data to an image memory,
An image signal read from the image data.
In the signal processing device, the image memory is divided into a plurality of memory areas.
Image data from each memory area.
Data can be transferred, so that practically
When reading data from memory,
Data can be written. C Conventional technology   Conventionally, for example, an NTSC standard television
Image with various functions by image signal processing
Image signal processing device that displays on the display screen
I am.   For example, as shown in FIG.
For example, a video tape recorder (VTR)
The main screen PIC1 consisting of the first input image reproduced from the
And at the same time, a second input image
For example, a video signal obtained by receiving a television broadcast
The sub screen PIC2, which is displayed by reducing the number to 1/4, for example, is displayed.
Indicates that the video of the currently received broadcast program
You can check the playback image of the VTR while watching
Image signal processor with loose picture-in-picture function
Has been proposed.   Also, as shown in FIG. 38 (B), the display screen DIP is
Direction (ie, V direction) and lateral direction (ie, H direction)
By dividing into two, four reduced screens divided into four
Receive channels (for example, first and second
3rd, 4th, 6th channel) images are displayed or reduced
Displaying a series of disassembled still images on screens PIC11 to PIC14
The so-called multi-screen function used when
An image signal processing device has been proposed.   If the display screen can be made multifunctional in this way, the display device
It has the advantage that it can be used for more diverse uses.   In this way, the picture-in-picture function, multi-picture
Conventionally, as a method of obtaining a converted image used for a surface function,
The input image signal is once converted to digital image data and
Image data written while writing to the image memory
Means for reading out and displaying on the display screen.
In this way, image reduction and enlargement processing,
Processing to display screens in a superimposed manner, or on the display screen
To make the screen displayed on the screen a moving image or a still image
Can be easily implemented. Problems to be solved by invention D   Thus, while writing image data to the image memory,
By reading the written image data,
To obtain an image signal to be displayed on the display screen DIP.
Write when input data is written to the image memory
Address signal and output image data from the image memory.
Asynchronous with each other as read address signals to read
Where it is necessary to be able to use
There is a case.   The input image signals coming from various image signal sources
In order to obtain a multifunctional image by combining
The image signal has a unique synchronization signal, which is
Uniformly to the read address signal or write address signal
If it were to fit, the display screen would be multifunctional.
Because it becomes difficult.   However, the read address signal and the write address signal
And asynchronous signals, the same address in the image memory
Write command to the memory area
A read command may be given. At this time,
Rear cannot perform read or write operation of image data
It becomes an operating state, and eventually under these conditions,
There is a problem that an image signal is lost.   The present invention has been made in consideration of the above points, and
Always write image data to the image memory
Image signal that can read image data
It is intended to propose a processing device. Means for solving problem E   In order to solve such a problem, in the present invention, the first
Write data DATA corresponding to the image signal VIDEO2 of_INWrite
While writing to the image memory 13 by the dress signal WADR
Write to image memory 13 by read address signal RADR
The read image data is read out and the second image signal VIDEO1 is read.
By switching between the corresponding image data, the first
The image based on the image signal VIDEO2 of FIG.
In the image signal processing device 1 to be inserted into the image based on DEO1
And the input write data DATA_INSplit into multiple and output
Switching means 32 for switching, and write data divided by the switching means 32
MEM1 to MEM3
Data stored in each memory area MEM1 to MEM3.
An image memory 31 for transmitting data as parallel data,
Sent from each memory area MEM1 to MEM3 of the image memory 31
Received parallel data and output as serial data
Writing to serial access memory 35 and image memory 31
Control means 51 for controlling the read and read and switching means 32,
52, and the control means 51 and 52 control the first image signal VIDE
Multiple time slots based on the O2 horizontal sync signal
Set a data processing period TRS consisting of
Time slots contained in the memory area MEM1
~ MEM3 from one memory area MEM1 ~ MEM3
Transmission period TRS1 to TRS3 to real access memory 35 and others
Write period ACC1 to ACC3 of memory area MEM1 to MEM3
Assignment and writing to each memory area MEM1 to MEM3
In addition to performing continuous time slots,
The rear area MEM1 to MEM3 to the serial access memory 35
Sending is performed in multiple consecutive time slots,
Furthermore, serial access of each memory area MEM1 to MEM3
The transmission to the memory 35 is performed by the horizontal retrace of the second image signal VIDEO1.
In between. F action   A plurality of memory areas ME constituting the image memory body 31
Image data written to M1 to MEM3 are different
Parallel transfer to serial access memory 35 with timing
Transferred as data DM1 to DM3, and the transferred image data
Data is read data DATA_OUTAs serial access note
Read from the memory 35.   Thus, image data can be read from some of the memory areas MEM1 to MEM3.
During serial transfer of data, other memory area ME
Write data DATA for M1 to MEM3_INWrite
The image data can be stored in the image memory 13 in practice.
Data is written and the written image data is
It can be read without lack. G Example   An embodiment of the present invention will be described below in detail with reference to the drawings. (G1) First embodiment   In FIG. 1, reference numeral 1 denotes an image signal processing device as a whole.
For example, the picture noise described above with reference to FIG.
And a first input terminal configured to implement
T1 receives the main screen image signal VIDEO1 that forms the main screen PIC1.
And a small screen image signal VIDEO2 that forms a small screen PIC2.
At the second input terminal T2.   The sub-screen image signal VIDEO2 is an NTSC composite video
Signal in the luminance signal / color signal separation circuit 11.
Phonen signal S_INThat is, the luminance signal Y₁, Color difference signal R₁−Y₁
And B₁−Y₁Analog / digital conversion circuit
Image memory after being converted to digital data in 12
Write data DATA to 13_INIs entered as   At the same time, the horizontal synchronization signal and
And the write clock signal WCK synchronized with the vertical synchronization signal is written.
It is generated in the clock signal generation circuit 14, and this is
Log / digital conversion circuit 12 uses sampling pulses
And the write address control circuit 15
As a clock input.   The write address control circuit 15 outputs a write clock signal.
WCK is counted by the address counter.
The initial address AD of the image memory 13_OOr final address
Su AD_MAXThe write address signal WADR that sequentially specifies
It is sent to the memory 13.   Thus, the image memory 13 stores the small-screen image signal VIDEO2.
Image data from the first pixel to the last pixel is a child screen
Synchronized with horizontal and vertical sync signals of video signal VIDEO2
While the initial address AD of the image memory 13_OOr final
Dress AD_MAXIs written to the memory area.   The main screen image signal VIDEO1 is read clock signal generation circuit 21
To the horizontal and vertical sync signals
The read clock signal RCK is used to control the read address.
Provided as a clock input to circuit 22 and
Digital / analog provided on the output side of the image memory 13
The signal is supplied to the analog conversion circuit 23 as a sampling pulse.   The read address control circuit 22 reads the read clock signal.
Signal RCK is counted by the address counter and the image
Initial address AD of memory 13_OOr last address AD_MAXThe finger
The read address signal RADR to be set is transmitted. This allows
Image memory 13 has initial address AD_OOr last address AD_MAX
The image data written to the main screen image signal VIDEO1
Repeatedly in synchronization with the horizontal and vertical sync signals
Read and read data DATA_OUTDigital / Ana
Sends to log conversion circuit 23, thus digital / analog
Component of the small screen image signal VIDEO2 from the
Signal S_OUT2The luminance signal Y comprising₁, Color difference signal R₁−Y₁Passing
And B₁−Y₁Is supplied to the switch circuit 24.   In the case of this embodiment, the write address control circuit 15
The read address control circuit 22 has an enlargement function and
It has a reduction function.
Of the small-screen image data written in the image memory 13
Specify every other address in the horizontal and vertical directions.
And thus every other image data
Extract (ie, cull every other image data and discard)
Support image data reduced to 1/4
Component signal S_OUT2To the switch circuit 24
It is made to be able to do.   In contrast, the main screen image signal VIDEO1 is a luminance signal / color
In the signal separation circuit 25, the component signal S_OUT1age
And luminance signal Y_Two, Color difference signal R_Two−Y_TwoAnd B_Two−Y_TwoSwitch times
Supply to road 24.   The switch circuit 24 is, for example, a system having a computer configuration.
Switch control supplied from controller (not shown)
The display screen DIP of the display device 26 is controlled by the signal SSW.
Of the frame cycle corresponding to (FIG. 38 (A)),
Component at the timing corresponding to the main screen PIC1
Signal S_OUT1Is sent to the display device 26, and the child screen PIC2
Component signal at the timing corresponding to the region
S_OUT2Is supplied to the display device 26.   The data is sequentially transmitted from the switch circuit 24 to the display device 26 according to the scanning.
Frame image signal S consisting of pixel data to be output_VDThe mat
Conversion into a display drive signal in the Rix circuit
It is supplied to a display screen consisting of a tube (CRT).   In the configuration of FIG. 1, a small screen image is stored in the image memory 13.
The image data representing the signal VIDEO2 is the sub-screen image signal VI.
Initial initialization is synchronized with the horizontal and vertical synchronization signals of DEO2.
Dress AD_OFrom the last address AD_MAXWritten sequentially up to
At the same time, the written image data is
Signal in synchronization with the horizontal and vertical sync signals of VIDEO1.
It is read out while being reduced to 4 screens.   Thus, the image memory 13 stores the write address signal WA
Image is read by read address signal RADR that is asynchronous to DR.
Although it is configured to read data,
As shown in Fig. 41, the write address signal WADR and read address
That the addresses specified by the address signals RADR pass each other
To avoid the possibility that the output image data may be disturbed.
So that writing and reading are always done at the same time
The configuration is as shown in FIG.   For example, as shown in FIG._OFrom the last
Address AD_MAX1 frame (and therefore 2
Image to which the image data of
For the memory 13, the write operation curve FRM_WAs shown in
Input image data at the timing WC
K_OFrom WCK_MAXWrite cycle T up to_WBetween image memory
Initial address AD_OFrom the last address AD_MAXInput image data
While writing data, the read operation curve FR
M_R, The initial address AD of the image memory_O
Or last address AD_MAXImage data written in
Timing RCK_OFrom RCK_MAXRead cycle T up to_Rof
When reading in between, write operation curve FRM_WAnd read operation
Curve FRM_RIntersection P_X1Crossing at the tie
Ming CK_X1Specified by the read address signal
Address AD_X1Is specified by the write address signal.
Consider a case in which you pass an address.   Here, the write operation curve FRM_WAlong one frame
Dress AD_O~ AD_MAXFig. 40
In (A), the data of the circular image as shown by the image K1 is
Position to overwrite the image memory where it is written
To write the data of the moved circular image K2
Reads when converting so-called video images
The image is distorted.   That is, the write operation curve FRM_WFigures along (Fig. 39)
Write figure K2 data to image memory on K1 data
And read out the written image data.
Curve FRM_RThe read operation curve FRM_R
Intersection P of_X1Earlier timing RCK_O~ CK_X1At
Is a write operation curve FRM as shown in FIG._WThailand
Ming WCK_O~ CK_X1Image data of image K2 overwritten in
Data is read.   On the other hand, the read operation curve FRM_RTiming CK_X1~ RC
K_MAXIn, the read address overtakes the write address
By doing so, the write operation curve FRM_WImage of figure K2 along
Before image data is written to the image memory,
That is, the image data of the figure K1 one frame before)
After reading, write the image data of figure K2
Will be. Of the read image data read as a result,
The content represents the figure K1.   As is clear from the readout image in FIG.
Write address signal and read address signal for image memory
Have different addressing speeds, such as when
Sometimes, the write operation curve FRM_WAnd readout operation curve FRM_RCrosses
May occur, in which case the intersection P_X1To
The image data content is shifted at the corresponding read image position
Such a display image may be disturbed.   Such an image shift is not noticeable in a still image
However, if the image data is a moving image, the display image
Unsightly image disturbance.   In FIG. 39 and FIG.
Address specified by the write address signal.
Fig. 39 shows a case where the specified address is overtaken.
As shown in FIGS. 41 and 42 corresponding to FIGS.
The address specified by the write address signal is
Address P specified by the address signal_X2No
Imming CK_X2In the same way, if
The image is distorted. (G2) Image memory 13   The image memory 13 stores the 1/4 reduced image as shown in FIG.
Image with memory capacity for 4 frames, one frame
It has a memory body 31. The image memory body 31 has first to fourth
3 groups of memory areas for each frame memory area
MEM1, MEM2, MEM3
Included in the first, second, third, and fourth frames for each MEM2 and MEM3
Frame memory area (M1
1, M12, M13, M14), (M21, M22, M23, M24), (M3
1, M32, M33, M34).   Reached from analog / digital conversion circuit 12 (Fig. 1)
Write data to be written_INIs the switch for allocating the memory area
The first, second, and third groups of write data DG
Switch circuit 3 for frame allocation divided into 1, DG2 and DG3
3 are supplied to the switch circuit units 33A, 33B, and 33C.   Each switch circuit section 33 of the frame allocation switch circuit 33
A, 33B, and 33C are first, second, and third groups of write data DG1,
The first, second, third and fourth frames of DG2 and DG3, respectively
Data (DF11, DF12, DF13, DF14), (DF21, DF22,
DF23, DF24) and (DF31, DF32, DF33, DF34)
Corresponding frame memory area (M11, M12, M13, M1
4), (M21, M22, M23, M24), (M31, M32, M33, M3
4) It is made to input each.   Write to each memory area MEM1, MEM2, MEM3
The input image data is stored in a switch 34 for frame selection.
One line of parameters passed through the switch circuits 34A, 34B, and 34C.
Serial access as real transfer data DM1, DM2, DM3
Predetermined in the memory area 35A, 35B, 35C of the memory 35
Are sequentially transferred during the different transfer periods.   Thus, the serial access memory 35 has the read address
Memory address AD for one frame from signal RADR_O~ AD_MAX
(FIG. 39 to FIG. 42) is one read address signal RADR.
When given for each frame, each frame memory area
One line of image data transferred to 35A, 35B, 35C
Data as serial read data DSR1, DSR2, and DSR3, respectively.
To the switch circuit 36 for selecting the memory area.   The switch circuit 36 for selecting a memory area is used for serial reading.
Memory area allocation system for outgoing data DSR1, DSR2, DSR3
To select the data specified by the control signal S13
From the original image data (ie, the write data DATA_IN) Painting
Read data DATA having the same pixel array as the elementary array_OUT
To the digital / analog conversion circuit 23 (Fig. 1)
Put out. (G3) Prevention of passing of image memory 13   In the above configuration, the write data arriving at the image memory 13 is
Data_INFirst, the frame allocation switch circuit 33
Therefore, the first to fourth frame memory areas (M11, M2
Assigned to one of (1, M31)-(M14, M24, M34)
Is written in frame units so that
The image data written in units is the frame selection switch.
The read data is selected by the switch circuit 34 in frame units.
Data_OUTIs sent as   Write image data in frame units in this way
When reading while referring to FIGS.
An address specified by the write address signal WADR;
With the address specified by the read address signal RADR
So that addresses do not overtake each other in between.
Switch circuit 33 for frame allocation and switch for frame selection
The switch circuit 34 has a write frame control circuit 41 and a read frame control circuit.
Write frame allocation control signal formed in control circuit 44
It is controlled by S12 and the read frame control signal S14.   In the case of this embodiment, the write frame control circuit 41
The write address control circuit 15
Counting the write frame pulse PFW
The first frame, the second frame, the third frame
, The fourth frame, the first frame...
A write frame allocation control signal S12 is generated.   Similarly, the read frame control circuit 44 is a quaternary counter.
The read address control circuit 22 (FIG. 1)
The readout frame pulse PFR given by
By this, the first frame, the second frame, the third frame
Frame, 4th frame, 1st frame ...
A designated read frame control signal S14 is generated.   Write frame control circuit 41 and read frame control circuit 44
Of the write-side passing detection circuit
42 and the overtaking detection signal transmitted from the reading side overtaking detection circuit 43
Given as a disable signal from signals S21 and S22
You.   The write-side overtaking detection circuit 42 has been described with reference to FIGS. 41 and 42.
As described above, the write address signal for the image memory 13
WADR and read address signal RADR are asynchronous, so write
The address specified by the address signal WADR is
Overtake the address specified by the dress signal RADR
Overtaking detection signal that detected this when it was about to go
S21 is connected to the enable terminal EN of the write frame control circuit 41.
By giving it as a enable signal, the write frame
The counting operation of the control circuit 41 is prohibited only once.   On the other hand, the read-side overtaking detection circuit 43
As described above with reference to the figure, the read address signal RADR
Address specified by the write address signal WADR.
The specified address is about to be overtaken
Detect this and read over the passing detection signal S22
As a disable signal to the enable terminal EN of the circuit 44
By giving, the count of the read frame control circuit 44
Operation is prohibited only once.   By the way, as described above with reference to FIGS. 41 and 42.
The address of the write address signal WADR is
The condition that may overtake the address of signal RADR is 3rd
As shown in FIG. 3A, the cycle of the write cycle is
At a time shorter than the cycle of the
The dress curve NW is the address of the first, second, third, and fourth frames.
Address while sequentially reading addresses
Approaching, for example, in the twelfth write cycle
The address of the write address signal WADR is read during the cycle CY1.
The phenomenon of overtaking the address of the address signal RADR occurs.   By the way, the address of the write address signal WADR is
Overtakes the address of the read address signal RADR,
Image data is written to the memory area of the same frame
Is read at the same time as the
Address of the address signal WADR becomes the current read address signal RADR.
Same as the memory area of the frame being read
If this is detected when trying to become the memory area of
The state immediately before the write address signal catches up with the same frame
And the possibility of overtaking is even stronger
It indicates that   The write-side overtaking detection circuit 42 detects that such a state has occurred.
Put out. That is, the write-side passing detection circuit 42
Upon receiving the assignment control signal S12 and the read frame control signal S14
Compare the write frame number FRW and (FRW, FRR) = (4, 1), (1, 2), (2, 3),
(3, 4) ... (1) One before the readout frame number FRR
When this number is reached, this is detected and an overtaking detection signal S21 is generated.
Send to write frame control circuit 41 to disable
Control that immediately follows
Count operation by frame pulse PFW is prohibited only once
To control.   By doing so, the time point t in FIG.₁as well as
t_TwoAs shown by, the write address curve NW
When trying to enter the same frame as line NR, the write frame
Control circuit 41 counts the write frame pulse PFW
Switch off the frame allocation switch circuit 33.
Operation so that it does not
The same memory area as the memory area of the frame
To repeatedly write newly arrived image data
To control the image memory body 31.   Thus, the address specified by the write address signal WADR
Is the frame of the frame read by the read address signal RADR.
Never enter the same memory area as the memory area
The write address signal WADR adds the read address signal RADR.
It can be controlled not to go over.   In this way, the write frame control circuit 41
Address approaches the read address, the write address
Address that operates to separate the address by one frame
Operates as a source separation means, and as a result, the write address signal
On the display screen by overtaking the read address signal
Can be effectively avoided.   In addition to this, the read-side overtaking detection circuit 43 is provided with the circuit shown in FIG.
Read address curve NR and write address in cycle CY2
As shown by the curve NW, the read address signal RADR is
Address specified by the write address signal WADR.
Detects when it is about to overtake the dress.   That is, the read-side overtaking detection circuit 43 uses the write frame allocation system.
Control signal S12 and readout frame control signal S14 for comparison
Then, at time t in FIG.₁₁And t₁₂As shown
The read address curve NR is the same as the write address curve NW
Detected when trying to enter memory area of frame
I do.   That is, the read-side overtaking detection circuit 43 outputs the read address signal
The read frame number FRR of the memory area specified by RADR is
Next formula (FRW, FRR) = (1, 4), (1, 2), (3, 2),
(4, 3) ... (2) Memory area specified by the write address signal WADR
Becomes the number one before the writing frame number FRW
The overtaking detection signal S22 to the readout frame control circuit 44.
The read frame frame that arrives immediately after
Control that prohibits the count operation for
I do.   As a result, the readout sent from readout frame control circuit 44
The frame control signal S14 is the frame that has been read
Image data of the same frame as the memory area of
The read address signal RADR changes the write address
To avoid overtaking the signal WADR
Can be prevented.   In this way, the read frame control circuit 44
Address approaches the write address, the read address
Address that operates to separate the address by one frame
Operates as a source separation means, and as a result, the read address signal
Displayed by RADR overtaking write address signal WADR
It is possible to effectively avoid the possibility of disturbance on the screen.   The above is the write address signal WADR and the read address signal RA
When the DR periods are not equal to each other
Although overtaking was described, the write address signal WADR and write
Address signals RADR are synchronized with each other,
Are equal to each other, as shown in FIG.
The write address curve NW and the read address curve NR overlap each other.
Therefore, the write address signal is
Frame number of the address specified by the
The frame number of the address specified by the
It will be in a state that matches.   In this case, the write address signal WADR is always
Read signal in the state of passing the address signal RADR or vice versa
Signal RADR overtakes write address signal WADR.
You.   At this time, the write-side overtaking detection circuit 42
FRW is (FRW, FRR) = (1, 1) ... (3) When read frame number FRR matches,
Detects and passes overtaking detection signal S21 to write frame control circuit 41
To give.   Thus, the write frame control circuit 41 is configured as shown in FIG.
As shown, time t₃₁FRW = 1 and FRR = 1
As a result, according to the write frame allocation control signal S12,
Re-image the same frame (ie, the first frame)
By executing a process that writes data,
Write address in the embedded address curve NW for one frame
No processing to separate from the read address curve NR
It is.   However, when such processing is performed, the writing frame number
The relationship between FRW and readout frame number FRR is given by the above formula (1).
Is satisfied. At time t₃₁Following
In a write cycle, FRW = 1 while FRR = 2
And the state satisfies the expression (1).   This state is as if the write address signal WADR is
The condition is the same as the condition for overtaking the response signal RADR. this
When the write-side overtaking detection circuit 42 detects this state,
An overtaking detection signal S21 is sent to the write frame control circuit 41,
Again, the memory area of the same frame (that is, the first frame)
Image data to the memory area of the
The write frame allocation control signal S12 is
It is sent to the switch circuit 33.   Thus, the write address signal WADR and the read address
The overtaking is ensured even when the signal RADR is in synchronization.
The possibility of occurrence can be avoided. (G4) Writing and reading of image memory 13   As described above, the image memory 13
Write image data at any time using the dress signal WADR
At the same time as the read address signal RADR.
Read the written image data at any time.
Can be   In order to realize such writing and reading operations, an image
The memory body 31 includes the memory area section control circuits 51 and 52 (second
According to FIG.
By controlling the memory area selection switch circuit 36,
The memory area is always randomly accessed
It is the same as being able to write data
Sometimes adversely affect the random access operation
The image data that has been written without
Read from the serial access memory 35 via the switch 36
Output data DATA_OUTSo that it can be transferred as
Has been established.   That is, the memory area control circuits 51 and 52
And read address control circuits 15 and 22 (Fig. 1)
Horizontal sync pulse PHW supplied from_SYNCAnd PHR_SYNCBased on
The switch circuit 32 for allocating the memory area and the memory
Write memory area for the rear selection switch circuit 36
Section control signal S11 and read memory area section control signal.
No. S13 is sent out.   Here, the write-side memory area section control circuit 51
As shown in FIG._SYNCBased on
Data processing period with the first to fifteenth time slots
Generates a timing signal TIM that repeatedly forms TRS,
The first, third, fifth, seventh, and ninth timers in the data processing period TRS.
Write data during access period ACC1 consisting of slots
DATA_INIs written to the first memory area MEM1 (FIG. 6).
(B1)) and the second, fourth, eleventh, thirteenth and fifteenth time
Write data DA in the access period ACC2 consisting of slots
TA_INIs written in the second memory area MEM2 (FIG. 6).
(B2)) and the sixth, eighth, tenth, twelfth and fourteenth ties
Write data in the access period ACC3 consisting of
DATA_INIs written to the third memory area MEM3 (6th
The write memory area section allocation control signal S11 as shown in FIG.
Is sent.   In addition, the memory area control circuit 51
A transfer that can transfer image data in the area MEM1, MEM2, and MEM3
Forming transmission periods TRS1, TRS2, TRS3, and successive data processing
During the period TRS, from the memory area control circuit 52 on the read side
When the transfer request signal S23 arrives,
Transfer periods TRS1, TS included in one data processing period TRS
For RS2 and TRS3, memory area MEM1, MEM2, MEM3
The image data written in the
Transferred to the serial access memory 35 through the
Let   Here, the read-side memory area section control circuit 52 performs horizontal synchronization.
Pulse PHR_SYNCMemory area section selection control based on
By sending signal S13, the serial access memory
Memory data for one line held in memory 35
The data is returned to the original data by the rear selection switch circuit 36.
Read data DATA_OUTAnd outputs the read data DATA
_OUTControl of the memory area on the writing side when sending
The transfer request signal S23 is sent to the circuit 51.   At this time, the memory area control circuit 51
Included in a given data processing period TRS in
During the periods TRS1, TRS2 and TRS3, the memory area MEM1, MEM
2.Release the transfer prohibition state for MEM3.
The next one line from the memory area MEM1, MEM2, MEM3
Transfer the image data.   Thus one line of memory area MEM1, MEM2, MEM3
Image data in one horizontal retrace interval on the read side.
It is transferred to the serial access memory 35 only once.
And write data DATA_INIs the data processing period TRS
Access periods ACC1, AC other than transfer periods TRS1, TRS2, TRS3
It will be written to C2 and ACC3.   Thus, during the third transfer period TRS3, the third memory cell
The parallel transfer data DM3 is transferred from the rear MEM3.
During the transfer, the third memory area used for the transfer
First and second memory areas MEM1 and NEM2 different from MEM3
Write data DATA_INIs made to be writable
, The first and second memory area units MEM
1.Write data DAT by randomly accessing MEM2
A_INWhile writing from the third memory area MEM3
Parallel transfer data DM3 to serial access memory 35
Can be transferred.   Thus, in the third transfer period TRS3, the image memory body
Write and read to 31 are completely asynchronous in practice.
Can be performed while maintaining relationships.   Similarly, in the second transfer period TRS2, the second memory
The parallel transfer data DM2 is transferred from the memory area MEM2.
While the third and first memory areas are different.
A Write data DATA for MEM3 and MEM1_INGet written
The image memory body 31 is practically the second
During the transfer period TRS2 of
Data_INAnd parallel transfer at the same time as writing
Transferring data DM2 to serial access memory 35
Can be.   Further, in the same manner, in the first transfer period TRS1,
The parallel transfer data DM1 from the memory area MEM1
During the transfer, a different second or third note
Write data DATA for rear area MEM2, MEM3_INWrite
The image memory main unit 31 is practically
Random access during the first transfer period TRS1 of
Write data DATA_INWhile writing
Transfer the real transfer data DM1 to the serial access memory 35
can do.   In this way, the image memory 13 maintains an asynchronous relationship.
While simultaneously writing and reading image data
Can be (G5) Second embodiment   7 shown in correspondence with FIGS. 3 (B) and 4 (B).
FIGS. 7A and 7B show a second embodiment, and
In the first embodiment, as described above with reference to FIG.
In addition, the image memory 13 has a frame memory area (M11 to M3).
1) According to (M12-M32), (M13-M33), (M14-M34)
1st to 4th frames with 1/4 reduced image as one frame
This memory is used to configure the
In the case of the example, instead of the four frame memories, four
A write-side passing detection circuit having a field memory
Overtaking was detected by 42 and the read-side overtaking detection circuit 43
When the address is separated based on the detection output
Count contents of the control circuit 41 and the control circuit 44
To the previous field number by 2 (and thus 2 fields)
It is configured to return.   In the case of this embodiment, one frame in FIG.
Image data performed in units (ie, two field units)
Executes data processing and related control in units of one field
2, except that the configuration shown in FIG.
The image memory 13 is used.   In such a configuration, as shown in FIG.
Point t₄₁The write address curve NW is equal to the read address curve N
Too close to R, overtaking detection of write address signal WADR
When the output signal S21 (FIG. 2) is obtained, the write
Two fields are written by the field allocation control signal S12.
Address is separated.   In this case, the write address signal WADR is
It is possible to effectively avoid the risk of overtaking the response signal RADR. This
In addition, in the case of FIG.
Subtract WADR for 2 fields (and therefore 1 frame)
The read address curve NR
As shown by adding “O” or “E”,
Read data DATA read by RADR_OUTInn
It will not disturb the relationship of the tarlace.   That is, the time t in FIG.₄₁At the read address
Address NR is in the third field and the write
Les curve NW is separated from the first field by 2 fields
Is already in the even field (this is called the E field)
Is written in the memory area of the first field
A. In the odd field (this is called the O field)
Overwrite the same E-field image data
At time t₄₁After that, the read address
E-field of image data read out along the curve NR
Reading so that the order of the field and O-field does not change.
Data DATA_OUTCan be sent from the image memory 13.
You.   Similarly, the time t in FIG.₅₁At
The dress curve NR approaches the write address curve NW too much for reading
Overtaking detection signal S22 for address signal RADR (Fig. 2)
Is obtained, the read field control signal S14
Field number specified by 2 fields
Pull apart.   By doing so, the read address curve NR is written.
Can effectively prevent the risk of overtaking the embedded address curve NW
With read data DATA_OUTO field at and
So that the order of the E-fields is not disrupted
You.   As described above, using the 4-field memory sequentially
Also, if you are configured to read out the flash memory,
Asynchronous write address signal WADR and read address
Signal RADR may overtake each other
Can prevent and disrupt interlacing relationships
May not be. (G6) Third embodiment   FIG. 8 corresponding to FIGS. 7 (A) and (B)
(A) and (B) show a third embodiment, and FIG.
In the case of (A) and (B), the address is detected when overtaking is detected.
Two fields apart (thus one frame)
However, in this embodiment, it is one field.
7 except that it is designed to be pulled apart.
The configuration is the same as in the case.   In such a configuration, the time t in FIG.₆₁And t₆₂
, The overwriting detection signal for the write address signal WADR
When S21 (FIG. 2) is obtained, the write field control signal
Field number specified by No. S11 is 1 field
Are separated by C   By doing so, the write address curve NW can be read.
Can effectively prevent the risk of overtaking the outgoing address curve NR.
You.   Similarly, at time t in FIG.₇₁And t₇₂smell
As for the read address signal RADR, the overtaking detection signal S22
(FIG. 2), the read field control signal S1
The field number specified by 4 is for one field
Only to be pulled apart.   By doing so, the read address curve NR is written.
Address curve NW can be effectively prevented
You.   However, with this structure, the NTSC system
There is a problem that the relationship of interlacing collapses.   That is, the write address curve NW in FIG.
As shown, time t₆₁In the second yield, O
Overwrite field and E-field image data
As shown by the read address curve NR,
Time t_61A, The first field and the second field
E-field image data continuously from the
Data is read out. Note that time t₆₂Same for
It is like.   In addition, the time t in FIG.₇₁And t₇₂At each
From the memory area of the second field and the first field
E-field and O-field images continuously
This results in reading data.   In this way, the O field or E field is continuous
When read, as shown in FIG. 9 (B), the display device
The display image DIPA at 26 is for the O-field image
Position where the E-field image is shifted upward by one line
Will be displayed on the screen.   In the case of the embodiment shown in FIG. 8, the abnormal screen DIPA is corrected.
Therefore, the write-side passing detection circuit 42 or the reading-side passing detection circuit
43 (FIG. 2) sent out of the overtaking detection signal S21 or S22.
Send to system controller.   At this time, the system controller
A one-line shift control signal SLS is supplied to the roll circuit 22.
Feed (Fig. 1), and one line of the E-field image
Control the read address so that
Correction to the normal display screen DIPN shown in FIG.
You.   In this way, the field memory can be used as the image memory 13.
Memory, the write address signal WADR and read address
Picture that may be caused by passing the dress signal RADR
Prevents image distortion and always obtains normal screen DIPN
be able to. (G7) Fourth embodiment   FIG. 10 in which parts corresponding to those in FIG.
This shows a fourth embodiment in which the image memory 13 is
As shown in FIG. 11, two
And the image memory 13
Write address signal WADR and read address signal RA for
DR is the write clock obtained from write clock signal generation circuit 14.
It is made to occur based on the tack signal WCK,
The write address signal WADR and read address signal RADR
It is made to expect.   The image memory 13 stores the write address signal WADR and the read address.
Signal RADR is received by the scaling converters 61 and 62, respectively.
And scaling provided separately by the system controller
Magnification or demagnification by control signals SECW and SECR
And conversion addresses converted based on conditions such as the display position.
Data signals WADRX and RADRX and write them to the image memory
It is supplied as a dress signal or a read address signal.   Write switch on the write side of field memories MF1 and MF2
Switch 63 is provided, based on the translation address signal WADRX.
Write formed in the write switch signal forming circuit 64
The write data DATA is generated by the switch signal SSW._INWrite
Exchange with the field memory MF1 or MF2 via the switch circuit 63
They are written so that they can write each other.   In addition, the read side of the image memory
The switch circuit 65 is provided, and based on the conversion address signal RADRX,
The read switch formed in the read switch signal forming circuit 66
Depending on the output switch signal SSR, the field memory MF1 or
Image data read from MF2 is read alternately
Read data DATA through path 65_OUTTo be sent as
It has been done.   Here, enlargement or reduction of the image, as shown in FIG. 12,
Pixels arranged horizontally and vertically (P11, P12 ...
…), (P21, P22 ……)
This is multiplied by n in the horizontal and vertical directions (for example, 2
In the case of enlargement by a factor of 2), as shown in Fig. 13,
The number of image data of the power pixel is n in the horizontal and vertical directions
Read data DATA arranged so as to overlap_OUTTo
Output from the image memory 13.   On the other hand, 1 / p (for example, 1 / p
= 1/3), as shown in Fig. 14,
Arranged horizontally and vertically in the force image
Pixels are arranged at predetermined intervals, that is, every p (for example, p = 2)
By extracting data while thinning it,
Data are p-1 thinned out and discarded
Read data DATA that is arranged with such image data
_OUTIs output from the image memory 13.   Such enlargement and reduction processing is performed on the image memory 13.
Write data DATA_INWhen writing or from the image memory 13
Read data DATA_OUTTo the image memory 13 when reading
By controlling the address, the following four
Performed by the method.   In the first method, as shown in FIG._IN
(FIG. 15 (A)) is written to the image memory 13 (FIG. 15 (B)).
When writing, the image data to be enlarged
Write image data redundantly in the memory area as described
The image data enlarged by the image memory 13
Data. Then, the enlarged image data is
By reading the next, the read data including the enlarged image
Data_OUT(FIG. 15 (C)) can be obtained.   In the second method, as shown in FIG.
TA_IN(FIG. 16 (A)) is sequentially written to the image memory 13 as it is.
While writing the data (Fig. 16 (B)).
When reading the written image data,
Image data in the same order as described above
The readout data containing the enlarged image.
Data_OUT(FIG. 16 (C)) is obtained.   In the third method, as shown in FIG._IN
When writing (FIG. 17 (A)) to the image memory 13,
As described above for the figure, a predetermined
Write to memory area while thinning image data at intervals
Write the reduced image data by going
(FIG. 17 (B)), the written image data is sequentially read.
By reading, the read data including the reduced image
DATA_OUT(FIG. 17 (C)) is obtained.   In the fourth method, as shown in FIG._IN
(FIG. 18 (A)) is sequentially stored in the image memory 13 as it is.
Write image data that is not reduced by writing
(FIG. 18 (B)), and the written image data
Including images reduced by reading while thinning
Read data DATA_OUT(FIG. 18 (C)) is obtained.   The write-side scaling converter 61 and the read-side scaling converter
The conversion circuit 62 (FIG. 11) performs the enlargement / reduction processing shown in FIGS.
The processing is executed according to the scaling control signals SECW and SECR.
As shown, the field memories MF1 and MF2
It is controlled by WADRX and RADRX.   In the case of this embodiment, as shown in FIGS.
1 field memory MF1 stores the write data DATA_INIs odd
Field (ie, O-field) image data
When writing the image data through the write switch circuit 63,
Write to in-address 1-263.   On the other hand, the second field memory MF2
Data_INIs an even field (ie E field)
When it is image data, it is transmitted through the write switch circuit 63.
To the line addresses 264 to 525.   Thus write data DATA_INO field alternately as
Or, when image data of E-field is sent
When the write switch circuit 63 is connected to the O-field or the E-field,
Field data alternately in the first field memory MF
Select and input the first or second field memory MF2
Go.   Thus, the write data is written to the field memory MF1 (or MF2).
Data_INIs written, the write operation is performed.
Not in the other field memory MF2 (or MF1)
The data is read through the read switch circuit 65 and the read data DATA
_OUTIt is read as.   Thus, using two field memories MF1 and MF2
By alternately performing a write operation or a read operation.
The write address signal WADR (or read
The output address signal RADR (or the output address signal RADR)
Address signal WADR)
The possibility of disturbance can be effectively avoided.   That is, as described above with reference to FIG.
For example, by overlapping writing on 13
If you try to double the size vertically, see Figure 19
As shown in (B), the field memories MF1 and MF2 are exchanged.
An enlarged image is obtained by reading or writing each other.
You.   As shown by the read address curve R0 in FIG.
The field written in the first field memory MF1.
Switch for reading image data of in-numbers 1 to 263 (horizontal axis)
Read data DATA via circuit 65_OUTRead as tie
Write switch 63, the write switch circuit 63
TA_INTo the line address 264 of the second field memory MF2.
Write to ~ 525 (vertical axis).   Thus, it was written to the second field memory MF2
The image data is then read as indicated by the read address curve R1,
Read data DATA through read switch circuit 65_OUTAs
While the data is read out sequentially,
And write data DATA_INThe data in the central part of
Write switch while being overlapped as shown by the curve W2.
Write to the first field memory MF1 via the circuit 63
Go.   Hereinafter, similarly, the data is written to the first field memory MF1.
The read O-field image data is
As shown by the curve R2, the read data is read through the read switch circuit 65.
Data_OUTAt the same time,
As shown by the response curve W3, the E field write data DATA
_INOf the central part of the data through the write switch circuit 63
To the second field memory MF2
I will be absorbed.   Thus, one field memory MF1 (or MF1)
2) In the middle of the O field (or E field)
The image data is written through the write switch circuit 63.
At the timing of going, the other field memory MF2
(Or MF1) image data through the readout switch circuit 65
Read data DATA_OUTBeing read out sequentially
, The read data DATA whose central part is doubled
_OUTCan be obtained.   By the way, during such enlargement processing, the write data DATA_INTo
Memory area to be written and image data to be read
Memory areas are different from each other
Specified by the write address signal WADR
The memory address is specified by the read address signal RADR.
May cause the phenomenon of overtaking the memory address
Can effectively avoid image distortion.
Can be prevented.   As shown in FIG. 19A, the field memory MF
Write data DATA using either 1 or MF2_INWrite
Read the written image data while writing
When going, be sure to specify by write address signal WADR
Memory address to be read is determined by the read address signal RADR.
Overtaking the specified memory address occurs.   That is, as shown by the read address curve R0,
While reading the data of line numbers 1-263
And the write data DATA as shown by the write address curve W1._IN
Of the image data in the center of the screen
As the data is written to the field memory, the center of the screen
Write address signal WADR in the memory area corresponding to
Is specified by the read address signal RADR.
Overtaking the specified address
Inevitable.   This problem is illustrated in FIGS. 10, 11 and 19 (B).
Thus, the first and second field memories MF1 and MF2 are
By alternately reading or writing,
It can be solved effectively.   In addition, as described above with reference to FIG.
When the central part is doubled by double reading
Is indicated by a read address curve R10 in FIG. 20 (B).
As described above, the write data DATA of the second field memory MF2 is
_INRead out the central portion of the image data from the switch circuit 65
Read data DATA of line numbers 1-263 via_OUTAs
And write address at the timing of this operation.
As shown by the curve W11, the write data DATA_INLine number of
Nos. 1 to 263 are sequentially written via the write switch circuit 63.
The data is written into the first field memory MF1.   Thus, sequentially write to the first field memory MF1
The image data written by the read address curve R1
As shown by 1, the image data at the center is read.
The readout data of the line numbers 264 to 525 are output through the output switch circuit 65.
Data_OUTAs the same tie
Write data DATA as shown by the write curve W12._IN
To the field memory MF2 via the write switch circuit 63.
Written sequentially.   Thus write data DATA_INAre sequentially written to the image memory 13.
In rare cases, the written image data is repeatedly read
As a result, the read data DATA whose central portion is enlarged_OUT
Can be obtained, but image data must be written
Memory area to be written and memory area to be read
Are configured to be different from each other,
As shown in FIG. 7A, designated by a read address signal
The memory address to be written is specified by the write address signal.
Phenomenon of overtaking specified memory address occurs
Risk can be effectively avoided, thus causing image distortion.
Can be prevented.   Further, as described above with reference to FIG.
Write data DATA for_INWhile thinning out
By sequentially reading the written image data,
In order to obtain a reduced image, as shown in FIG.
In the same manner as described above with reference to FIG.
Write / read operation of the flash memory MF1 and MF2 alternately.
As shown in FIG. 21 (A),
Can avoid overtaking memory addresses,
In this case, it is possible to effectively prevent
Can stop.   Further, as described above with reference to FIG.
TA_INAre sequentially written to the image memory 13 and
Read out by thinning out the embedded image data
Data DATA_OUTIn the case of obtaining
Then, as shown in FIG. 22 (B), the field memory MF1
And MF2 are sequentially alternately written or read.
As a result, additional memory addresses as shown in FIG.
It is possible to effectively prevent the possibility of passing.   Note that the method described above with reference to FIGS.
Figure 19 when the screen is enlarged or reduced
As described above, the read data DATA_OUO field at
If the relationship between E and E fields is reversed, the first
The read address control is performed in the same manner as described above for the figure.
Line shift control provided to the rule circuit 22 (FIG. 10)
The display position of the abnormal field is changed to one line by the signal SLS.
In this case, the correction may be made by the amount corresponding to the distance. (G8) Image display using enlarged read data   FIG. 10, FIG. 11, FIG. 15 and FIG.
Using such a technique, the two files constituting the image memory 13
Duplicate writing data for yield memories MF1 and MF2
Or read image data written sequentially
When the image is enlarged by performing
_OUTAs natural as possible as a magnified image represented by
Place appropriate image data in visible pixel positions
Is desirable.   As a result, as shown in FIG.
1st, 2nd, 3rd ... Lines LE1, LE2, LE3 ...
The image data for one line is represented by a, b, c,.
Also, the first, second, third ... line LO of the O field
The data of each line of 1, LO2, LO3 ... is A, B, C ...
, The image is drawn in the vertical direction, that is, the V direction.
N times, for example, n = 2 times, n = 3 times, n = 4 times, n = n
When data is enlarged twice, duplicated data or duplicated data
The display position of the data is shown in FIG. 24, FIG. 25, FIG. 26, and FIG.
As shown in the following equation.   That is, if the magnification n is an even number, the O field
The in-data display start position is the standard display start position.
From line LO1Is shifted in the V direction by the number m of lines represented by
And the display start position of the O-field line data
In the V direction with respect to the display position of the field line data
Shift.   When the magnification n is odd, the following expression is used. The number of lines represented by
Shift the display start position.   For example, when the magnification is n = 2, n = 2 is added to the equation (4).
By substituting, m = 0 or 1, so FIG.
Lines that overlap by two pixels as shown in (A) or (B)
Display start position of data A, B, C ... is standard display start
Offset from position, ie line LO1, by m = 0 or m = 1
By doing so, the O field line data A, B,
C ... is the E field line data a, b, c ...
The O-field image has a relationship that is almost in the middle
Can be displayed, and a proper enlarged image can be obtained.
It is.   When the magnification n is n = 3, this is expressed by the following equation (5).
M = 1. Therefore, as shown in Fig. 25
And the three line data A and B of the O field
The display start position of ...... is set to the standard display start position,
It is displayed at a position shifted from the LO1 by m = 1.   In this way, three overlapping fields in the E-field
O-fields adjacent to in-data a, b ...
The line data A, B ... are almost at the center of each other
Can be displayed in such a display position as
To get a large and natural image
You.   When the magnification n is set to n = 4, this is expressed by the following equation (4).
, The number m of the shifted lines becomes m = 1 or m = 2.
Become. Therefore, as shown in FIG. 26 (A) or (B), O
Of four overlapping line data A, B ... of the field
The display position is set to the line data a of the adjacent E-field,
b. Positional relationship so that they are almost in the middle of each other
Can be displayed so as to maintain the resolution
A large and natural enlarged image can be displayed.   Generally, when the magnification n is n = n, the expression (4) or
According to the equation (5), the number m of the shifted lines is m = m.   Therefore, as shown in FIG.
.. Are displayed adjacent to each other.
E-field line data a, b ...
By being able to display staggering in almost the middle position,
Displays a large-scale image with large resolution and natural
obtain.   28 to 31 corresponding to FIGS. 24 to 27.
The O field display start position is set to the standard position LO
If you display it without shifting it, you can configure the O field.
The display position of the overlapping line data A, B.
Position close to adjacent line data a, b ...
Will be displayed.   This means that when you look at the enlarged image,
And the distance between adjacent pixels in the E field
Since it will not change in a size corresponding to the multiple n,
The resolution may deteriorate and the enlarged image may look unnatural.
Result.   In this regard, if displayed as shown in FIGS. 25 to 27,
Such a problem can be prevented. (G9) Image display using reduced readout data   As described above with reference to FIGS. 10 and 11, the two
While memory memories MF1 and MF2 are operated alternately,
Write data DATA in the manner described above with reference to FIG._IN
While writing, while thinning out the image data at predetermined intervals
To extract or save to field memories MF1 and MF2
To extract and read image data while thinning it out at predetermined intervals.
Read data DATA containing the reduced image
_OUTCan be obtained.   However, in this way, extraction is performed while thinning out image data.
If you try to reduce the image by
The extraction position of the image data extracted without
Resolution may be degraded and an unnatural reduced image may result
There is.   In order to solve this problem, in this embodiment, the multiple
Input image of line data to be extracted without skipping p
The positions on the image are selected according to the following relationship.   That is, when the multiple p is an even number, the O field
In-data standard display start position, ie line LO1
La The position shifted by the number of lines p on the input image as represented by
Read line data at_OUTExtracted as
When the reduction multiple p is an odd number,Q line from the reference position LO1 on the input image as represented by
The line data at the position shifted by
_OUTExtract as   For example, when the reduction multiple p is p = 2, this is substituted into the equation (6).
, The number of shifted lines q becomes q = 0 or q = 1.
You.   Therefore, as shown in FIG.
Of the two line data following the V direction as image data,
The standard display start position, that is, the line shifted from line LO1
Line data A at a position shifted by
C, E ... are extracted. In this way, the O-field
Extracted in the E-field as line data
Line data a, c, e,.
It is possible to display the line data A, C, E.
Can be.   When the number of shift lines p is q = 1, FIG.
As shown in (B), the line to be extracted from the O field
From the reference line LO1 as B, D, etc.
Extract line data that is shifted by one line
You. In this way, it is extracted in the E field
Line data a, c, e,.
Extract line data B, D, ... of O field
Display a natural image with a large resolution and a natural size.
Can be shown.   Further, when the reduction multiple p is p = 3, this is substituted into the equation (7).
Then, the number of shift lines q becomes q = 1. This place
If O field is extracted from 3 line data
As shown in FIG. 33, the reference line
Image data B, E... Shifted by one line from LO1
Extract.   In this way, the image extracted in the E-field
Are at intermediate positions with respect to image data a, d, g,.
Line data extracted from O-field image data
By displaying B, E,..., A reduced image as a whole is displayed.
A natural image with a large resolution can be displayed as an image.   More generally, when the reduction multiple p is p = p, the shift line
The number q is q = q. In this case, as shown in FIG.
It is shifted by q lines from the O field
Line data P1, P2 ... are extracted.   In this way, the image extracted from the E-field
O data at almost the middle position for data a, k, s ...
Yield line data P1, P2, …… must be displayed
Large and natural images as reduced images
Can be displayed.   Note that FIGS. 35 to 37 correspond to FIGS. 32 to 34, respectively.
As shown in the line data to be extracted,
Position adjacent to the position of the line data extracted from
Extract the O-field line data,
Distribution of line data extracted on the image is partially biased
Read data DATA_OUTIf the resolution of the image deteriorates
It is unavoidable that both become unnatural, but Figs. 32 to 34
Extracting reduced data using methods such as
Can be prevented. (G10) Other embodiments (1) In the case of (3), the write frame number FRW and the read
When the relationship between the outgoing frame number FRR is FRW = 1 and FRR = 1
The address was separated by the detection operation.
The condition is not limited to this, (FRW, FRR) = (2, 2),
(3, 3) and (4, 4) are the same as those described above.
The effect can be obtained. (2) In the case of the embodiment shown in FIG.
The serial memory is divided into three memory areas MEM1 to MEM3.
Transfer periods to the access memory 35
But the number of memory areas is not limited to three,
I just want it. (3) In the embodiment of FIG. 6, the horizontal retrace interval TRS is set to 15
Data is transferred in units of
Transmission, but the number of clock pulses
The main point is that all messages are stored in the horizontal flyback section TRS.
What is necessary is just to be able to transfer the data of the memory area part. (4) Frame memory in the case of the embodiment shown in FIGS.
Numerical values, field memos in the case of the embodiment of FIGS. 7 and 8
The case where the number of res was set to 4 was described.
The number of memory or field memory is not limited
Anything above is fine. The number of frames or fields
If there is a margin, write address and read address
The number of frames to be separated when overtaking is detected during
Is not limited to one frame or one field.
Or fields. (5) In the embodiment shown in FIG.
Switch circuit 32 for frame and switch circuit 33 for frame allocation.
The write data DATA for the image memory 31_INShake
Switch circuit for frame selection
34 and the switch circuit 36 for selecting the memory area.
Read data DATA from image memory body 31_OUTSelect and out
Function in this configuration
Switch the write address and read address for the
Even if it can be done by changing,
Similar effects can be obtained. (6) In the embodiment of FIG. 13, the write switch circuit 63
The write data DATA to the image memory body 31_INTo
While writing while switching, the read switch circuit 65
Read data DATA from the image memory main unit 31._OUTChoose
Output while selecting and switching.
Write function to image memory body 31
And by switching the read address
However, the same effect as in the above case can be obtained.
You. Effect of H invention   As described above, according to the present invention, a random access memo
Reconfigured image memory body by multiple memory areas
Image data written to each memory area
Is sequentially transferred in units of multiple memory areas
Transfer and read as data to serial access memory
That one memo
During the data transfer period of the rear area, the other memory area
Can be written with the write data. Thus practical
The write data is always written to the image memory while
Sometimes it is necessary to maintain an asynchronous relationship with writing
From which the image data can be read
An image signal processing device can be realized.   In doing so, the image data from the memory area
Data in the horizontal retrace interval of the second image signal.
Is performed continuously, so that the output image
Noise can be prevented from being generated in the image.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an overall configuration of a first embodiment of an image signal processing apparatus according to the present invention, and FIG. 2 is a block diagram showing a detailed configuration of an image memory 13 in FIG. 3 to 5 are curve diagrams for explaining an address overtaking operation, FIG. 6 is a signal waveform diagram for explaining a transfer operation of the memory area units MEM1 to MEM3 in FIG. 2, and FIG. FIG. 8 is a curve diagram for explaining a case where a field memory is used as a second embodiment of the image signal processing apparatus according to the present invention, FIG. 8 is a curve diagram showing a third embodiment of the present invention, and FIG. FIG. 10 is a block diagram showing the general configuration of a fourth embodiment of the image signal processing apparatus according to the present invention, and FIG. 11 shows the detailed configuration of the image memory shown in FIG. Block diagram, twelfth
FIG. 14 to FIG. 14 show the write data DA when performing the enlargement or reduction processing.
TA _IN and schematic view showing an arrangement on the display screen of the pixels of the read data DATA _OUT, schematic diagram FIG. 15-FIG. 18 showing the scaling processing procedure, Fig. 19-FIG. 22 FIG. 15 FIG. 23 to FIG. 23 for explaining the operation of the image memory in the processing procedure of FIG.
FIGS. 24 to 27 are schematic diagrams showing the display position of the read data subjected to the enlargement processing, and FIGS. 28 to 31 are schematic diagrams for explaining the display position of the read data on the display screen. Figures 24 to 27
As shown in the figure, a schematic diagram showing the display position of the enlarged read data when the processing of shifting the line is not performed, FIGS. 32 to 34 are schematic diagrams showing the extraction position on the display screen of the reduced read data, and FIG.
FIGS. 37 to 38 are schematic diagrams showing extraction positions of reduced read data when the lines are not shifted as shown in FIGS.
The figure is a schematic diagram showing a multifunctional display screen, FIG. 39 is a curve diagram for explaining the operation when the read address overtakes the write address, and FIG. 40 is the overtaking shown in FIG. 39 41 is a schematic diagram for explaining the disturbance on the display screen, FIG. 41 is a curve diagram for explaining the operation of the write address overtaking the read address, and FIG. 42 is a view on the display screen due to the overtaking of FIG. 41. FIG. 4 is a schematic diagram for explaining the disturbance that occurs in FIG. DESCRIPTION OF SYMBOLS 1 ... Image signal processing apparatus, 11 ... Luminance signal / color signal separation circuit, 12 ... Analog / digital conversion circuit, 13 ... Image memory, 14 ... Write clock signal generation circuit, 15 ... Write address Control circuit, 21 ... Read clock signal generation circuit, 22 ... Read address control circuit, 23 ...
... Digital / analog conversion circuit, 24 ... Switch circuit, 25 ... Brightness / color signal separation circuit, 26 ... Display device, 31 ... Image memory body, MEM1-MEM3 ... Memory area part, (M11-M14 ) To (M31 to M34): Frame memory area, MF1, MF2: Field memory.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Kyoichi Murakami               6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo So               Knee Co., Ltd. (72) Inventor Masaharu Tokuhara               6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo So               Knee Co., Ltd.                (56) References JP-A-58-116585 (JP, A)

Claims (1)

(57) [Claims] While writing the write data corresponding to the first image signal to the image memory by the write address signal, the image data written to the image memory is read by the read address signal while reading the write data corresponding to the second image signal. By switching between image data, an image signal processing device that inserts an image based on the first image signal into an image based on the second image signal divides the input write data into a plurality of pieces. Switching means for outputting the write data divided by the switching means, an image memory configured to transmit the data stored in each of the memory area parts as parallel data, A serial access memory for receiving parallel data transmitted from each memory area of the image memory and outputting it as serial data; Control means for controlling writing and reading of the image memory and the switching means, wherein the control means sets a data processing period comprising a plurality of time slots based on a horizontal synchronizing signal of the first image signal. A time slot included in the data processing period is allocated to a transmission period from one of the plurality of memory area units to the serial access memory and a writing period to another memory area unit. Writing to the memory area is performed at discontinuous time slots, transmission to the serial access memory of each memory area is performed at a plurality of continuous time slots, and serial access to each memory area is performed. The transmission to the memory is performed in the horizontal retrace interval of the second image signal. That the image signal processing apparatus.