JP2888593B2 - Semiconductor integrated circuit system and semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a semiconductor integrated circuit system and a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit system that operates by being supplied with a plurality of power supplies, and a semiconductor integrated circuit suitable for use in the system.

[Prior art]

At present, 5 V is generally used as a standard operation power supply voltage of a semiconductor integrated circuit. However, as the size of the semiconductor integrated circuit is increased, the miniaturization of the element is promoted. As a result, the electric field in the element is increased, and various physical phenomena such as the withstand voltage of the element and hot carriers hinder the miniaturization. Therefore, to solve this problem, lower the power supply voltage,
Studies are underway to solve the problem by relaxing the electric field in the device.
There is also a move to officially adopt 3.3V as the standard operating power supply voltage for 4MDRAM and later. In addition, there is a movement to adopt a power supply voltage of 3.3 V even in a 0.5 μm class logic, and it is expected that the operating power supply voltage of the semiconductor integrated circuit will be further reduced in the future.

[Problems to be solved by the invention]

However, even if the power supply voltage is lowered to 3.3 V, it takes a considerable period of time for the hard resources to become as good as the current mainstream 5 V system hardware resources. It is expected that the system will be mixed. In this case, the following problem occurs. That is, as shown in a comparative example shown in FIG. 5, for example, output pins D01 and D11 of a 5V semiconductor integrated circuit A and a 3.3V semiconductor integrated circuit B having a CMOS tristate output buffer circuit composed of D2, P02 and N02.
Are connected to a common bus line BL, when the high-voltage side semiconductor integrated circuit A uses the bus line BL, the gates of the output buffer transistors P12 and N12 of the low-voltage side semiconductor integrated circuit B are connected to 3.3V, respectively. And the ground voltage (0 V) is applied to release the bus line BL. However, when a signal output from the high-voltage side semiconductor integrated circuit A to the bus line BL is at a high level, 5 V is applied to the drain of the transistor P12, so that the drain junction becomes conductive and the channel and the well ( Alternatively, a channel current or a well current flows from the power supply (5 V) of the semiconductor integrated circuit A to the power supply (3.3 V) of the semiconductor integrated circuit B via the substrate). Then, this current causes the semiconductor integrated circuit B on the low voltage side to latch up or to operate as a transistor.
P12 will be degraded and destroyed. Therefore, for example, as shown by a broken line in FIG.
A voltage conversion interface circuit C is provided on BL, and the bus line
There was a problem that BL could not be shared. In the figure, d is an input signal, and D2 is a level shift function for controlling the output buffer transistors P12 and N12 (semiconductor integrated circuit B), P02 and N02 (semiconductor integrated circuit A) according to the input signal d. Is a tri-state output buffer drive circuit having no. The tri-state output buffer drive circuit D2 activates the circuit when the output enable signal OE is at a high level to generate an output signal corresponding to the input signal d as shown in FIG. Are low when transistors P02, N02
(In the case of the semiconductor integrated circuit A), the transistors TP01 and TP for cutting off and releasing the data bus BL.
P-channel NOR gate 10 consisting of 02, TN01, and TN02;
N consisting of transistors TP04, TP05, TN05 and TN06
A channel-side NAND gate 12, a transistor TP03, a P-channel buffer 14 without a level shift function having a TN03, and a transistor NTP buffer 16 also having a transistor TP06, TN07, without a level shift function,
It is composed of The present invention has been made in order to solve the conventional problems, and provides a semiconductor integrated circuit system and a semiconductor integrated circuit that can directly share a bus line without passing through an interface circuit. With the goal.

[Means for Solving the Problems]

The present invention relates to a semiconductor integrated circuit system including a plurality of circuits having different power supply voltages and generating output signals having different amplitudes according to the power supply voltage, and a common bus line connecting the circuits. Whether the power supply voltage is approximately equal to the power supply voltage of the higher circuit in the well or substrate of the output p-channel transistor of the lower circuit,
The high voltage applying means for applying a higher voltage and the high level of the gate control signal applied to the gate of the output p-channel transistor are substantially equal to or higher than the power supply voltage of the circuit having the higher power supply voltage. The above object is achieved by providing a level shift circuit for boosting the voltage to a voltage, and preventing a current from flowing from a circuit having a higher power supply voltage to an output p-channel transistor of a circuit having a lower power supply voltage. The present invention also provides a semiconductor integrated circuit connected to a circuit having a power supply voltage higher than its own through a common bus line. A high voltage applying means for applying a voltage substantially equal to or higher than the voltage; and a high level of a gate control signal applied to the gate of the output p-channel transistor, which is referred to as a power supply voltage of a circuit whose power supply voltage is higher than itself. A semiconductor integrated circuit suitable for use in the system is provided by including a level shift circuit for boosting the voltage to a voltage equal to or higher than the voltage. The semiconductor integrated circuit has a p-channel transistor connected between a power supply and an output terminal, and an n-channel transistor connected between ground and the output terminal,
The two transistors are controlled in a complementary manner in response to an input signal to supply the power supply or the ground voltage to an output terminal, and the high voltage applying means includes a well or a p-channel transistor of the p-channel transistor. A voltage which is substantially equal to or higher than a power supply voltage of a circuit whose power supply voltage is higher than its own voltage is applied to the substrate, and the level shift circuit controls at least a gate control signal applied to the gate of the p-channel transistor. The high level is boosted to a voltage higher than the voltage at which the p-channel transistor is cut off. Further, the semiconductor integrated circuit includes a booster circuit for generating a voltage by itself that is substantially equal to or higher than the power supply voltage of the circuit whose power supply voltage is higher than the power supply voltage of the semiconductor integrated circuit. According to the present invention, in a semiconductor integrated circuit having at least two power supplies having different power supply voltages, an output p-channel transistor connected between a first power supply and an output terminal; And an output n-channel transistor connected to the two transistors, the two transistors being controlled in a complementary manner in response to an input signal so as to supply a voltage of the first power supply or a ground voltage to an output terminal. And
A second power supply having a higher voltage than the first power supply is connected to a well or a substrate of the output p-channel transistor;
The above object is achieved by providing a level shift circuit for increasing the high level of a gate control signal applied to the gate of the output p-channel transistor to a voltage substantially equal to the voltage of the second power supply.

[Action and effect]

According to the present invention, there is provided a semiconductor integrated circuit system having a plurality of circuits having different power supply voltages and generating output signals having different amplitudes according to the power supply voltage, and a common bus line connecting the circuits. A high voltage applying means for applying a voltage substantially equal to or higher than the power supply voltage of the higher power supply circuit to the well or substrate of the output p-channel transistor of the lower power supply voltage circuit; a level shift circuit that boosts the high level of the gate control signal applied to the gate of the p-channel transistor to a voltage that is substantially equal to or higher than the power supply voltage of the higher power supply voltage; Current is prevented from flowing into the output p-channel transistor of the other circuit from the circuit with the higher power supply voltage. Therefore, even if circuits having different power supply voltages are connected by a common bus line, current does not flow from a circuit having a higher power supply voltage to a circuit having a lower power supply voltage, which causes deterioration, destruction, and latch-up of elements. Can be prevented, and the reliability of the semiconductor integrated circuit can be improved. Also, there is no need to use an interface circuit. In particular, a semiconductor integrated circuit suitable for use in the system includes a p-channel transistor connected between a power supply and an output terminal, and an n-channel transistor connected between ground and the output terminal. The two transistors are controlled to conduct conduction complementarily in response to an input signal so as to supply the power supply or the ground voltage to an output terminal, and the high voltage applying means includes a well or a substrate of the p-channel transistor. A voltage that is substantially equal to or higher than the power supply voltage of the circuit whose power supply voltage is higher than the power supply voltage of the circuit, and the level shift circuit controls at least a high level of a gate control signal applied to the gate of the p-channel transistor. If the level is boosted to a voltage higher than the voltage at which the p-channel transistor is cut off, the above object is surely achieved. Rukoto can. In addition, in a semiconductor integrated circuit having at least two power supplies having different power supply voltages, an output p-channel transistor connected between a first power supply and an output terminal, and connected between a ground and the output terminal. An output n-channel transistor;
The two transistors are controlled in a complementary manner in response to an input signal so as to supply a voltage of the first power supply or a ground voltage to an output terminal thereof. A second power supply having a higher voltage than the first power supply is connected, and a level shift circuit that boosts a high level of a gate control signal applied to the gate of the output p-channel transistor to a voltage substantially equal to the voltage of the second power supply Is provided, it is possible to provide a semiconductor integrated circuit that reliably achieves the above object.

【Example】

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the first embodiment of the present invention, as shown in FIG.
3.3.V of the 3.3V semiconductor integrated circuit B on the low voltage side as shown in the figure.
A first transistor P01 of, for example, a P-channel MOS type connected between the 3V power supply and the output terminal D11, and a second of an N-channel MOS type, for example, connected between ground and the output terminal D11. Having a transistor N01, and complementarily controlling conduction of the transistors P01 and N01 according to an input signal d,
In the low-voltage side 3.3 V semiconductor integrated circuit B having a tri-state output buffer drive circuit D 1 for supplying the power supply or the ground voltage to the output terminal D 11, the well or substrate of the first transistor P 01 is supplied from the 5 V power supply. And a level shift circuit 20 for raising the high level of the gate control signal applied to the gate of the first transistor P01 to 5 V, as shown in FIG. The tri-state output buffer driving circuit D1 has a second
As shown in detail in the figure, the circuit is activated according to an output enable signal OE to generate an output signal according to an input signal d, or an output transistor P0
1 and N01, to release the data bus BL as a cutoff, a P-channel side NOR gate 10 including transistors TP1, TP2, TN1, and TN2;
An N-channel side NAND gate 12 including TP6, TN5, and TN6;
From the P-channel NOR gate 10 to the output transistor P01
The level of the gate control signal applied to the gate of the input signal is changed from the input signal level 0 to 3.3 V to the level 0 to match the 5 V power supply
For example, transistors TP3, TP4, TN to boost to 5V
3, a level shift circuit 20 composed of TN4, and a buffer 16 composed of transistors TP7 and TN7 for transmitting the output of the NAND gate 12 on the N-channel side to the gate of the output transistor N01. On the N-channel side, since the ground level of the high-voltage side semiconductor integrated circuit A and the low-voltage side semiconductor integrated circuit B are the same potential (ground potential), the above-mentioned problem caused by the difference in power supply voltage does not occur. For this reason, in the present embodiment, the level shift circuit 20 is received only on the P channel side to simplify the circuit configuration. It is needless to say that a similar level shift circuit may be provided on the N-channel side. In this case, the current drive amount of the transistor N01 increases, so that a larger external load can be driven at high speed. According to the present embodiment, the well or substrate of the output buffer transistor P01 is biased to 5 V, and the level shift circuit 20 incorporated in the tristate output buffer drive circuit D1 detects the signal applied to the gate of the transistor P01. The level is changed from the input signal level 0 to 3.3V to 0.
Since the voltage has been boosted to ~ 5V, the transistor P01 can be completely cut off, and even if 5V is applied from the output terminal D11 side, no channel current or well current is generated, and
The above problem can be avoided. Next, a second embodiment of the present invention will be described in detail with reference to FIG. In the second embodiment, a booster circuit HV is built in the same 3.3 V semiconductor integrated circuit B as in the first embodiment, and a bias voltage VB, for example, 5 V is obtained from a 3.3 V power supply. Things. For example, as shown in FIG. 4, the booster circuit HV includes a ring oscillator RO, an inverter INV, and capacitors C1 and C2.
And a charge pump circuit composed of transistors N1, N2, and N3, and a diode transistor that clamps the output VB boosted by the charge pump circuit at a voltage that is twice as high as the threshold voltage from a power supply (3.3V).
It consists of N4 and N5. In this embodiment, since it is not necessary to apply 5 V from the outside, the system configuration is simple. In each of the above embodiments, the semiconductor integrated circuit of the 5 V system is used as the high voltage side and the 3.3 V system is used as the low voltage side. However, the power supply voltage of the semiconductor integrated circuit and the combination thereof are not limited thereto.

[Brief description of the drawings]

FIG. 1 is a block diagram including a partial circuit diagram showing the entire configuration of a first embodiment of the present invention. FIG. 2 is a tri-state output including a level shift circuit used in the first embodiment. FIG. 3 is a circuit diagram showing a buffer circuit, FIG. 3 is a block diagram including a partial circuit diagram showing a second embodiment of the present invention, and FIG. 4 is a configuration of a booster circuit used in the second embodiment. FIG. 5 is a block diagram including a partial circuit diagram showing the entire configuration of the comparative example. FIG. 6 is a circuit diagram showing a tri-state output buffer circuit used in the comparative example. is there. A: 5V semiconductor integrated circuit, B: 3.3V semiconductor integrated circuit, BL: Bus line, P01, N01 ... Transistor, d: Input signal, D1, D2 ... Tristate output buffer drive circuit, 20: Level shift circuit, HV: Boost circuit, VB: Bias voltage.

Claims (5)

(57) [Claims] 1. A semiconductor integrated circuit system comprising: a plurality of circuits having different power supply voltages; generating a plurality of output signals having different amplitudes according to the power supply voltage; and a common bus line connecting the circuits. A high voltage applying means for applying a voltage substantially equal to or higher than the power supply voltage of the higher power supply circuit to the well or substrate of the output p-channel transistor of the lower power supply voltage circuit; a level shift circuit that boosts the high level of the gate control signal applied to the gate of the p-channel transistor to a voltage that is substantially equal to or higher than the power supply voltage of the higher power supply voltage; Wherein a current is prevented from flowing into an output p-channel transistor of the other circuit from a circuit having a higher power supply voltage. Beam. 2. A semiconductor integrated circuit connected to a circuit having a power supply voltage higher than the power supply voltage via a common bus line, wherein a well or a substrate of an output p-channel transistor includes:
Whether the power supply voltage is almost equal to the power supply voltage of the higher circuit,
A high voltage applying means for applying a voltage higher than this; and a high level of a gate control signal applied to the gate of the output p-channel transistor, the power supply voltage being substantially equal to or higher than the power supply voltage of the circuit higher than itself. A semiconductor integrated circuit, comprising: a level shift circuit that boosts a voltage. 3. The semiconductor integrated circuit according to claim 2, further comprising: a p-channel transistor connected between a power supply and an output terminal; and an n-channel transistor connected between ground and said output terminal. The two transistors are controlled in a complementary manner in response to an input signal so as to supply the power supply voltage or the ground voltage to an output terminal, and the high voltage applying means includes a well of the p-channel transistor. Alternatively, a voltage which is substantially equal to or higher than a power supply voltage of a circuit whose power supply voltage is higher than its own voltage is applied to the substrate, and the level shift circuit controls at least a gate of the p-channel transistor. A semiconductor device characterized in that a high level of a signal is boosted to a voltage higher than a voltage at which the p-channel transistor is cut off. Product circuit. 4. The semiconductor integrated circuit according to claim 2, further comprising: a booster for generating a self-generated voltage whose power supply voltage is substantially equal to or higher than a power supply voltage of a circuit higher than itself. A semiconductor integrated circuit including a circuit. 5. A semiconductor integrated circuit having at least two power supplies having different power supply voltages, comprising: an output p-channel transistor connected between a first power supply and an output terminal; An output n-channel transistor connected between the two transistors, the two transistors being controlled in a complementary manner in response to an input signal to supply an output terminal with a voltage of the first power supply or a ground voltage. A second power supply having a higher voltage than the first power supply is connected to the well or the substrate of the output p-channel transistor, and the high level of the gate control signal applied to the gate of the output p-channel transistor is changed. A semiconductor integrated circuit having a level shift circuit for boosting a voltage to a voltage substantially equal to a voltage of a second power supply.