JP2881894B2 - Resistor - Google Patents

Resistor

Info

Publication number
JP2881894B2
JP2881894B2 JP2012275A JP1227590A JP2881894B2 JP 2881894 B2 JP2881894 B2 JP 2881894B2 JP 2012275 A JP2012275 A JP 2012275A JP 1227590 A JP1227590 A JP 1227590A JP 2881894 B2 JP2881894 B2 JP 2881894B2
Authority
JP
Japan
Prior art keywords
thin film
film transistor
channel thin
polycrystalline
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2012275A
Other languages
Japanese (ja)
Other versions
JPH03217053A (en
Inventor
隆 野口
和浩 田島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2012275A priority Critical patent/JP2881894B2/en
Publication of JPH03217053A publication Critical patent/JPH03217053A/en
Application granted granted Critical
Publication of JP2881894B2 publication Critical patent/JP2881894B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路装置中等に形成される抵抗
体に関するものである。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistor formed in a semiconductor integrated circuit device or the like.

〔発明の概要〕[Summary of the Invention]

本発明は、上記の様な抵抗体において、電流の温度依
存特性が互いに逆であるnチャネル薄膜トランジスタと
pチャネル薄膜トランジスタとを接続して抵抗体を構成
することによって、抵抗値の温度依存性を小さくしたも
のである。
The present invention reduces the temperature dependence of the resistance value by connecting an n-channel thin film transistor and a p-channel thin film transistor, each of which has a temperature-dependent current characteristic opposite to each other, to form a resistor. It was done.

〔従来の技術〕 半導体集積回路装置中等の抵抗体は、一般に多結晶Si
膜によって構成されており、その他にMOSトランジスタ
等によって構成されている場合もある。
[Prior Art] A resistor in a semiconductor integrated circuit device or the like is generally made of
It is composed of a film, and may be composed of a MOS transistor or the like.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

ところで、MOS−SRAMの負荷用の抵抗体としてはMΩ
程度の高抵抗が要求され、バイポーラデバイスでもkΩ
程度の高抵抗がしばしば要求される。
By the way, MOS-SRAM load resistors are MΩ
High resistance is required, and even for bipolar devices, kΩ
A high degree of resistance is often required.

一方、多結晶Siは半導体であるので、伝導帯の下端の
エネルギをEc、フェルミ準位をEfとすると、抵抗値R
は、 R=R0exp{(Ec−Ef)/kT} と表わされる。
On the other hand, since polycrystalline Si is a semiconductor, if the energy at the bottom of the conduction band is E c and the Fermi level is E f , the resistance R
It is expressed as R = R 0 exp {(E c -E f) / kT}.

このため、高抵抗を得るためには、Efを禁制帯の中央
付近に位置させてEc−Efを大きくする必要がある。しか
し、Ec−Efを大きくすると、上記の式からも明らかな様
に、抵抗値Rの温度依存性が大きくなる。従って、多結
晶Si膜では、高抵抗で且つ抵抗値の温度依存性の小さな
抵抗体を構成することが原理的に困難であり、設計上及
び動作上のマージンが小さい。
Therefore, in order to obtain a high resistance, it is necessary to increase E c −E f by positioning E f near the center of the forbidden band. However, increasing the E c -E f, as is apparent from the above equation, the temperature dependence of the resistance value R becomes large. Therefore, in a polycrystalline Si film, it is theoretically difficult to form a resistor having a high resistance and a small temperature dependence of the resistance value, and a margin in design and operation is small.

また、MOSトランジスタでは、その相互コンダクタン
スgmは移動度μに比例するが、単結晶Siの移動度は音響
形格子振動による散乱の影響を大きく受ける。このた
め、温度が高くなれば移動度及び相互コンダクタンスが
小さくなって抵抗値が高くなり、多結晶Si膜とは逆特性
ではあるが、やはり温度依存性が大きい。
Further, in the MOS transistor, whose transconductance g m is proportional to the mobility mu, the mobility of the single crystal Si is greatly affected by scattering due to acoustic type lattice vibration. Therefore, as the temperature increases, the mobility and the transconductance decrease, and the resistance value increases. Although the characteristics are opposite to those of the polycrystalline Si film, the temperature dependence is also large.

〔課題を解決するための手段〕[Means for solving the problem]

本発明による抵抗体は、電流の温度依存特性が互いに
逆であるnチャネル薄膜トランジスタとpチャネル薄膜
トランジスタとが接続されて成っている。
The resistor according to the present invention is formed by connecting an n-channel thin film transistor and a p-channel thin film transistor whose current-dependent temperature characteristics are opposite to each other.

〔作用〕[Action]

本発明による抵抗体では、nチャネル薄膜トランジス
タとpチャネル薄膜トランジスタとで電流の温度依存性
が相殺される。
In the resistor according to the present invention, the temperature dependence of the current is offset by the n-channel thin film transistor and the p-channel thin film transistor.

〔実施例〕〔Example〕

以下、本発明の実施例を第1図及び第2図を参照しな
がら説明する。
An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

本実施例は、樹枝状(デンドライト)多結晶Si膜を能
動層とするnチャネル及びpチャネル薄膜トランジスタ
を形成し、これらの薄膜トランジスタを第1A図または第
1B図の様に接続したものである。
In this embodiment, an n-channel and p-channel thin film transistor having a dendritic polycrystalline Si film as an active layer is formed, and these thin film transistors are formed as shown in FIG. 1A or FIG.
They are connected as shown in Fig. 1B.

樹枝状多結晶Si膜を形成するには、通常の多結晶Si膜
にSi+をイオン注入して非晶質化するか、または低温で
当初から非晶質Si膜を形成し、これらの非晶質Si膜を60
0℃程度の低温でアニールして固相成長させる。
To form a dendritic polycrystalline Si film, a normal polycrystalline Si film is made amorphous by ion implantation of Si + , or an amorphous Si film is formed from the beginning at a low temperature, 60 crystalline Si films
Anneal at a low temperature of about 0 ° C. for solid phase growth.

樹枝状多結晶Siでは、通常の多結晶Siよりも、粒径が
大きく且つ粒界の電気性特性も改善されているので、ト
ラップが少ない。このため、樹枝状多結晶Siは単結晶Si
と通常の多結晶Siとの中間的な性質を有している。
Dendritic polycrystalline Si has a larger grain size and improved electrical properties of grain boundaries than ordinary polycrystalline Si, and therefore has fewer traps. For this reason, dendritic polycrystalline Si is
Has properties intermediate between that of ordinary polycrystalline Si.

ところで、既述の様に、単結晶Siの移動度は音響形格
子振動による散乱の影響を大きく受けるので、温度が高
くなれば移動度が小さくなる。
By the way, as described above, the mobility of single-crystal Si is greatly affected by the scattering due to the acoustic lattice vibration. Therefore, the mobility decreases as the temperature increases.

これに対して、通常の多結晶Siではトラップが多いの
で、その移動度はイオン化不純物による散乱の影響を大
きく受ける。このため、温度が高くなれば移動度は大き
くなる。
On the other hand, since ordinary polycrystalline Si has many traps, its mobility is greatly affected by scattering by ionized impurities. Therefore, the mobility increases as the temperature increases.

しかし、上述の様に樹枝状多結晶Siは単結晶Siと通常
の多結晶Siとの中間的な性質を有しているので、その移
動度は温度依存性自体が小さい。
However, as described above, dendritic polycrystalline Si has intermediate properties between single-crystal Si and ordinary polycrystalline Si, and thus the mobility itself has a small temperature dependence.

第2図は、本実施例の様に樹枝状多結晶Si膜を能動層
とし、ゲート幅及びゲート長が夫々20μm及び7μmで
あるnチャネル薄膜トランジスタと、ゲート幅及びゲー
ト長が夫々40μm及び7μmであるpチャネル薄膜トラ
ンジスタとの、電流の温度依存特性を示している。
FIG. 2 shows an n-channel thin film transistor having a dendritic polycrystalline Si film as an active layer and a gate width and a gate length of 20 μm and 7 μm, respectively, and a gate width and a gate length of 40 μm and 7 μm, respectively. 9 shows temperature dependence of current with a certain p-channel thin film transistor.

この第2図から明らかな様に、nチャネル薄膜トラン
ジスタでは通常の多結晶Si膜を能動層とした場合の特性
が若干残っており、pチャネル薄膜トランジスタでは単
結晶Si基板を用いた場合の特性が若干現れているが、電
流依存性自体は共に小さい。
As is apparent from FIG. 2, the characteristics of the n-channel thin film transistor when the ordinary polycrystalline Si film is used as the active layer remain slightly, and the characteristics of the p-channel thin film transistor when the single crystal Si substrate is used are slightly different. Although appearing, the current dependence itself is small.

従って、第1図に示した本実施例では、nチャネル薄
膜トランジスタとpチャネル薄膜トランジスタとで電流
の温度依存性が相殺され、全体の抵抗値の温度依存性が
非常に小さい。
Therefore, in the present embodiment shown in FIG. 1, the temperature dependence of the current is canceled out by the n-channel thin film transistor and the p-channel thin film transistor, and the temperature dependence of the entire resistance value is very small.

また、薄膜トランジスタの能動層を構成している樹枝
状多結晶Si膜の膜厚を薄くする程、単位面積当りの見掛
のトラップが少なくなるので、抵抗値の温度依存性を小
さくするのに効果的である。
In addition, as the thickness of the dendritic polycrystalline Si film constituting the active layer of the thin film transistor is reduced, apparent traps per unit area are reduced, which is effective in reducing the temperature dependence of the resistance value. It is a target.

以上の様な本実施例の抵抗体の抵抗値を調整するに
は、例えば、ゲート長を一定にしておき、ゲート幅を変
動させることによって行う。
In order to adjust the resistance value of the resistor of the present embodiment as described above, for example, the gate length is kept constant and the gate width is varied.

なお、バイポーラデバイスではその製造プロセス中に
薄膜トランジスタの製造プロセスを含んでいないのでこ
のプロセスを追加する必要があるが、MOS−SRAM等の様
に元々薄膜トランジスタの製造プロセスを含んでいる場
合はプロセスは従来通りでよい。
In the case of bipolar devices, this process must be added because the manufacturing process of the thin film transistor is not included in the manufacturing process.However, when the manufacturing process of the thin film transistor is originally included, such as in a MOS-SRAM, the process is conventionally performed. You can be on the street.

〔発明の効果〕〔The invention's effect〕

本発明による抵抗体では、nチャネル薄膜トランジス
タとpチャネル薄膜トランジスタとで電流の温度依存性
が相殺されるので、抵抗値の温度依存性が小さい。
In the resistor according to the present invention, the temperature dependence of the current is canceled out by the n-channel thin film transistor and the p-channel thin film transistor, so that the temperature dependence of the resistance value is small.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の実施例の回路図、第2図は樹枝状多結
晶Si膜を能動層とするnチャネル及びpチャネル薄膜ト
ランジスタの電流の温度依存特性を示すグラフである。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a graph showing temperature-dependent characteristics of current of an n-channel and p-channel thin film transistor having a dendritic polycrystalline Si film as an active layer.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 FI H01L 27/092 (58)調査した分野(Int.Cl.6,DB名) H01L 21/8234 - 21/8238 H01L 21/8249 H01L 27/04 H01L 27/06 H01L 27/088 - 27/092 ──────────────────────────────────────────────────続 き Continuing on the front page (51) Int.Cl. 6 identification code FI H01L 27/092 (58) Investigated field (Int.Cl. 6 , DB name) H01L 21/8234-21/8238 H01L 21/8249 H01L 27/04 H01L 27/06 H01L 27/088-27/092

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】電流の温度依存特性が互いに逆であるnチ
ャネル薄膜トランジスタとpチャネル薄膜トランジスタ
とが接続されて成る抵抗体。
1. A resistor formed by connecting an n-channel thin film transistor and a p-channel thin film transistor whose current-dependent temperature characteristics are opposite to each other.
JP2012275A 1990-01-22 1990-01-22 Resistor Expired - Lifetime JP2881894B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012275A JP2881894B2 (en) 1990-01-22 1990-01-22 Resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012275A JP2881894B2 (en) 1990-01-22 1990-01-22 Resistor

Publications (2)

Publication Number Publication Date
JPH03217053A JPH03217053A (en) 1991-09-24
JP2881894B2 true JP2881894B2 (en) 1999-04-12

Family

ID=11800817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012275A Expired - Lifetime JP2881894B2 (en) 1990-01-22 1990-01-22 Resistor

Country Status (1)

Country Link
JP (1) JP2881894B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2887032B2 (en) * 1992-10-30 1999-04-26 シャープ株式会社 Thin film transistor circuit and method of manufacturing the same

Also Published As

Publication number Publication date
JPH03217053A (en) 1991-09-24

Similar Documents

Publication Publication Date Title
JP2658570B2 (en) Semiconductor device and manufacturing method thereof
US5448093A (en) Micro MIS type FET and manufacturing process therefor
JP2881894B2 (en) Resistor
JPH04181779A (en) Thin film transistor
JPH03228365A (en) Semiconductor resistor circuit
US6437403B1 (en) Semiconductor device
JPS60136262A (en) Field effect transistor
JP3146504B2 (en) Semiconductor electronic circuit
JPH03291972A (en) Mos thin-film transistor
JPS6110992B2 (en)
JPH0722515A (en) Semiconductor integrated circuit
JPH0513443A (en) Integrated circuit
JPH10223654A (en) Method of forming compound semiconductor element which restrains temperature dependence
JPH0427153A (en) Semiconductor integrated circuit device
JPS607126A (en) Manufacture of semiconductor device
JPH01770A (en) Compound semiconductor integrated circuit
JPS59132163A (en) Semiconductor device
JPS58178569A (en) Manufacture of semiconductor device
JPH0231462A (en) Semiconductor element
JPS59228763A (en) Semiconductor device
JPS6245164A (en) Semiconductor integrated circuit device
JPS60192368A (en) Manufacture of amorphous silicon semiconductor device
JPH09129866A (en) Semiconductor device
JPS6195569A (en) Manufacture of compound semiconductor integrated circuit
JPS6031279A (en) Mos semiconductor device

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080205

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090205

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100205

Year of fee payment: 11

EXPY Cancellation because of completion of term