JP3146504B2 - Semiconductor electronic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor electronic circuit which does not lower the current supply capability and which is not affected by the ambient temperature.

[0002]

2. Description of the Related Art In recent years, there has been a demand for the development of devices that can operate in a high-temperature atmosphere and devices whose characteristics are not affected by temperature even when the ambient temperature fluctuates. However, in a general nonlinear element using a semiconductor, it is inevitable that the characteristics of the element slightly change depending on the ambient temperature. This is because physical properties of the semiconductor, such as mobility and carrier energy distribution, greatly depend on temperature.

For example, in single crystal silicon, as the temperature increases, scattering of carriers due to the crystal lattice increases, and the mobility of carriers decreases. In general, it is known that the mobility decreases in proportion to the temperature raised to the power −1.5 to −2.5. If the chip temperature rises to 300 ° C., the carrier mobility decreases to about ３ to の of the mobility at room temperature (25 ° C.). Since the drain current of the MOSFET is proportional to the carrier mobility in the saturation region, for example, if a drain current of 1 mA flows at room temperature, only a drain current of approximately 0.3 mA flows in a 300 ° C. atmosphere. As a result, this may cause malfunction or failure of the device using the semiconductor element. In order to improve the temperature instability of a device using the device due to the temperature dependence of the characteristics of the device itself, generally, the operating region of the device is limited, and the device is placed in a range in which the temperature varies as little as possible. It works only with.

It is known that a general MOSFET has a so-called temperature-insensitive operating point where the temperature coefficient of its output is normally zero. FIG. 4A is a characteristic diagram showing a relationship between a gate voltage and a drain current of a single-crystal SiMOSFET manufactured by a standard process using temperature as a parameter. The intersection of all curves at one point indicates that the same set of gate voltage and drain current exists at any temperature. The temperature dead point is Z
It is called TC (Zero Temperature Coefficient) point.
At the ZTC point, once the potential of each electrode is fixed, the output (drain) current does not change at any temperature. This is because the tendency of the drain current to decrease due to the decrease in the mobility with the temperature rise and the tendency to increase the drain current due to the increase in the drain-substrate junction current are balanced.

By setting the bias gate voltage of the MOSFET to the ZTC point due to such characteristics, a device whose characteristics are not affected by temperature can be constituted.
This method is used in operational amplifiers.

[0006]

However, in a MOSFET in which the active region is formed of single-crystal silicon, the ZTC point exists in the non-saturated region in the operating characteristics, as shown in FIG. Therefore, if MOSFE
If T is used in a saturation region in operating characteristics, it is possible to increase the drain current. However, on the other hand, the temperature coefficient of the drain current increases, and the characteristics of the device greatly depend on the temperature. Conversely, when the gate voltage is set at the ZTC point, the influence of the temperature decreases, but the MO
Since the operating characteristics of the SFET are not saturated, there is a problem that the drain current cannot be increased. In order to increase the drain current by setting the gate voltage to the ZTC point, the area of the element has to be increased in the conventional MOSFET.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide an electronic circuit having no temperature dependence of an output current and a large current supply capability without increasing the size of an element. Is to configure.

[Means for Solving the Problems]

The present inventor has conducted various studies on the region where the ZTC point exists on the operating characteristic curve of the MOSFET. As a result, the active region of the MOSFET has an average crystal grain size of 1-10 μm.
It has been discovered for the first time that the ZTC point can be made to exist near or in a saturation region of the transistor by using m polycrystalline silicon. The present invention is based on this finding. That is, according to the present invention, according to the input voltage,
In a semiconductor electronic circuit for controlling a supply current, an insulated gate field effect transistor having an active layer of polycrystalline silicon having an average crystal grain size of 1 to 10 μm, and a bias voltage applied between a gate and a source of the transistor are set to a drain current. In the temperature characteristics, the average formation of polycrystalline silicon in the active layer
And a bias circuit for providing a voltage substantially independent of temperature according to the crystal grain size . It also depends on temperature
Bias voltage is in the saturation region or saturation on the operating characteristic curve.
It is characterized by being present near the sum area. Furthermore, polycrystalline
That the average crystal grain size of silicon is 1.6-3 μm
Features. The inventor measured the average crystal grain size of polycrystalline silicon, that is, the relationship between the size of the domain constituting the single crystal silicon microscopically and the position of the ZTC point on the operating characteristic curve. As a result, the present inventors set the crystal grain size to 1.
By setting the ZTC point to MOSFET
It has been found for the first time that it is possible to exist near the saturation region on the operating curve of the. A more desirable range of the crystal grain size is 1.6 to 3 μm. Note that the above characteristic is M
The same applies to other insulated gate field effect transistors of OSFETs.

[0009]

The active layer of the insulated gate field effect transistor is made of polycrystalline silicon having an average crystal grain size of 1.0 to 10 μm. The bias voltage applied between the gate and the source of the transistor depends on the temperature characteristics of the drain current and the polycrystalline silicon in the active layer.
The voltage is set to be substantially independent of temperature according to the average crystal grain size of the metal . Therefore, the bias voltage can be set at the ZTC point, and the ZTC point can be present in the saturation region or near the saturation region on the operating characteristic curve.
Therefore, the current supply capability could be increased without increasing the element size of the transistor, and the temperature dependence of the supply current could be reduced. In particular, by setting the crystal grain size of polycrystalline silicon to 1.6 to 3 μm, the above-described effects were remarkably obtained.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to a specific embodiment. FIG. 1 is a configuration diagram of an embodiment apparatus in which the present invention is applied to a digital logic integrated device with a built-in power supply circuit. This device 10 includes a stabilized power supply unit 1, a digital logic circuit unit 2,
It comprises a level adjustment circuit section 3 and an output circuit section 4. The logic circuit section 2 is formed on single crystal silicon, and the stabilized power supply section 1, the level adjustment circuit section 3 and the output circuit section 4 are formed on polycrystalline silicon having an average crystal grain size of 2.4 μm. I have. Each circuit includes a MOSFET. These circuit units 1 to 4 are all formed on the same chip.

The stabilized power supply unit 1 converts, for example, a voltage of 12 V of a vehicle-mounted battery to 3 V, and supplies a stabilized voltage to the logic circuit unit 2. The relationship between the stabilized power supply unit 1 and the logic circuit unit 2 can be represented by an equivalent circuit as shown in FIG. E denotes output terminals 1a and 1 of the stabilized power supply unit 1.
open voltage generated between both terminals when b is opened,
That is, it is the internal electromotive force of the stabilized power supply unit 1. r ₀ is the output resistance of the stabilized power supply unit 1, and v ₀ is the voltage between the output terminals 1 a and 1 b in the connection state of FIG. 2, that is, the supply voltage to the logic circuit unit 2. r _i is an input resistance of the logic circuit unit 2. I ₀ is an output current supplied to the logic circuit unit 2.

As is apparent from the equivalent circuit shown in FIG. 2, the fluctuation of the internal electromotive force E or the output current I _{0 due to} the temperature makes the supply voltage v ₀ to the logic circuit 2 unstable. On the other hand, stabilization of the supply voltage v _{0 to} the logic circuit unit 2 is necessary to improve the reliability of the logic operation of the logic circuit unit 2. Therefore, it is necessary to reduce the temperature fluctuation of the internal electromotive force E or the output current I ₀ without lowering the output current supply capability.

FIG. 3 shows a specific circuit configuration of the stabilized power supply unit 1. The transistor Tr1 is an output transistor of the stabilized power supply unit 1. The transistor Tr1 is an MOSFET in which an active layer, that is, a layer in which a channel is formed between a source and a drain is made of polycrystalline silicon. The bias circuit consisting of resistor R ₁ and the series-connected Zener diode D _Z of the two elements, the gate G of the transistor Tr1 is biased. That is, the gate voltage applied to the gate G of the transistor Tr1 voltage determined by the breakdown voltage of the Zener diode D _Z, in the present embodiment is 11V.

The bias voltage 11V is a voltage sufficient to bring the operation state of the transistor Tr1 into a state close to the saturation region on the operation curve. Here, the saturation region is an operation region where the output current does not increase so much even when the transistor Tr1 is sufficiently turned on and the bias voltage is increased. By applying this bias voltage 11V,
By setting the value of the drain D is connected to the resistor R ₂ appropriately, the drain of the transistor Tr1 D and the source S
The voltage between them can be 3V. The bias voltage 11 V can be set to the ZTC point by configuring the active layer of the transistor Tr1 with polycrystalline silicon. That is, the bias voltage corresponding to the ZTC point can be increased by using polycrystalline silicon for the active layer of the transistor.

FIG. 4A is a characteristic diagram in which the relationship between the gate voltage and the drain current of a transistor Tr1 whose active layer is made of polycrystalline silicon is measured using temperature as a parameter. FIG. 4B is a characteristic diagram in which the relationship between the gate voltage and the drain current of a transistor in which the active layer is made of single-crystal silicon as in the prior art and whose temperature is used as a parameter is measured with the same element size as the transistor. It is. As can be understood from these two characteristic diagrams, the ZTC point exists on the higher voltage side in the transistor made of polycrystalline silicon as compared with the transistor made of single crystal silicon. Therefore, when the voltage at the ZTC point is used as the bias voltage, the polycrystalline silicon transistor has a current supply capability of 100 times that of the single crystal silicon transistor.
It turns out that it is twice as high. This means that when the transistor dimensions are the same and both transistors are in the state where the best temperature characteristics are obtained, the current supply capability of the polycrystalline silicon transistor is 100 times higher than that of the single crystal silicon transistor. Means that.

In order to increase the number of fan-outs of the output circuit section 4, it is desirable that the output current be large. Therefore, also in the output circuit section 4, the MOSFET made of polycrystalline silicon used in the above-mentioned stabilized power supply section 1 is used.

In the logic circuit section 2, the signal transmission speed is more important than the current supply capability. Therefore, the logic circuit unit 2
The transistor used in the above was single crystal silicon. In the logic circuit section 2, since the current supply capability is not so required, the bias voltage is set to a lower ZT than that of polycrystalline silicon.
It can be set to point C. Therefore, the temperature fluctuation of the operation characteristics can be reduced.

The signal level adjusting circuit unit 3 includes the logic circuit unit 2
Is a circuit for adjusting the output signal level of the output circuit section to the input signal level of the output circuit section 4. In this embodiment, since the single crystal and polycrystalline substrates are insulated and separated, the signal level adjusting circuit unit 3 can be formed on the polycrystalline silicon substrate as it is.

Next, a method of manufacturing the circuit board of the present embodiment will be described with reference to FIG. The surface of the single crystal silicon substrate 30 shown in FIG. 5A is thermally oxidized to form a thermal oxide film 31 having a thickness of 0.5 μm as shown in FIG. This thickness is arbitrary. Next, as shown in FIG.
Polycrystalline silicon film 32 was formed on thermal oxide film 31 as follows. In a 100% SiH ₄ gas at 610 ° C. and a pressure of 1 Torr by LPCVD, 1-3 μm
After depositing silicon to a thickness of 1 with N ₂ gas atmosphere
Heat treatment was performed at 200 ° C. for 13 hours, and silicon was grown until the average crystal grain size became 1.6 to 3 μm. Further, the surface of the grown film was flattened. This polycrystalline silicon film 32 can be formed by the above-described method, or can use many means such as a recrystallization method and a solid phase growth method.
The crystal grain size needs to be 1.6-3 μm.

After the formation of the polycrystalline silicon film 32, a resist 33 was applied to a portion where the polycrystalline silicon film 32 was left as shown in FIG. Then, (e) of FIG.
As shown in FIG.
2 and the thermal oxide film 31 were removed by etching to partially expose the single crystal silicon substrate 30. After the formation of such a substrate, the polycrystalline silicon film 3 shown in FIG.
This circuit was formed on the second and single crystal silicon substrates 30 by a normal MOS process. That is, the polycrystalline silicon film 3
2, a stabilized power supply unit 1, a signal level adjustment circuit unit 3, and an output circuit unit 4 were formed, and a logic circuit unit 2 was formed on a single crystal silicon substrate 30.

According to the above process, the thickness of the polycrystalline silicon film 32 is changed in various ways to produce the polycrystalline silicon films 32 having different crystal grain sizes.
A MOSFET was manufactured on the polycrystalline silicon film 32.
Then, the relationship between the gate voltage and the drain current of these MOSFETs, that is, the operating characteristics were measured while changing the temperature. The results are shown in FIGS. 6B to 7F.
As a comparative example, the operating characteristics of a single-crystal silicon MOSFET were measured while changing the temperature. The result is shown in FIG.

[0022] In the range gate voltage V _G is less of 20V is,
It is understood that the relationship between the crystal grain size and the ZTC point is as follows.

[0023]

TABLE 1 no crystal grain size ([mu] m) ZTC point gate voltage V _G (V) the drain current I _D (mA) 0.9 or less. 1.6 20 1 2.0 13 0.95 2.4 11 2.0 Single crystal 1.5 0.009

[0024] From the above measurement results, the relationship ZTC point (gate voltage V _G and the drain current I _D) and the crystal grain size 8
Shown in From the above measurement results, the crystal grain size is 1.6 to 2.
In the range of 4 μm, the drain current at the ZTC point is 1 to 2
mA. This drain current is 100 to 200 times the drain current at the ZTC point of the single crystal silicon MOSFET. It is also understood that as the crystal grain size increases, the gate voltage at the ZTC point decreases, and there may exist a crystal grain size at which the drain current has a maximum value. From the above measurement results, the desirable range of the crystal grain size of polycrystalline silicon in which the drain current at the ZTC point is about 100 times or more that of single crystal silicon is as follows.
Expected to be 0-10 μm. Further, a desirable range is
1.6 to 3 μm.

In this embodiment, the transistor requiring a large power supply capability is constituted by a MOSFET having an active layer of polycrystalline silicon having the above average crystal grain size, and the transistor requiring a large signal transmission speed is a single crystal silicon. Is an active layer. With such a configuration, an electronic circuit with good temperature stability and high power supply capability can be obtained without increasing the element area. In this embodiment, polycrystalline silicon and single crystal silicon are formed on the same substrate, but they may be formed on separate substrates. Furthermore, only the single crystal silicon device chip is cooled or kept away from a high temperature atmosphere,
A polycrystalline silicon device chip may be placed in a location exposed to high temperatures. In addition, a method shown in FIG. 9 may be used to form polycrystalline silicon. That is, by periodically ion-implanting (43) impurity Si into the single-crystal silicon substrate 40 using the mask 41, a crystal state equivalent to a polycrystalline grain boundary can be obtained.
Even when a MOSFET is manufactured on such a substrate, ZT
The drain current at point C can be increased. In addition, ZTC is determined by combining different types of substrate materials.
It is also possible to change the points.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a one-chip device equipped with an electronic circuit according to a specific embodiment of the present invention.

FIG. 2 is an equivalent circuit showing a relationship between a stabilized power supply unit and a logic circuit unit of the device according to the embodiment.

FIG. 3 is a circuit diagram of a stabilized power supply unit of the device according to the embodiment.

FIG. 4 is a measurement diagram in which operating characteristics of a polycrystalline silicon MOSFET and a single-crystal silicon MOSFET are measured while changing temperature.

FIG. 5 is an explanatory view showing a manufacturing step of the device according to the example.

FIG. 6 shows a single crystal silicon and a polycrystalline silicon MOSFE.
FIG. 9 is a measurement diagram of the operating characteristics of T measured with changing temperature.

FIG. 7 is a measurement diagram in which operating characteristics of a polycrystalline silicon MOSFET are measured while changing temperature.

FIG. 8 is a measurement diagram showing the relationship between the ZTC point and the crystal grain size in the operating characteristics of the MOSFET.

FIG. 9 is an explanatory diagram showing a device manufacturing method according to another embodiment.

[Description of Signs] 30 ... Single-crystal silicon substrate 31 ... Thermal oxide film 32 ... Polycrystalline silicon film

──────────────────────────────────────────────────続 き Continued on the front page (56) References JP-A-2-74070 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21 / 8234 H01L 27/088 H03F 1/30

Claims (3)

(57) [Claims] 1. A semiconductor electronic circuit for controlling a supply current according to an input voltage, comprising: an insulated gate field effect transistor having an active layer of polycrystalline silicon having an average crystal grain size of 1.0 to 10 μm; and a bias voltage applied between the source, the temperature characteristic of the drain current, multi of the active layer
A semiconductor electronic circuit, comprising: a bias circuit for setting a voltage substantially independent of temperature according to an average crystal grain size of crystalline silicon . 2. The temperature-independent bias voltage,
Exists in or near the saturation region on the operating characteristic curve
The semiconductor electronic circuit according to claim 1, wherein: 3. An average crystal grain size of the polycrystalline silicon is
2. The method according to claim 1, wherein the thickness is 1.6 to 3 [mu] m.
The semiconductor electronic circuit according to claim 2.