JP2876737B2 - Program event recording processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a program event recording processing method for extending the function of program event recording for improving the efficiency of program debugging. For the purpose of expansion, in the program event recording processing method of the information processing device,
An address comparison stop signal output from an address comparison stop mechanism for detecting an event including an instruction fetch event and a recording area change event, and a program event recording mechanism output for detecting an event including an instruction fetch event and a storage area change event There is provided switching means for switching the output by taking a logical sum with an interrupt signal and outputting the address comparison stop signal and the interrupt signal by a program command, and outputting by taking the logical sum. It is configured to be an interrupt signal.

[Industrial Application Field] The present invention relates to a program event recording processing method for extending the function of program event recording for improving the efficiency of program debugging.

The program event recording is a function that, when a predetermined event is detected to collect trace information of the program operation, causes a program interrupt by hardware and notifies the control program of the event that caused the interrupt. The predetermined events include a successful branch event in which the program was able to branch correctly when the program came to a branch, an instruction fetch event in which a predetermined instruction was correctly read from memory,
There are a storage area change event that changes the storage content of the memory, a general register change event that changes the storage content of the general register, and the like, and which event is selected can be designated by a program. In the case of an instruction fetch event and a storage area change event, the range of the storage area can be specified by a program.

[Conventional technology]

Latches, comparators, and the like for efficiently executing program debugging work in an information processing device that performs pipeline processing
A program event recording mechanism composed of a processing circuit and the like is provided. The instruction fetch storage area in the instruction fetch event and the storage area to be subjected to the recording area change event are specified in consideration of the relationship with the above hardware. Usually, the designated area is one place (range).

[Problems to be solved by the invention]

The reason why the number of the registers is one is that the hardware amount of the register and the comparator that determine the storage area constituting the program event recording mechanism occupies a considerable amount. For this reason, in the prior art, the designation of the storage area of the instruction fetch event and the storage area change event can be performed only one at a time, so that the use of the program debugging means is limited. A problem had arisen.
Further, the addition of a program event recording mechanism significantly increases the amount of hardware described above, which is not desirable.

Incidentally, an address comparison and stop mechanism having a mechanism similar to the program event recording mechanism is usually provided in an information processing apparatus that performs pipeline processing.

The address comparison stop mechanism is a mechanism originally used for hardware debugging. The hardware tester inputs an address specified from the operator console, and when an event such as instruction fetching or storage area change is detected, the CPU (center A function to stop a CPU or the like when an address is accessed by a processing device or the like, or to generate an interrupt, thereby facilitating investigation of a design failure.

The present invention utilizes the circuit of the address comparison and stop mechanism to extend the program event recording function so that the program event recording function can be exhibited when the address comparison and stop mechanism is not used, thereby improving the efficiency of program debugging. It is an object of the present invention to provide an improved program event recording mechanism.

[Means for solving the problem]

FIG. 1A is a principle diagram of the present invention, and FIG. 1B shows a list of input / output signals of the block diagram shown in FIG.

The address comparison stop signal B output from the address comparison stop mechanism 2 and the interrupt signal A output from the program event recording mechanism 1 are input to the switching means 3. Switching means 3
Is configured to output the logical sum A + B of the address comparison stop signal B and the interrupt signal A as an interrupt signal in response to the program command E, and to output the address comparison stop signal B and the interrupt signal A as the interrupt signal A, respectively. I do. By switching the value of E to 1,0, outputs X and Y shown in (b) are obtained.

(Operation)

With the above configuration, when the address comparison and stop mechanism 2 needs to exhibit its function, the switching means 3 outputs an address comparison stop signal B, and the program event recording mechanism 1 outputs an interrupt signal A. , So that each mechanism performs its own function. When the function of the address comparison stop function 2 is stopped and the function of the program event recording mechanism 1 is expanded, the switching means 3 is switched to output the logical sum A + B of the address comparison stop signal B and the interrupt signal A. By using the logical sum A + B as an interrupt signal, the capability of the program event recording mechanism 1 is doubled.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

2A and 2B are block diagrams showing the configuration of an embodiment of the present invention, and FIG. 3 is a detailed diagram of the switching circuit 3 shown in FIG. 2A.

2A and 2B, the configuration of this embodiment is roughly divided into a program event recording mechanism 1, an address comparison and stop mechanism 2, and outputs of these two mechanisms 1 and 2 output as a logical sum according to a program command. It comprises a switching circuit 3 that outputs the outputs of the mechanisms 1 and 2 as they are. The program event recording mechanism 1 and the address comparison and stop mechanism 2 are usually provided in an information processing apparatus for performing pipeline processing in order to improve the efficiency of program debugging. In this embodiment, the function of inputting an address from the operator console, which is the original role of the address comparison and stopping mechanism 2, and detecting an event of instruction fetching and storage area change by designating the range of the storage area is utilized as it is. Most of the circuits of the address comparison and stop mechanism 2 are shared so that the program event recording can be executed when the program address is not required. A small control circuit has been added so that an address can be specified from a program, and a signal that stops the CPU when a specified event is detected in this circuit causes a program interrupt for program event recording to occur. Is what you do.

The present embodiment is an apparatus constituting a part of an information processing apparatus for performing pipeline processing, and thus operates in a machine cycle of pipeline processing. The machine cycle of this embodiment includes a D step for performing instruction decoding, an A cycle for generating an address, a T cycle for performing address conversion, a B cycle for reading out a buffer memory, an E cycle for performing an operation, and a W for performing a write to a register or a memory. It consists of six cycles. 2A, T, B, shown at the top of FIG. 2B,
E and W represent these cycles. In a pipeline-controlled computer, each processing cycle operates independently, receives new processing requests one after another from the preceding processing cycle, performs the processing specified in that cycle, and sends it out to the next cycle.

First, the program event recording mechanism 1 shown in FIG. 2A will be described. Input operand OP_EAG of effective address
TOAR11 (T-cycle operand address register)
And a TIAR21 (T-cycle operand address register) for inputting an A-cycle instruction address register signal AIAR, a control register CR31 for storing the specification of a start position when a range of a storage area is specified, and an end position Control register CR32 that stores the specification of
Provided in the cycle. A bus for inputting a position signal from a program is connected to CR31 and CR32. The comparators 12 and 13 and the logic circuit 14 output the OP_EAG signal from CR31 and CR3.
It outputs a signal as to whether or not it is in the storage area set to 2. The comparators 22 and 23 and the logic circuit 24 output the AIAR signal
Outputs a signal indicating whether it is in the storage area set to 1 and CR32.

The signal output from the logic circuit 14 is output as an operand store program event record signal (W_OP_STORE_PER) through the latches 15, 16, and 17 in each cycle B, E, and W. The signal output from the logic circuit 24 is also output in each cycle B , E, and W, are output as instruction fetch / program event recording signals (W_IF_PER) through latches 25, 26, and 27. The operation as the program event recording mechanism 1 is based on both signals (W_OP_STORE_PE
R, W_IF_PER) causes a program interrupt.

Next, the address comparison stopping mechanism 2 shown in FIG. 2B will be described. Operand logical address register OP_L
AR41 is a register for inputting a logical address to be read from the buffer memory, and instruction fetch / logical address register IF_LAR51 is a register for inputting an address of an instruction to be read from the buffer. Stop register ST
OP_REG71 and stop register STOP_REG72 are registers for respectively storing the start and end positions of the storage area specified by the operator console. In this embodiment, the input bus has the same speed as the input bus to the control registers CR31 and CR32 so that the storage area can be specified from the program when the program event recording operation is performed. The output signal of OP_LAR41 is supplied to comparators 42 and 43 and a logic circuit 44.
Is detected in the storage areas respectively set in the STOP_REGs 71 and 72, and through the latches 46 and 47, in the write cycle W, the operand address stop signal (W_
OP_ADRS_STOP). Similarly, the output signal from IF_LAR51 is also set to STOP_REG7 by comparators 59 and 60 and logic circuit 61.
It is detected whether or not it is in the storage areas respectively set to 1, 72, and through the latches 62, 63, 64, 65, 66, 67, the instruction fetch / address stop signal (W_IF
_ADRS_STOP). The latches 63 to 64 are provided for adjusting the cycles because the operation times of the OP_LAR41 and the IF_LAR51 are different. The operation as the address comparison stopping mechanism 2 is based on the two signals (W_OP_ADRS_ST).
OP, W_IF_ADRS_STOP) to stop the CPU. The output signals of the program event recording mechanism 1 and the address comparing and stopping mechanism 2 are processed by the switching circuit 3 shown in FIG. 2A newly provided in this embodiment.

Next, the switching circuit will be described in detail with reference to FIG. The switching circuit 3 is controlled by a program event recording switching signal PER_ENB specified by a program. When PER_ENB = 1, W_
The OP_ADRS_STOP signal and the W_IF_ADRS_STOP signal are
The OR of the W_OP_STORE_PER signal, the W_IF-PER signal, and the OR circuit 77 is obtained through the steps 5 and 76. As a result, the signal from the address comparison and stop mechanism 2 is detected as a program event recording signal, causing the program to be fetched and not stopping the CPU. When PER_ENB = 0, W_OP_ADRS_STOP signal, W_IF
The _ADRS_STOP signal is output from the OR circuit 78 through the AND circuits 75 and 76, and serves to stop the CPU which is the original function of the address comparison and stop mechanism 2.

In this embodiment, since the existing hardware of the address comparison and stop mechanism 2 is used as it is, the main hardware to be added is to increase the speed of the switching circuit 3 and the bus lines of the STOP_REGs 71 and 72. Burden is small.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, by slightly adding and improving hardware, the address comparison and stop mechanism can be implemented by switching both the original operation and the program event recording operation by a program command. Program event recording function is expanded,
The debugging efficiency of the program is improved.

Further, the designation of the storage area of the address comparison stop mechanism is directly input from the operator console, but this can be performed by a program.

[Brief description of the drawings]

FIG. 1A is a block diagram showing the principle of the present invention,
(B) is a diagram showing a list of input / output signals of the block diagram shown in (a), FIGS. 2A and 2B are block diagrams showing a configuration of an embodiment of the present invention, and FIG. 3 is a diagram showing FIG. FIG. 3 is a detailed view of the switching circuit shown. In the figure, 1... A program event recording mechanism, 2... An address comparison stop mechanism, 3.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 11/28-11/34

Claims (1)

(57) [Claims] An address comparison stop signal output from an address comparison stop mechanism for detecting an event including an instruction fetching event and a recording area change event in a program event recording processing system of an information processing apparatus; A case where a logical sum of an interrupt signal output from the program event recording mechanism (1) for detecting an event including a storage area change event is output, and a case where the address comparison stop signal and the interrupt signal are respectively output A switching means (3) for switching and outputting the output by a program command, and using the output obtained by the logical sum as an interrupt signal.