JP2865551B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit device,
In particular, the present invention relates to a semiconductor integrated circuit device characterized by a clock main line formed on an LSI chip.

[0002]

2. Description of the Related Art In many cases, an external clock signal is input to an LSI in order to determine the operation timing of a sequential circuit in the LSI. Usually, a large number of flip-flops and latches are connected to the clock signal line to which this clock signal is transmitted, and a malfunction occurs if the clock signal timing is shifted (clock skew). Conventionally, in order to prevent this clock skew, a buffer that aligns the timing of clocks supplied to flip-flops and latches is configured in multiple stages and wired, and the design of multiple buffers that drive clock wiring is designed to be equal in load. Clock tree method to add restrictions (NEC Technical Report Vo
l. 45 No. 8/1992) was common.

[0003] However, designing a clock wiring having such a limitation is based on CAD (Computer Aide).
d Design) is still a heavy load in design. In order to solve this problem, there has been proposed a system in which a clock main line is arranged so as to surround a circuit block, and a clock dedicated driver supplies a clock signal to the clock main line (see Japanese Patent Application Laid-Open No. 4-48779). Such a clock main line is formed in an aluminum wiring layer.

A description will be given with reference to FIG. FIG. 6 is a partial sectional view of an aluminum wiring layer of a conventional semiconductor integrated circuit device. The clock trunk line 13 shown in FIG.
4 are formed in the same layer as the first layer aluminum wiring 11 with an interlayer insulating film 16 interposed therebetween. Further, the first layer aluminum wiring 11 is connected to the gate 15 formed on the element isolation oxide film 14 via the contact 17. When the first layer aluminum wiring 11 is wired with, for example, an element (not shown) on the left side of FIG.
Are formed in the same layer as the aluminum wiring 11 of the first layer, the aluminum wiring 11 of the first layer is first wired to the aluminum wiring 12 of the second layer via the contact 17. Next, the aluminum wiring 12 of the second layer and the element on the left side of FIG. 6 are wired, whereby the aluminum wiring 11 of the first layer and the element on the left side of FIG. 6 are wired.

[0005]

As described above, the clock trunk line 13 is formed on the same layer as the first layer aluminum wiring 11. For this reason, the first-layer aluminum wiring 11 needs to be bypassed to avoid the clock trunk line 13 or be connected to the second-layer aluminum wiring 12 via a contact, resulting in a reduction in wiring efficiency. There is.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor integrated circuit device in which wiring efficiency is improved and clock skew is reduced.

[0007]

According to the present invention, there is provided a semiconductor integrated circuit device comprising: (1) a clock trunk line for transmitting a clock signal, which is wired immediately above an element isolation oxide film; It is characterized by comprising a plurality of wiring layers formed above the main line with an insulating film interposed therebetween and connecting the elements.

[0008]

According to the semiconductor integrated circuit device of the present invention, since the clock main line is wired immediately above the element isolation oxide film, the first
There is no pressure on the layer wiring and the second layer wiring due to the miniaturization technology. In addition, since the first layer wiring is formed above the clock main line with an insulating film interposed therebetween, the clock main line is wired in the layer of the first layer wiring as in the prior art. Does not need to be bypassed or wired to the second-layer wiring, and the wiring efficiency of the clock trunk, the first-layer wiring, and the second-layer wiring are both improved, and a clock trunk with reduced clock skew is formed.

[0009]

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a partial sectional view of an aluminum wiring layer of a semiconductor integrated circuit device according to one embodiment of the present invention. Compared with FIG. 6 of the prior art described above, the clock trunk line 13 is wired just above the element isolation oxide film 14. For this reason, even when the aluminum wiring 11 of the first layer is connected to an element (not shown) on the left side of FIG.
There is no need to connect with the aluminum wiring 12 of the layer, and the wiring efficiency is improved.

A clock signal is supplied to the clock trunk line 13 wired in this way. FIG. 2 shows the clock trunk line 13 and the gate 1 of the semiconductor integrated circuit device according to one embodiment of the present invention.
FIG. 5 is a diagram in which wiring is performed by a first-layer aluminum wiring 11. FIG. 2A is an external view of the semiconductor integrated circuit device viewed from above the chip, and FIG. 2B is a partial cross-sectional view taken along line AA ′ of FIG. 2A. ing. The clock main line 13 and the gate 15 are connected to the first layer aluminum wiring 11 via the contact 17.

The clock trunk line 13 is wired in this manner.
Supplies a clock signal to the gate 15. FIG.
FIG. 3 is a layout diagram of clock distribution lines in the semiconductor integrated circuit device according to one embodiment of the present invention. The input / output unit 32 of the semiconductor substrate 31 shown in FIG. 3A is provided with a clock signal input buffer 33. The clock signal A input to the clock signal input buffer 33 is amplified by the clock drivers 34a and 34b and supplied to the clock main line 13. The clock main line 13 is wired in a matrix around each gate array block 35, whereby a clock signal with reduced clock skew is supplied to each gate array block 35.

FIG. 3B is a diagram showing details of the two gate array blocks 35. The two gate array blocks 35 are each wired so as to be surrounded by the clock main line 13, so that the clock signal A is efficiently provided.
Is transmitted to the circuits of the two gate array blocks 35. FIG. 4 is a schematic diagram showing the first half of the manufacturing process of the clock trunk line 13 of the semiconductor integrated circuit device shown in FIG.

FIG. 5 is a schematic diagram showing a manufacturing process of the latter half of the clock trunk line 13 of the semiconductor integrated circuit device shown in FIG. The clock trunk line 13 is formed through the processes of (a) to (d) of FIG. 4 and (a) to (d) of FIG. First, FIG.
As shown in (a), a gate 15 is formed in the diffusion region. FIG. 4A shows the diffusion layer 41 already formed.
Are also shown.

Next, as shown in FIG. 4B, an interlayer insulating film 16 such as BPSG (Boron-Phospho) is formed.
rus-Silicate Glass) CVD
(Chemical Vapor Deposition
Deposit by the method n). Next, as shown in FIG. 4C, etch back is performed for flattening and the interlayer insulating film 1 is formed.
Make 6 uniform.

Next, as shown in FIG. 4D, an aluminum layer 42 is deposited on the interlayer insulating film 16 by sputtering.
Next, as shown in FIG. 5A, a photoresist 43 is applied on the aluminum layer 42 and exposed. Thereafter, the aluminum layer 42 is etched, and the photoresist 43 is removed with an aqueous solution.

As a result, a part of the aluminum layer 42 remains as shown in FIG. 5B, thereby forming the clock main line 13. Next, as shown in FIG.
Further, another interlayer insulating film 16 is deposited on the interlayer insulating film 16 by CVD in order to make the layer 6 thicker, and reflowed. Further, in order to flatten the surface of the interlayer insulating film 16, SOG (Spin), which is also an interlayer insulating film, is used.
(On Glass) film is applied, and then the SOG film is etched back to expose the interlayer insulating film 16.

Thus, the clock trunk line 13 shown in FIG. 5D is formed. Although the manufacturing processes after FIG. 5D are omitted, these manufacturing processes are performed by a known manufacturing process, and a desired semiconductor integrated circuit device is formed.

[0018]

As described above, in the semiconductor integrated circuit device of the present invention, since the first layer wiring is formed above the clock main line with the insulating film interposed therebetween, the clock main line, the first layer wiring, and the first layer wiring are formed. The wiring efficiency of the two-layer wiring is improved, and the clock skew is reduced. For this reason, a semiconductor integrated circuit device whose design is facilitated and whose speed is increased is provided.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of an aluminum wiring layer of a semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 2 is a diagram of a semiconductor integrated circuit device according to one embodiment of the present invention in which a clock main line and a gate oxide film are wired by a first-layer aluminum wiring.

FIG. 3 is a layout diagram of clock distribution lines in the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 4 is a schematic diagram showing a first half of a manufacturing process of a clock main line of the semiconductor integrated circuit device shown in FIG. 1;

FIG. 5 is a schematic view showing a manufacturing process of the latter half of the clock trunk line of the semiconductor integrated circuit device shown in FIG. 1;

FIG. 6 is a sectional view of an aluminum wiring layer of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 First layer aluminum wiring 12 Second layer aluminum wiring 13 Clock trunk line 14 Element isolation oxide film 15 Gate 16 Interlayer insulating film 17 Contact 31 Semiconductor substrate 32 Input / output unit 33 Clock signal input buffers 34a, 34b Clock driver 35 Gate Array block 41 Diffusion layer 42 Aluminum layer 43 Photoresist

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/82 H01L 21/76 H01L 21/822 H01L 27/04

Claims (1)

(57) [Claims] 1. A wiring lined immediately above an element isolation oxide film,
A semiconductor integrated circuit device comprising: a clock main line for transmitting a clock signal; and a plurality of wiring layers formed on the clock main line with an insulating film interposed therebetween and connecting elements.