JP2864558B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device having a trench structure such as a trench isolation.

(Prior Art) As a conventional method for manufacturing a semiconductor device having a groove structure in a semiconductor substrate, there is a method as shown in FIG. 5, for example.

First, a thick oxide film 22, for example, is formed as a material for an etching mask on the surface of a Si semiconductor substrate 21 by thermal oxidation (FIG. 1A). The oxide film 22 is patterned using a photolithography technique, and an opening 23 is formed at a position where a vertical groove is to be formed (FIG. 2B). Vertical grooves 24 are formed in the semiconductor substrate 21 using anisotropic etching such as RIE, which has strong anisotropy in the vertical direction with respect to the surface of the semiconductor substrate 21 (FIG. 3C). If a trench capacitor is used,
The inner wall of the vertical groove 24 is oxidized.

A deposit 25 such as polycrystalline silicon or SiO ₂ is deposited inside the vertical groove 24 and on the surface of the semiconductor substrate 21 by using a CVD method or the like (FIG. 4D). In this step, the inside of the vertical groove 24 is filled with the deposit 25. Next, a resist film 26 for etch back is applied to the entire surface (FIG. 9E). The entire surface is etched back by using an etching method such as RIE, and the surface of the semiconductor substrate 21 is planarized (FIG. 1F).

As described above, it is possible to completely embed the deposit 25 in the vertical groove 24 in which the width of the opening is substantially the same as or wider than the internal width by using the CVD method or the like.

By the way, recently, a technology has been developed to form a groove in the semiconductor substrate whose inner width is larger than the width of the opening, and to bury a deposit such as SiO ₂ in this groove to realize isolation or the like. Is coming.

FIG. 6 shows that a groove 27 having a rhombic cross section whose inner width is larger than the width of such an opening 27a is formed by SiO.
₂ shows a trench structure in which a deposit 25 such as ₂ is buried. In such a groove 27, the deposit 25 follows the inner surface of the groove 27 and the surface of the semiconductor substrate 21 with the same thickness at the time of deposition by the CVD method or the like. A cavity 28 is formed inside 27.

(Problems to be Solved by the Invention) When manufacturing a semiconductor device having a groove structure in which a deposit is embedded in a groove having an inner width larger than the width of an opening, a conventional method uses Deposit cavities are created.
For this reason, stress remains in the semiconductor substrate, and contaminants may accumulate inside the cavity, and thus there is a problem that the reliability of the semiconductor device may be reduced.

Therefore, the present invention provides a method for manufacturing a semiconductor device, which can completely bury a deposit in a groove having an inner width larger than the width of an opening, thereby improving the reliability of the semiconductor device. The purpose is to do.

[Constitution of the Invention] (Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a first method of forming a first groove having an inner width larger than the width of an opening in a semiconductor substrate. And a second step of depositing a first deposit on the inside of the first groove and on the surface of the semiconductor substrate to a substantially uniform thickness so as to cover an opening of the first groove. A third step of introducing an impurity into the first deposit deposited in the opening of the first groove, and at least a region into which the impurity has been introduced in the third step is formed with respect to the surface of the semiconductor substrate. A fourth step of forming a second groove by etching with anisotropic etching having anisotropy in the vertical direction, and depositing a second deposit on the second groove and the surface of the semiconductor substrate And a fifth step of performing the above.

(Operation) When depositing the first deposit in the second step, the first groove has a larger width inside the first groove than in the opening. Cavities are created. The formation of the second groove reaching the cavity by the fourth step and the deposition of the second deposit by the fifth step are performed. When the degree of spread of the second groove is large, the third step and the fourth step are repeated a required number of times, so that the inside of the second groove is completely filled with the second deposit. Be included.

Further, by introducing impurities into the first deposit in the third step, the etching rate of the first groove opening in the fourth step becomes higher than the etching rate of the other parts other than the first groove opening. Groove formation is performed at high speed. In addition, a region into which impurities are not introduced is less likely to be over-etched, and precise management of an etching time and a precise etching apparatus are not required.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 and FIG. 2 are views for explaining a first embodiment of the present invention.

The manufacturing method of the semiconductor device according to this embodiment will be described with reference to these drawings. In the following description,
The item symbols of (a) to (i) are shown in FIG.
(I).

(A) A thick oxide film 2 is formed as a material for an etching mask on the surface of a Si semiconductor substrate 1 by thermal oxidation. Next, the oxide film 2 is patterned using a photolithography technique, and an opening 3 is formed at a position where a groove is to be formed.

(B) A vertical groove 4 is formed in the semiconductor substrate 1 by using anisotropic etching such as RIE, which has strong anisotropy in a direction perpendicular to the surface of the semiconductor substrate 1.

(C) The inner surface of the vertical groove 4 is subjected to isotropic etching or anisotropic etching using an alkaline anisotropic etching solution. The example in the figure is a case where anisotropic etching is performed,
For example, if the surface of the Si semiconductor substrate 1 is the (100) plane, the anisotropic etching significantly lowers the etch rate on the (111) plane. A groove 5 having a rhombic shape and an inner width larger than the width of the opening 5a is formed. Here, if necessary, the inner wall of the groove 5 is oxidized.

(D) The inside of the groove 5 and the semiconductor substrate 1 using a CVD method or the like.
A deposit 6 made of polycrystalline silicon is deposited to a substantially uniform thickness on the surface of the groove 5, and the opening 5a of the groove 5 is closed. As the material of the deposit 6, instead of polycrystalline silicon, depending on the use of the groove structure,
SiO ₂ , PSG or BPSG is used. In this deposition step, since the inside of the groove 5 is widened, a cavity 8 of the deposit 6 is formed therein.

(E) The deposit 6 is etched using anisotropic etching with strong vertical anisotropy such as RIE. At this time, anisotropic etching is used in which the deposit 6 has a higher etching rate than the oxide film 2 serving as an etching mask material.

(F) The anisotropic etching of the deposit 6 is further advanced, and an etching hole 9 reaching the cavity 8 is formed in the groove 5. The inside of the etching hole 9 is narrower than the opening.

(G) A deposit 7 of the same material as that used in the step (d) is deposited to a substantially uniform thickness on the etching hole 9 and the surface of the semiconductor substrate 1 by a CVD method or the like. Embed

(H) A resist film 11 for etching back is applied to the entire surface.

(I) The entire surface is etched back using an etching method such as RIE, and the surface of the semiconductor substrate 1 is planarized.

As described above, according to the method of this embodiment, compared with the conventional method, the steps (e) and (f) of digging the etching hole 9 by anisotropic etching and the second deposition by the CVD method or the like And (g) depositing 7
The deposits 6 and 7 can be completely buried in the groove 5 whose inner width is larger than the width of the opening 5a.

Here, the steps (e) and (f) of digging the etching hole 9 and the step (g) of depositing the second deposit 7 are added only once, so that the deposit 6 7 can be completely embedded as shown in FIG.
This is a case where the size B / 2, which is half the width B of the opening 5a, is larger than the horizontal distance A between the point 5b having the largest width inside the groove 5 and the edge of the opening 5a. For a groove having a horizontal distance A larger than B / 2, a step (e) of digging an etching hole 9;
By repeating (f) and the second deposition step (g) of the deposit 7 a required number of times, the inside of the groove can be completely filled with the deposit.

 Next, FIG. 3 shows a second embodiment of the present invention.

In this embodiment, the deposit in the first deposit depositing step corresponding to FIG. 1D is non-doped polycrystalline silicon 12, and after this depositing step, the surface of the non-doped polycrystalline silicon 12 is removed. , Doped polycrystalline silicon 12a by doping and diffusion of impurities such as phosphorus or arsenic. When such a treatment is added, the doped polycrystalline silicon 12a has an increased etching rate,
Step of digging an etching hole 9 ((e) of FIG. 1)
(F)), the deposit on the upper portion of the cavity 8 can be efficiently etched.

During the etching, when the upper portion of the cavity 8 is opened, the etching of the deposit under the cavity 8 starts.
Since the etching rate of the deposit below the cavity 8 is lower than that of the upper side, the etching hole 9 can be dug without significantly changing the shape of the deposit below the cavity 8. Therefore, it is much easier to completely bury the inside of the groove 5 with the deposit.

Further, when the non-doped polycrystalline silicon 12 is doped with an impurity, the impurity is introduced only into the region of the opening 5a by the ion implantation method without using the diffusion method as described above. Is more effective.

FIG. 4 shows a third embodiment of the present invention. This embodiment shows a case where a deposit is buried in a groove having an equal width on the upper side and a wider width on the lower side.

In FIG. 4, the same or equivalent members as those in FIG. 1 are denoted by the same reference numerals as those described above, and duplicate description will be omitted.

A vertical groove is formed by anisotropic etching using a mask on which the oxide film 2 is patterned. Then, the side wall of the vertical groove is masked with an oxide film or the like, and only the bottom of the vertical groove is isotropically etched to form a groove 13 having an equal width on the upper side and a wider lower part (FIG. 4). (A)).

Thereafter, a first deposit 6 deposition step (FIG. 8B), an etching hole 9 forming step by anisotropic etching (FIGS. 9C and 9D), and a second deposition 7 After the deposition step (FIG. 9E) and the step of flattening the surface of the semiconductor substrate 1 by etching (FIG. 9F), the deposit 6 is formed in the groove 13 whose inner width is wider than the width of the opening. , 7 are completely embedded.

If necessary, the step of forming the etching hole 9 and the step of depositing the second deposit are repeated a plurality of times.
This is the same as in the first embodiment.

[Effects of the Invention] As described above, according to the present invention, deposits are deposited to a substantially uniform thickness on the inside of the width where the inner width is larger than the width of the opening and on the surface of the semiconductor substrate. Etching the deposit deposited in the first step by a first step of closing the opening of the groove and anisotropic etching having anisotropy in a direction perpendicular to the surface of the semiconductor substrate; A second step of digging an etching hole reaching a cavity formed inside the groove;
And a third step of depositing a deposit on the etching hole and the surface of the semiconductor substrate to bury the etching hole, and removing the deposit on the surface of the semiconductor substrate to remove the deposit on the surface of the semiconductor substrate. And the fourth step of flattening the portion allows the deposit to be completely buried in the groove having an inner width larger than the width of the opening, so that stress does not remain on the semiconductor substrate, and the like. There is an advantage that the reliability of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a process diagram for explaining a first embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIG. 2 is a process of digging an etching hole and depositing a second deposit in the first embodiment. And FIG. 3 is a diagram for explaining a groove dimension in which a deposit can be completely buried in the inside of the groove by performing the steps only once. FIG. 3 is a diagram for explaining a second embodiment of the present invention. FIG. 4 is a process chart for explaining a third embodiment of the present invention, FIG. 5 is a process chart for explaining a conventional method of manufacturing a semiconductor device, and FIG. 6 is a diagram for explaining another conventional example. FIG. 1: semiconductor substrate, 5, 13: groove, 5a: opening, 6, 7, 12: deposit, 8: cavity, 9: etching hole.

Claims (1)

(57) [Claims] A first step of forming a first groove having an inner width larger than a width of an opening in a semiconductor substrate; and a first deposition step inside the first groove and a surface of the semiconductor substrate. A second step of depositing an object with a substantially uniform thickness so as to cover the opening of the first groove; and introducing an impurity into the first deposit deposited in the opening of the first groove. A third step of performing anisotropic etching having anisotropy in a direction perpendicular to the surface of the semiconductor substrate at least in a region into which impurities are introduced in the third step.
A method of forming a groove, and a fifth step of depositing a second deposit on the surface of the second groove and the surface of the semiconductor substrate.