JP2864023B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device used in a computer or the like.

[Summary of the Invention]

The present invention relates to a method of manufacturing a semiconductor device having a dual gate structure in which at least two gate electrodes are electrically connected in series. Different regions are formed, and the thin film is etched back so that regions having different concentrations are partially left so that the gate length of each of the dual gate electrodes is accurately processed.

[Conventional technology]

Conventionally, as shown in FIG. 2, a field effect MOS (Metal-Oxide-Semicon) in which two or more gate electrodes are electrically connected.
ductor) The method of manufacturing the transistor is based on the p-type semiconductor substrate 1
After processing the floating gate electrode 13 and the control gate electrode 14 through the gate insulating film 12 using the same mask, the select gate electrode is processed using another mask through the select gate insulating film 17, Select gate electrode 18 and floating gate electrode
There is known a manufacturing method in which an N ^{+ -type} source region 19 and a drain region 11 are formed in self-alignment with each other.

[Problems to be solved by the invention]

However, the conventional method of manufacturing a semiconductor device has a drawback that when the transistor is reduced in size, the variation increases because the floating gate electrode 13 and the select gate electrode 18 are not processed in a self-aligned manner.

Therefore, the present invention solves such a conventional drawback by manufacturing a semiconductor device suitable for miniaturization and high integration in which the variation in transistors does not increase even if the select gate electrode 18 and the floating gate electrode 13 are reduced. The way is aimed.

[Means for solving the problem]

In order to solve the above-mentioned problems, the present invention forms a thin film for a select gate electrode after processing a floating gate electrode, and forms a region having a partially different concentration by a shadow effect by doping impurities by oblique ion implantation. Further, the floating gate electrode and the select gate electrode can be processed in a self-aligned manner by etching back by isotropic etching to leave a region having a partially different concentration as a select gate electrode.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 (a) to 1 (e) are cross-sectional views of a semiconductor in respective steps showing a method for manufacturing a semiconductor device according to the present invention. N type
The case of a MOS transistor will be described.

As shown in FIG. 1A, a thin film 2 for a gate insulating film as a first insulating film, a thin film 3 for a floating gate electrode as a first thin film for a gate electrode, and a second insulating film on the surface of a P-type silicon substrate 1. A thin film 4 for a control gate insulating film as a film and a thin film 5 for a control gate electrode as a second thin film for a gate electrode are sequentially formed, and a floating gate electrode 3A as a first gate electrode is further formed.
And a resist (photosensitive film) pattern 6 as a mask for processing the control gate electrode 5A as a second gate electrode.
Is patterned by photolithography.
For example, as the thin film 2 for a gate insulating film, about 100 to 200 Å
As the silicon oxide film and the thin film 3 for the floating gate electrode,
The thin film 4 for the N ⁺ type polycrystalline silicon film of about 2000 to 3000 mm and the control gate insulating film includes a silicon oxide film of about 100 mm and about 1 mm.
As a composite insulating film of a silicon nitride film of 50 mm and a silicon oxide film of approximately 30 mm, and a thin film 5 for a control gate electrode, about 3000
Forming a Å of N ⁺ -type polycrystalline silicon film. Here, a silicon oxide film may be used as the control gate insulating film thin film 4, and a metal such as tungsten or a silicide film such as tungsten silicide may be used as the control gate electrode thin film 5. Next, as shown in FIG. 1B, anisotropic etching is performed using the resist pattern 6 as a mask to form a floating gate electrode 3A as a first gate electrode and a control gate electrode as a second gate electrode.
Leave 5A. Next, as shown in FIG. 1C, a select gate electrode thin film 8 is formed as a third gate electrode thin film, and oblique ion implantation of arsenic is performed. Since phosphorus has a large diffusion coefficient, it is difficult to form a concentration distribution. Since arsenic has a small diffusion coefficient, it easily forms a concentration distribution. As shown in FIG. 1 (c), by processing the floating gate electrode 3A and the control gate electrode 5A, a step corresponding to both film thicknesses (about the height of the floating gate electrode 3A).
2000 to 3000 mm and control gate electrode 5A approx.
00 °). Ion implantation or thermal diffusion is performed so that the ion-implanted arsenic is doped to the bottom of the select gate electrode thin film 8. When ions are implanted into the substrate 1 at an implantation angle θ, the ion implantation has a directional property, and the length approximated by the following equation to one side wall of the floating gate electrode 3A and the control gate electrode 5A due to the shadow effect. low concentration region of arsenic L ₁ is formed.

L ₁ step _{× tanθ + t s ... (1} ) where, t _s is the thickness of the select gate electrode film 8.
The select gate electrode thin film 8 may be a polycrystalline silicon film or a metal.

For example, t _s = 3000Å, step = 6000 Å, When θ = 7 °, the low impurity region 8B of arsenic L ₁ 3500 Å is formed.
Therefore, when the select gate electrode thin film 8 is a polycrystalline silicon film, the arsenic low concentration region 8B has an extremely low etching rate with respect to the arsenic-doped region.
As shown in FIG. 1D, the low concentration region 8B can be selectively left by the etching process. Etching is preferably performed with small anisotropy. This is because unnecessary areas are not left on other steps. Therefore, the selection gate electrode 8A as the third selection gate electrode can be processed in a self-aligned manner with respect to the floating gate electrode 3A. The same processing can be performed by using a P ⁺ type polycrystalline silicon film as the select gate electrode thin film 8 before arsenic doping. Further, the length of the select gate electrode 7A can be controlled according to the equation (1).

Next, as shown in FIG. 1 (e), the selection gate electrode 8A
By doping the floating gate electrode 3A with an N-type impurity on the substrate surface, the N-type source region 9 and the drain region 10 can be formed. As in FIG. 1 (e), the floating gate electrode type semiconductor non-volatile memory and a channel length L ₂ which is controlled by the channel length L ₁ and the floating gate electrode 3A are electrically connected to be controlled by the selection gate electrode 8A Can be formed. According to the manufacturing method of the semiconductor device of the present invention, it can be accurately processed channel length L ₁ and the channel length L ₂ that affect the characteristics of the semiconductor device. Therefore, a semiconductor device which is suitable for high integration obtained by reducing the channel length L ₁ and L ₂ can be achieved. The method of manufacturing a semiconductor device of the present invention shown in FIG. 1 (a) ~ (e), to the channel length L _1, and the floating gate electrode 3A with a larger long easy step of channel length L ₁ Although a semiconductor nonvolatile memory having a dual structure with the control gate electrode 5A has been described as an example, the present invention can also be applied to a general dual gate semiconductor device. FIG. 3 is a cross-sectional view of a general dual-gate MOS transistor using another method of manufacturing a semiconductor device according to the present invention. Unlike the semiconductor nonvolatile memory of FIG.
Since the step becomes smaller as much as the gate electrode 23,
The remainder of the select gate electrode 18 becomes smaller. Each area is the first
It is the same as FIG. This is a structure without the control gate electrode 5A. However, when the step is small, from equation (1),
By increasing θ, the length of the select gate electrode 18 can be increased. Next, a transistor having an asymmetric impurity region can be formed by using the advantage that a sidewall can be formed only on one side according to the present invention. Fig. 4 (a)-
This will be described with reference to FIG. As shown in FIG.
After patterning the gate electrode 123 serving as the first gate electrode via the gate insulating film 112A serving as the first insulating film, the N ⁻ region 121 is formed by doping with an N-type impurity. next,
As shown in FIG. 4B, the insulating film 117 as the second insulating film
A polycrystalline thin film 118 is formed as a second gate electrode thin film to be the select gate electrode 118A (second gate electrode) shown in FIG. The region 118B is formed. Next, the polycrystalline silicon film 118 is isotropically etched to form a structure as shown in FIG.
Next, the low concentration polycrystalline silicon region 118A and the gate electrode 12
N ^{+ is} added to the surface of the P-type silicon
A source region 110 and a drain region 119 are formed. Since the N ^- region 121 can be formed in a self-aligned manner under the low-concentration crystalline silicon region 118A that is the second gate electrode of arsenic and the selection gate electrode, as shown in FIG. An asymmetrical MOS transistor including an N ⁺ type source region 110, an N ⁻ type drain region 121, and a gate electrode 123 is formed. By forming only the drain region to be N ^- type, high reliability which prevents generation of hot electrons
MOS transistors can be formed.

FIG. 5 shows a floating gate electrode 3A in another semiconductor device structure.
And the control gate electrode 5A are overlapped to increase the level difference,
Further, in this example, a P-type impurity region 221 having a concentration higher than that of the substrate 1 is formed in a self-aligned manner under the select gate electrode 8A in order to easily generate hot electrons. This is a structure in which an impurity region 221 is added to the semiconductor device of FIG. By using the manufacturing method of the present invention, a semiconductor device with less variation in characteristics can be easily manufactured. In the description of the present invention, arsenic with a small diffusion coefficient was used as the ion-implanted particles. It can also be implemented.

〔The invention's effect〕

As described above, the present invention relates to a method of manufacturing a semiconductor device having a dual-gate structure, in which arsenic is obliquely ion-implanted into one gate electrode having a step to partially form an arsenic low-impurity region. By selectively leaving the low-impurity region by etching back of the etching process with small anisotropy, there is an effect of enabling a dual-gate MOS transistor with small variation and suitable for high integration.

[Brief description of the drawings]

1 (a) to 1 (e) are cross-sectional views in the order of steps of a method of manufacturing a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view of a semiconductor device formed by a conventional method of manufacturing a semiconductor device, and FIG. FIG. 4A is a cross-sectional view of a semiconductor device using another method of manufacturing a semiconductor device of the present invention, and FIGS. 4A to 4D are cross-sectional views in the order of steps of another method of manufacturing a semiconductor device of the present invention; FIG. 5 is a sectional view of a final step of a semiconductor device according to still another method of manufacturing a semiconductor device according to the present invention. 1 ...... P-type silicon substrate 2A ...... gate insulating film 3A ...... floating gate electrode 5A ...... control gate electrode 8A ...... selection gate electrode 9 ...... N ⁺ -type source region 10 ...... N ⁺ -type drain region

Claims (8)

(57) [Claims] A step of patterning a first gate electrode thin film formed on a surface portion of a first conductivity type semiconductor substrate via a first insulating film to form a first gate electrode;
Forming a second insulating film on the patterned first gate electrode; forming a second gate electrode thin film on the second insulating film; and forming the second gate electrode on the second insulating film. Oblique ion implantation of an impurity element into a thin film for use;
Patterning the second gate electrode thin film as a side wall on one side wall of the first gate electrode thin film by selectively etching the second gate electrode thin film depending on the impurity concentration. Production method. 2. The method according to claim 1, wherein said selective etching is isotropic etching. 3. The method according to claim 1, wherein said second gate electrode thin film is a polycrystalline silicon film. 4. The method according to claim 1, wherein the impurity element is a criterion. 5. A step of sequentially forming a first insulating film, a first thin film for a gate electrode, a second insulating film, and a second thin film for a gate electrode on a surface portion of a semiconductor substrate of a first conductivity type; A step of patterning the first gate electrode thin film, the second insulating film and the second gate electrode thin film by anisotropic etching, and patterning the first gate electrode thin film and the second Forming a third insulating film on the insulating film and the second gate electrode thin film; forming a third gate electrode thin film on the third insulating film; Obliquely ion-implanting an impurity element into the thin film for the gate electrode, and selectively etching the third thin film for the gate electrode depending on the impurity concentration to form the first thin film for the gate electrode on one side wall of the first thin film for the gate electrode. Three thin films for the gate electrode The method of manufacturing a semiconductor device comprising a step of patterning a Lumpur. 6. The method according to claim 5, wherein said selective etching is isotropic etching. 7. The method according to claim 5, wherein the third gate electrode thin film is a polycrystalline silicon film. 8. The method according to claim 5, wherein said impurity element is arsenic.