JP2863239B2 - Simulation method for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for simulating a semiconductor integrated circuit, and more particularly, to a simulation method when circuit data used in a simulation at a transistor level includes partial circuit data having a hierarchical structure. By multiplying a magnification variable of an arbitrary value for each partial circuit, it is possible to obtain the same electrical characteristics as those obtained when the partial circuits are connected in parallel, and to increase the efficiency of the simulation. The purpose of the present invention is to provide a method of simulating a semiconductor integrated circuit capable of forming a hierarchical circuit by defining a basic circuit composed of basic elements such as a resistive element, a capacitive element, a transistor element or a partial circuit by a plurality of basic circuits. When performing a simulation of an integrated semiconductor integrated circuit, the The same magnification variable portion is defined for the element constants of the constituent basic elements, and the magnification variable of an arbitrary value is multiplied for each partial circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simulating a semiconductor integrated circuit, and more particularly, to a method for simulating a case where circuit data used in a simulation at a transistor level includes partial circuit data having a hierarchical structure. It is about.

In recent years, as the degree of integration of semiconductor integrated circuits (ICs) has increased, circuit data input to a simulator has been increasing. For this reason, it is necessary to process the circuit data using the hierarchical definition in the simulation of the IC circuit.

[Prior art] Conventionally, to simulate an IC, a basic circuit such as a NAND (Negative AND) circuit and a NOR (Negative OR) circuit in the circuit data or a circuit obtained by collecting a plurality of these circuits is a partial circuit. , The circuit data is hierarchized, and a simulation is performed by appropriately incorporating these partial circuits into a main circuit.

That is, for example, when the semiconductor integrated circuit 5 is composed of the partial circuits 1 to 4 as shown in FIG.
Different magnification variables are defined for the element constants of the respective basic elements constituting the elements Nos. 1 to 4. When the simulation result does not become a preset result, the characteristics and conditions of the partial circuits 1 to 4 are changed by changing each magnification variable.

As a method of changing the characteristics and conditions of each of the partial circuits 1 to 4, the same partial circuits 1 may be connected in parallel as shown in FIG. 5, for example.

[Problems to be Solved by the Invention] However, when different magnification variables are defined for all the basic elements constituting each of the partial circuits 1 to 4, it takes time to manage and change the magnification variables. There was a problem. Further, when the same partial circuits 1 are connected in parallel, a call statement is required for each of the partial circuits 1, and there is a problem that the number of call statements increases.

The present invention has been made in order to solve the above-described problems, and an object of the present invention is to multiply a magnification variable having an arbitrary value for each partial circuit to obtain an electrical characteristic when the partial circuits are connected in parallel. It is an object of the present invention to provide a method for simulating a semiconductor integrated circuit, which can obtain similar electric characteristics and can increase the efficiency of a simulation.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method in which a basic circuit composed of basic elements such as a resistive element, a capacitive element, and a transistor element or a partial circuit is defined by a plurality of basic circuits. When performing a simulation of a semiconductor integrated circuit in which circuit data is hierarchized, the same magnification variable portion is defined for each elementary element of each basic element constituting the partial circuit, and an arbitrary value is defined for each partial circuit. Multiply by the magnification variable.

[Operation] Therefore, by multiplying a magnification variable of an arbitrary value for each partial circuit, the element constants of all the basic elements constituting the partial circuit are changed, and the electrical characteristics when the partial circuits are connected in parallel are changed. Similar electrical characteristics are obtained, and the efficiency of the simulation of the semiconductor integrated circuit is improved.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the simulation apparatus 10 includes a magnification setting unit 11 and a simulator unit 12. The magnification setting section 11 receives the partial circuit data 13 for each of the partial circuits 1 to 4 shown in FIG. 4, and receives the magnification variable P for each of the partial circuits 1 to 4.

FIG. 3 shows an example of the partial circuit data 13.
Are resistance elements R1, R2, ... as basic elements, and capacitance elements
.., Transistor elements T1, T2,..., Current source elements, diode elements, and the like. Each of the resistance values of the resistance elements R1, R2, ..., the respective capacitance values of the capacitance elements C1, C2, ..., the transistor elements T1, T2, ...
..The same magnification variable P1 is defined in the data such as the channel width, channel area, and overlap area with the gate, and the resistance value of each resistance element R1, R2,... Is divided by the magnification variable P1. The capacitance value of each of the capacitance elements C1, C2,. Have been.

That is, the partial circuit corresponding to the partial circuit data 13 is P1
, The resistance of each of the resistance elements R1, R2,... Becomes 1 / P1, the capacitance of each of the capacitance elements C1, C2,. The channel width of T2,..., The channel area, and the overlap area with the gate are P1 times.

Then, as shown in FIG. 2, the magnification setting unit 11 sets a magnification variable P for each partial circuit data based on the input partial circuit data 13 and the magnification variable P, and then sets each current source for each partial circuit data. The data of the element, each transistor element, each capacitance element, each resistance element, and each diode element are multiplied by the input magnification, and the result is output to the simulator unit 12 at the next stage. For each current source element, the magnification variable P is multiplied by the bias current value or the voltage value and the amplitude value, and for each transistor element, the channel width, the channel area, and the overlapping area with the gate are multiplied by the magnification variable P. For each capacitance element, the capacitance value and the junction area are multiplied by the magnification variable P. For each resistance element, the resistance value is divided by the magnification variable P, for the diode element, the resistance value is divided by the magnification variable P, and the reverse saturation current value is multiplied by the magnification variable P. I have.

The simulator unit 12 at the next stage is based on each partial circuit data output after the magnification setting process by the magnification setting unit 11,
Each of the partial circuits 1 to 4 is simulated for a predetermined time, and the execution result 14 is output.

As described above, in the present embodiment, the same magnification variable portion P is defined for each of the partial circuits 1 to 4 with respect to the element constants of the resistive element, the capacitive element, the transistor element, the current source element, and the diode element constituting the partial circuit. Since the value of the magnification variable P to be multiplied with respect to the partial circuit is set to an arbitrary value, when different magnification variables are defined for all the basic elements constituting the partial circuit as in the related art, Took time to manage and change the magnification variables, but it was possible to easily change the element constants of all the basic elements constituting the partial circuit, and to obtain the same electrical characteristics as when the partial circuits were connected in parallel. Characteristic can be obtained, and the simulation of the semiconductor integrated circuit can be made more efficient. Also, unlike the conventional case where the same partial circuits are connected in parallel, the number of call statements does not increase.

[Effects of the Invention] As described above in detail, according to the present invention, by multiplying a magnification variable having an arbitrary value for each partial circuit, the same electrical characteristics as those obtained when the partial circuits are connected in parallel are obtained. There is an excellent effect that characteristics can be obtained and simulation can be performed with high efficiency.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a simulation apparatus for implementing the present invention, FIG. 2 is a flowchart showing a magnification setting process in one embodiment, FIG. 3 is a diagram showing an example of partial circuit data, and FIG. FIG. 5 is a diagram illustrating an example of a circuit, and FIG. 5 is a diagram illustrating an example of a conventional simulation method. In the figure, 1 to 4 are partial circuits, 5 is a semiconductor integrated circuit, C1, C2,... Are capacitive elements, P and P1 are magnification variables, R1, R2,. .. Denotes a transistor element.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50

Claims (1)

(57) [Claims] A simulation of a semiconductor integrated circuit in which circuit data is hierarchized by defining a basic circuit composed of basic elements such as a resistance element, a capacitance element, a transistor element, or a partial circuit by a plurality of basic circuits. A semiconductor, wherein the same magnification variable portion is defined for each elementary factor of each elementary element constituting the partial circuit for each partial circuit, and a magnification variable having an arbitrary value is multiplied for each partial circuit. Simulation method for integrated circuits.