JP3054109B2 - Logic circuit delay calculation method, delay calculation apparatus thereof, and delay data calculation method of delay library - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay calculation method for calculating a delay time of a logic circuit with high accuracy, a delay calculation device, and a delay data calculation method for a delay library.

[0002]

2. Description of the Related Art As for the power supply voltage inside an integrated circuit, the voltage value of the power supply voltage applied to an external power supply terminal may be different from the voltage value of the power supply voltage applied to an internal circuit. One is to intentionally set different voltage values to improve the characteristics of the integrated circuit, and the other is to be caused by a parasitic element resulting from an increase in the speed of the integrated circuit and miniaturization of the manufacturing process.

[0003] Each case will be described below.

(First Conventional Example) In order to reduce the power consumption of an integrated circuit or increase the circuit speed, a power supply voltage applied to an internal circuit block may be selectively set.
For example, a voltage lower than the voltage applied to the power supply terminal is set in a circuit block requiring low power consumption, and the same power supply voltage as an external power supply voltage is set in a circuit block requiring high speed.

In designing an integrated circuit as described above, in order to verify delay and operation of signal propagation of the integrated circuit, a gate-level delay library is created for each power supply voltage, and a desired delay is determined. You need to select and use a library.

(Second Conventional Example) A power supply line (hereinafter abbreviated as a VDD line) for supplying a power supply potential to a circuit block of an integrated circuit, and a ground line (hereinafter abbreviated as VDD) for supplying a ground potential.
Abbreviated as VSS line. ), Current consumption flows, and a voltage fluctuation occurs due to a wiring parasitic element formed of a resistance (R), a capacitance (C), or an inductance (L) appearing on the VDD line and the VSS line. For example, for simplicity, the wiring parasitic element of the power supply wiring is only a resistor. The power supply voltage effectively applied to the circuit block becomes smaller due to the voltage fluctuation caused by the wiring resistance, so that the delay time increases. However, in the conventional delay calculation method, since an ideal VDD line and a VSS line in which the applied power supply voltage does not change are premised, a problem that an error between the obtained analysis result and the actual measurement result becomes large. Have.

As a method for solving this, there is a simulation method disclosed in, for example, Japanese Patent Application Laid-Open No. 6-124318. According to the simulation method, the data extraction unit,
The process parameter storage unit and the power supply voltage storage unit calculate the resistance of the power supply wiring, and the gain coefficient calculation unit and the drain current calculation unit use the MOSFE as a gate element.
The drain current of T is calculated. After calculating the voltage drop amount of the power supply line using the resistance of the power supply wiring and the drain current, the propagation delay calculation unit calculates the delay time from the gain coefficient β of the drain current and the associated capacitance.

[0008]

[Problems to be solved by the invention]

(First Conventional Example) As described in the first conventional example, the delay data extraction processing for obtaining desired delay data from a cell library is based on the assumption that the power supply voltage is set to a predetermined value. Since it is necessary to extract the delay data by the number of times of the set values of the different power supply voltages, the extraction time is long in the case of a multi-input gate such as a multi-bit addition cell. Has the problem that it becomes longer. Further, it has not been possible to cope with finding an optimum solution of the power supply voltage for optimizing both the power consumption by the power supply voltage and the delay time in consideration of the delay time.

(Second Conventional Example) In Japanese Patent Application Laid-Open No. 6-124318 shown in the second conventional example, a gain coefficient in a propagation delay calculating section, which is an important point in calculation of power supply voltage dependence of delay time, is described. There is a problem that the relationship between β and the delay time is not disclosed, and a specific calculation method of the delay time is not disclosed.

As a method of analyzing the delay time from the power supply voltage dependence of the gain coefficient β, a MOSF is analyzed by a circuit simulation at a transistor level or a switch level.
There is a method of obtaining a time for charging or discharging a load capacitance or a load resistance based on the voltage dependence of the drain current of the ET. However, this method has a problem that it is not practical because the number of circuit elements increases because a netlist expanded at the transistor level is used as a target of circuit simulation, and the analysis time is too long for a large-scale circuit. I have.

As a method of calculating the power supply voltage dependency of the delay time, there is a method of multiplying the power supply voltage dependency coefficient of the delay time calculated in advance by the delay time. A method is conceivable in which a plurality of effective power supply voltages are obtained by subtracting the potential corresponding to the power supply voltage fluctuation amount of the VDD line and the VSS line for each operating condition, and the delay values extracted for each of the power supply voltages are used. . However, these methods require an effective power supply voltage to be determined in advance, and in practice, such as a plurality of circuit blocks connected to wiring of different power supply voltages or a circuit block operating at a different frequency or a different frequency. However, there is a problem that it is not possible to accurately analyze the influence of the voltage fluctuation of the different power supply lines generated for each circuit block in the integrated circuit.

Further, as shown in the first conventional example, in the case of an integrated circuit including a plurality of circuit blocks operating at different power supply voltages, a method of uniformly multiplying the power supply voltage dependency coefficient of the delay time by the entire integrated circuit is used. Cannot be calculated.

An object of the present invention is to solve the above-mentioned conventional problems at once, and to make it possible to easily and analytically calculate the power supply voltage dependence of the delay time of a logic circuit so that the delay time can be reliably obtained. With the goal.

[0014]

In order to achieve the above-mentioned object, the present invention provides a method for controlling a delay time of a logic circuit to which a first power supply voltage is applied, by adding a ratio of the second power supply voltage to the first power supply voltage. Power supply voltage coefficient, which is the value of
Multiplied by the current coefficient which is the value of the ratio of the drain saturation current of the FET when the power supply voltage of
Of the logic circuit to which the power supply voltage is applied.

According to a first logic circuit delay calculation method according to the present invention, when a logic circuit including a plurality of logic elements including FETs is simulated, a delay in signal propagation time due to a power supply voltage of the logic circuit is calculated. A delay calculation method for a logic circuit, wherein a value of a ratio of a second power supply voltage to a first power supply voltage is used as a power supply voltage coefficient, and a first value with respect to a drain saturation current of the FET when the second power supply voltage is applied. The value of the ratio of the drain saturation current of the FET when the first power supply voltage is applied is defined as a current coefficient, and the first delay time and the power supply voltage coefficient which are delay times of the logic circuit when the first power supply voltage is applied. Is calculated by multiplying the product of
Is the delay time of the logic circuit when the power supply voltage is applied.

In the second logic circuit delay calculation method according to the present invention, one logic circuit is constructed, and each of the logic circuits comprises an FET.
A logic circuit delay calculation method for calculating a signal propagation time delay due to each effective power supply voltage of a plurality of circuit blocks that operate with different effective power supply voltages, comprising a plurality of logic elements including: Calculate the power supply voltage coefficient which is the value of the power supply voltage ratio of the circuit block,
FE when the effective power supply voltage of each circuit block is applied
A current coefficient which is a value of a ratio of a drain saturation current of the FET when a reference power supply voltage is applied to a drain saturation current of T is calculated, and a reference which is a delay time of each circuit block when the reference power supply voltage is applied. The product of the delay time, the power supply voltage coefficient and the current coefficient of each circuit block is calculated, and the calculation result is set as the effective delay time which is the delay time of each circuit block.

According to a third method for calculating a delay of a logic circuit according to the present invention, when simulating a logic circuit including a plurality of logic elements including an FET, a signal propagation time delay due to a voltage fluctuation of a power supply voltage of the logic circuit is provided. Is a method of calculating a delay of a logic circuit, which calculates a fluctuation voltage due to a current consumption of the logic circuit and a voltage fluctuation caused by a wiring parasitic element of a power line, and then calculates a reference power supply voltage and a fluctuation voltage applied to a power supply terminal. The effective power supply voltage, which is the ratio of the effective power supply voltage to the reference power supply voltage, is calculated by calculating the effective power supply voltage applied to the logic circuit. Calculates the current coefficient which is the value of the ratio of the drain saturation current of the FET when the reference power supply voltage is applied to the drain saturation current of the FET when is applied Calculates the product of the power supply voltage coefficient and the current coefficient as a reference delay time of the logic circuit calculated based on the reference power supply voltage, and calculates the result of the delay of the logic circuit when the effective power supply voltage is applied. The time is an effective delay time.

In a third delay calculation method for a logic circuit,
The current consumption of the logic circuit is the sum of the current consumption of each of the specific logic elements operating together at one operation time among the plurality of logic elements, and the specific logic element is connected based on the sum of the current consumption. It is preferable that the amount of voltage fluctuation of the power supply line be calculated and the amount of voltage fluctuation of the power supply line be used as the fluctuation voltage.

In the first to third logic circuit delay calculation methods, the FET is preferably a P-channel MOSFET.

In the first to third logic circuit delay calculation methods, a value obtained by raising a drain saturation current of an FET to a power of a difference between a power supply voltage and a threshold voltage of the FET by a predetermined coefficient, and raising the power to the power. Is preferably multiplied by a current gain coefficient.

A first logic circuit delay calculation device according to the present invention calculates a signal propagation time delay due to a power supply voltage of a logic circuit when simulating a logic circuit including a plurality of logic elements including FETs. A delay calculation device for a logic circuit, comprising: a layout data providing unit for providing layout data for determining an arrangement of a logic element in the logic circuit; a connection information providing unit for providing connection information of the logic circuit; A process parameter assigning unit for assigning process information for determining electrical characteristics of the logic element; a library data assigning unit for assigning delay data of the logic element; and a value of a ratio of the second power supply voltage to the first power supply voltage. A power supply voltage coefficient is determined, and a first power supply to a drain saturation current of the FET when a second power supply voltage is applied. Power supply coefficient determining means for determining a current coefficient which is a value of a ratio of a drain saturation current of the FET when a voltage is applied, and a first power supply voltage based on delay data, layout data, process information and connection information. Delay calculating means for calculating a delay time of the logic circuit when the voltage is applied, a product of the delay time calculated by the delay calculating means, the power supply voltage coefficient, and the current coefficient, and the calculation result is represented by a second power supply. Effective delay calculating means for calculating an effective delay time of the logic circuit when a voltage is applied.

In the first logic circuit delay calculating device,
The logic circuit is operated by different power supply voltages from each other, is composed of a plurality of circuit blocks constituting one logic circuit, and further includes a power supply voltage information providing means for providing each power supply voltage information of the logic circuit and the circuit block, The coefficient determining means includes means for determining a power supply voltage coefficient for each block that defines a value of a power supply voltage of each circuit block with respect to a reference power supply voltage, and a drain saturation current of the FET when the power supply voltage of each circuit block is applied. And a means for determining a block-by-block current coefficient that defines the value of the ratio of the drain saturation current of the FET when the reference power supply voltage is applied.

In the second logic circuit delay calculating apparatus according to the present invention, when simulating a logic circuit including a plurality of logic elements including FETs, a delay in a signal propagation time due to a voltage fluctuation of a power supply voltage of the logic circuit. A delay calculation device for a logic circuit that calculates layout data, a layout data providing unit for providing layout data for determining an arrangement of a logic element in the logic circuit, a connection information providing unit for providing connection information of the logic circuit, Parameter assigning means for assigning process information for determining electrical characteristics of wiring and logic elements, library data assigning means for assigning delay data and current consumption data of logic elements, and signal wiring using layout data and process parameters Signal wiring extracting means for extracting parasitic elements of Power source wiring parasitic element extracting means for extracting a wiring parasitic element of a power wiring in which a power supply terminal and a logic circuit are connected with each other by using data, and a current consumption of a logic circuit using a parasitic element of a signal wiring and current consumption data. The power supply voltage fluctuation amount is calculated using the current consumption and the power supply wiring parasitic element, and the difference between the power supply voltage applied to the power supply terminal and the voltage corresponding to the voltage fluctuation amount is calculated. And an effective power supply voltage calculating means for calculating an effective power supply voltage, which is an effective power supply voltage, and a power supply voltage coefficient which is a value of a ratio of the effective power supply voltage to the power supply voltage. Delay power supply coefficient determining means for determining a current coefficient which is a value of a ratio of a drain saturation current of the FET when a power supply voltage is applied to a drain saturation current of the FET, and a parasitic element of the signal wiring. Delay calculation means for calculating a delay time when a power supply voltage is applied using the delay data of the element; and calculating a product of the delay time calculated by the delay calculation means, a power supply voltage coefficient and a current coefficient, and Effective delay calculating means for setting the result as an effective delay time of the logic circuit.

In a second logic circuit delay calculating device,
The current consumption calculation means calculates the sum of the current consumption of each of the plurality of logic elements and a specific logic element operating together at one operation time, and the effective power supply voltage calculation means calculates the sum of the current consumption and the power supply. The voltage variation of the power supply wiring to which the specific logic element is connected is calculated using the wiring parasitic element of the wiring, and the delayed power supply coefficient determining means determines the voltage variation amount of the plurality of logic elements in order from the logic element having the earliest operation time. It is preferable to calculate a power supply voltage coefficient and a current coefficient for each logic element using an effective power supply voltage applied to the logic element.

In the second logic circuit delay calculating device,
The logic circuit is an integrated circuit including at least one circuit block each having at least one standard cell. The integrated circuit is provided with an external power supply terminal to which a power supply voltage is applied, and the at least one circuit block has at least one circuit block. A block power supply terminal connected to the external power supply terminal and to which a voltage for driving the circuit block is applied is provided, and at least one standard cell is connected to the block power supply terminal and receives a voltage for driving the standard cell. Current consumption calculating means for calculating a current consumption of a circuit block using current consumption data of a parasitic element of a signal line and current consumption of a standard cell; Chip-level current consumption that calculates the current consumption of an integrated circuit using the current consumption of a block Calculating means for calculating a chip-level fluctuation voltage that is a voltage fluctuation amount of a power supply wiring from an external power supply terminal to a block power supply terminal using current consumption of a circuit block. By calculating a fluctuation voltage calculating means and a difference between a power supply voltage applied to an external power supply terminal and a chip-level fluctuation voltage,
A chip-level effective power supply voltage calculating means for calculating a chip-level effective power supply voltage; and a block-level fluctuation voltage, which is a voltage fluctuation amount from a block power supply terminal to a cell power supply terminal, based on current consumption data of a standard cell. Block level fluctuation voltage calculation means, and a block level effective power supply voltage calculation means for calculating a block level effective power supply voltage by calculating a difference between the chip level effective power supply voltage and the block level fluctuation voltage,
It is preferable to calculate the effective delay time of the integrated circuit based on the block-level effective power supply voltage.

In the second logic circuit delay calculating device,
The current consumption calculating means is configured to calculate, among the plurality of standard cells,
Calculate the sum of the current consumption of each specific standard cell operating together at one operation time, determine the current consumption of the standard cell, and specify the current consumption of the standard cell and the wiring parasitic capacitance of the power supply wiring. The amount of voltage fluctuation of the power supply wiring to which the standard cell is connected is calculated, and the delayed power coefficient determining means calculates the effective power supply voltage applied to the standard cell in order from the standard cell having the earlier operation time among the plurality of standard cells. Preferably, the power supply voltage coefficient and the current coefficient are calculated for each standard cell.

In a second logic circuit delay calculator,
The current consumption calculation means has switching frequency data giving means for giving a switching frequency for each node of the connection information, and calculates the current consumption of the integrated circuit by using the switching frequency, the current consumption of the parasitic element of the signal wiring and the current consumption of the standard cell. Preferably, it is calculated.

In the second logic circuit delay calculating device,
The current consumption calculation means calculates a transition probability, which is a probability of transition from one logical value to another logical value, using a logical function included in the connection information, and calculates a transition probability, a parasitic element of a signal wiring, and a consumption of a standard cell. It is preferable to calculate the current consumption of the integrated circuit using the current data.

In the delay calculation device for the first or second logic circuit, the calculation result output by the effective power supply voltage calculation means is stored, and the current calculation result of the effective power supply voltage calculation means and the stored calculation result are compared with each other. Convergence condition judging means for judging whether or not the difference falls within a predetermined range, and when the difference does not fall within the predetermined range, repeating the current consumption calculating means and the effective power supply voltage calculating means until the difference falls within the predetermined range. Is preferred.

In the delay calculation device for the first or second logic circuit, the FET is preferably a P-channel MOSFET.

In the delay calculation device for the first or second logic circuit, the drain saturation current of the FET is determined by the power supply voltage and the FE
Preferably, the difference between T and the threshold voltage is raised to a power by a predetermined coefficient, and the value obtained by raising the power is multiplied by a gain coefficient of the current.

A first method of calculating delay data of a delay library according to the present invention is a method of calculating delay data of a signal propagation time of a delay library used for simulation of a logic circuit composed of logic elements including FETs. A power supply voltage coefficient defining step of defining a power supply voltage coefficient which is a value of a ratio of the second power supply voltage to the power supply voltage; and a first power supply voltage with respect to a drain saturation current of the FET when the second power supply voltage is applied. A current coefficient defining step of defining a current coefficient which is a value of a ratio of a drain saturation current of the FET when applied, and a first delay time which is a delay time of a logic circuit when the first power supply voltage is applied A first delay time defining step, and calculating a product of the first delay time, the power supply voltage coefficient, and the current coefficient, to obtain a logical circuit when the second power supply voltage is applied. The second determines the delay time is a delay time, and a delay data determination step of the delay data delay time of the second.

In the first delay data calculating method of the delay library according to the present invention, the FET is a P-channel MOSF
Preferably it is ET.

In the first delay data calculation method of the delay library according to the present invention, the drain saturation current of the FET is obtained by raising the difference between the power supply voltage and the threshold voltage of the FET to a power by a predetermined coefficient and raising the power. Preferably, the value is obtained by multiplying the obtained value by the gain factor of the current.

A second method of calculating delay data of a delay library according to the present invention is a method of calculating delay time of signal propagation time of a delay library used for simulation of a logic circuit including a logic element including a P-channel MOSFET and an N-channel MOSFET. A power supply voltage coefficient defining step of defining a power supply voltage coefficient which is a value of a ratio of the second power supply voltage to the first power supply voltage; and a drain of the P-channel MOSFET when the second power supply voltage is applied. P channel M when the first power supply voltage for the saturation current is applied
A first current coefficient defining step of defining a first current coefficient which is a value of a ratio of a drain saturation current of the OSFET; and a first current coefficient defining step for the drain saturation current of the N-channel MOSFET when a second power supply voltage is applied. A second current coefficient defining step of defining a second current coefficient which is a value of a ratio of a drain saturation current of the N-channel MOSFET when the power supply voltage is applied, and a logic when the first power supply voltage is applied A first delay time defining step of defining a first rise delay time and a first fall delay time of the circuit; and calculating a product of the first rise delay time, a power supply voltage coefficient, and a first current coefficient. Thus, the second rising delay time, which is the rising delay time of the logic circuit when the second power supply voltage is applied, is determined, and the second rising delay time is set to the rising delay data. Rise delay data determining step and a first fall delay time and the power supply voltage coefficient second to
, A second fall delay time, which is a fall delay time of the logic circuit when the second power supply voltage is applied, is determined, and the second fall delay A falling delay data determining step of using time as falling delay data.

In the second method for calculating delay data of a delay library according to the present invention, the drain saturation current of each of the P-channel MOSFET and the N-channel MOSFET is determined by calculating the difference between the power supply voltage and the threshold voltage of each MOSFET by a predetermined coefficient. It is preferable that the powers are obtained by multiplying the values obtained by the powers by the current gain coefficients.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a method of calculating the power supply voltage dependence of the delay time in a logic circuit according to the present invention will be described.

FIG. 1 is a graph showing the power supply voltage dependence of the delay time of each basic CMOS gate of a 2-input NAND gate, 2-input NOR gate, 4-input NAND gate and 4-input NOR gate used in a logic circuit. In FIG.
1 indicates a 2-input NAND gate, 2 indicates a 2-input NOR gate, 3 indicates a 4-input NAND gate, and 4 indicates 4
The input NOR gate is shown. 5 is a P-channel MOS
Power supply voltage Vdd with respect to FET drain saturation current Idsp
6 is an N-channel MOSF
The ratio of the power supply voltage Vdd to the drain saturation current Idsn of the ET (Vdd / Idsn).

FIG. 2 shows about 300 layouts obtained by the building block method using standard cells.
9 is a graph showing the power supply voltage dependence of the delay time of a circuit block equivalent to 0 gates and a 4 KB static RAM circuit. In FIG. 2, reference numeral 7 denotes a logical block, and reference numeral 8 denotes a static RAM. 9 is a ratio (Vdd / Idsp) of the power supply voltage Vdd to the drain saturation current Idsp of the P-channel MOSFET of each circuit, and 10 is a ratio (Vdd / Idsn) of the power supply voltage Vdd to the drain saturation current Idsn of the N-channel MOSFET of each circuit. ).

Here, the drain saturation current is obtained by converting the gate-source voltage and the drain-source voltage to the power supply voltage Vdd.
Is the current when set to.

Hereinafter, a method for analytically obtaining the delay of the signal propagation time of the logic circuit will be described.

In general, the delay time of a logic circuit is the time for discharging the charge Q stored in the load capacitance by the drain current of the MOSFET, and thus has the following relationship (Equation 1).

[0043]

(Equation 1)

[Formula 2] is obtained by transforming [Formula 1].

[0045]

(Equation 2)

Here, Cl is a load capacity, Id is a drain current, ΔV is a potential change due to charge / discharge of the load capacity, and Td is a delay time.

Further, since Id and ΔV change according to the power supply voltage Vdd, the following relational expression [Equation 3] is further derived.

[0048]

(Equation 3)

Here, Ids is the drain saturation current at the power supply voltage Vdd.

The power supply voltage dependency exists in the drain saturation current Ids. The power supply voltage dependency of the drain saturation current Ids mainly includes dispersion scattering, phonon scattering,
The effect of reducing the mobility of carriers by the electric field Vgs / Tox between the gate and the source (Vgs is the voltage between the gate and the source and Tox is the thickness of the oxide film) caused by scattering due to surface undulations, Electric field Vds / L between drain and source
eff (where Vds is the drain-source voltage and Lef
f is the effective channel length. ), And the decrease in threshold voltage due to the short-channel effect caused by the drain electric field.

The drain current Id combining these effects is
Expression of IEEE Jounal of Solid-State Circuits, vo
l.25, N0.2, April 1990, pp. 584-594, and the expression of the drain saturation current Ids using this format is shown in the following equation [Equation 4].

[0052]

(Equation 4)

Here, β is a gain coefficient of the MOSFET expressed by β = μ · Cox · W / L, and each variable is: μ: mobility of carrier Cox: capacitance per unit area of the gate oxide film W: gate width L: gate length Vt: threshold voltage of the MOSFET. The value of the index α is the long channel M
It is 2 as is well known in OSFET.

For example, in a CMOS device having a small gate length by a 0.5 μm CMOS process or the like, when the gate-source voltage Vgs, the drain-source voltage Vds, and the power supply voltage Vdd are all set to 3.3 V, , The index α of the N-channel MOSFET is 1.1 to 1.
2 and the index α of the P-channel MOSFET becomes 1.5 to 1.6. As the power supply voltage Vdd decreases, the index α approaches 2 of the long channel MOSFET model.

When the power supply voltage dependency of the drain saturation current Ids is compared between the P-channel MOSFET and the N-channel MOSFET, the decrease rate of the drain saturation current due to the decrease in the power supply voltage is determined from the value of the index α.
It turns out that ET is larger. Therefore, FIGS. 1 and 2
As shown in FIG. 5, the dependency of the delay time on the power supply voltage depends on the ratio of the power supply voltage Vdd to the drain saturation current Idsp (Vdd / Ids).
Explain that it almost matches p).

Using the relational expression [Equation 3] and the calculation expression [Equation 4], the delay time Td is calculated based on the drain saturation current Ids and the MOSFE.
By expressing the T as a function of the threshold voltage Vt and the index α, the dependency of the delay time on the power supply voltage can be obtained in a simple form shown in the following [Equation 5].

[0057]

(Equation 5)

Here, Vdd0 represents a reference power supply voltage used as a reference for calculating the delay time, for example, a power supply voltage used as a reference when the delay data is extracted from the cell library. Idsp0 is the P-channel M at the reference power supply voltage Vdd0.
Represents the drain saturation current of the OSFET, Td0 represents the reference delay value of the logic circuit determined as the reference power supply voltage Vdd0, and α0 represents the index α of the drain saturation current at the reference power supply voltage Vdd0. Idspi represents the drain saturation current of the P-channel MOSFET at the power supply voltage Vddi,
αi is the drain saturation current Idsi when the power supply voltage is Vddi.
Represents an index α.

As shown in this equation, the power supply voltage Vddi and the index α are added to the reference delay value Td0 obtained by the delay calculation.
multiplied by the delay power supply coefficient Kv (Vddi) indicating the relationship with the reference power supply voltage Vdd0,
The delay time Td at i can be easily and reliably calculated.

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 3 shows an operation flow of the delay calculating device for a logic circuit according to the first embodiment of the present invention. The delay calculation device for a logic circuit according to the present invention is assumed to be a computer having an external storage device, and the external storage device and the computer may be of any form or model.

First, as shown in FIG. 3, various data necessary for calculating the delay of the signal propagation time of the logic circuit are prepared in advance. 11 is held in the layout data providing means,
The layout data of the circuit and the standard cell to be subjected to the delay analysis, 12 are held in the process parameter assigning means, and the wiring parameters consisting of the wiring resistance, the wiring capacitance, and the magnetic permeability per unit shape, and 13 are held in the connection information assigning means. Circuit connection information, which is a gate-level connection description of the circuit to be analyzed, is stored in the library data providing means, cell delay data extracted at the reference power supply voltage Vdd0, and 15 is stored in the operating power supply voltage providing means. The predetermined operating power supply voltage data 16 is a saturation current parameter which is held in the process parameter assigning means and determines the drain saturation current such as carrier mobility and oxide film thickness.

Next, in the signal wiring extraction step S01,
The signal wiring extracting means extracts desired wiring resistance, wiring capacitance, and wiring inductance for each signal node from the layout data 11, the wiring parameters 12, and the circuit connection information 13. Note that if the operating frequency of the logic circuit is 1 GHz or less, the calculation of the wiring inductance may be omitted.

Next, in the delay calculating step S02, the delay calculating means uses the cell delay data 14 serving as a reference and the wiring resistance and the wiring capacitance extracted in the signal wiring extracting step S01 as a logic circuit to be analyzed. Is calculated at the reference power supply voltage Vdd0.

Next, in the delayed power supply coefficient determining step S03, the delay power supply coefficient determining means determines the predetermined operating power supply voltage data 15 (= Vddi) and the predetermined operating power supply voltage data 15 (= Vddi).
After calculating the drain saturation current Idspi of the P-channel MOSFET based on the saturation current parameters 16 such as carrier mobility and oxide film thickness based on the reference power supply voltage Vdd
The value of the ratio to the drain saturation current Idsp0 of the P-channel MOSFET at 0 is calculated to determine the delay power supply coefficient Kv (Vddi) at the operating power supply voltage Vddi.

Next, in the effective delay calculating step S04,
The effective delay calculating means calculates the delay time at the reference power supply voltage Vdd0 calculated by the delay calculating means, the delayed power coefficient Kv (Vddi) calculated by the delay power coefficient determining means, as shown in the equation [5]. To determine the delay time at the operating power supply voltage Vddi.

FIG. 4 is a calculation flow detailing the delayed power supply coefficient determination step S03. In FIG. 4, a P-channel MO
Using the above equation (Equation 4) to calculate the drain saturation current Idspi of the SFET, the index αi corresponding to the operating power supply voltage Vddi is selected to determine the drain saturation current Idspi.

First, in the operating power supply voltage determining step S31, a predetermined operating power supply voltage Vddi is extracted from the operating power supply voltage data 15 shown in FIG. 3, and then in the index determining step S32, the operating power supply voltage Vddi is set in advance. Power supply voltages Vdd0, Vdd1, Vdd2, ..., Vddn-1, Vddn
(Where n is an integer greater than or equal to 2), the index is determined by the index αi in the operating power supply voltage Vddi.
To determine.

Next, a drain saturation current determining step S33A
, The drain saturation current Idspi at the operating power supply voltage Vddi is determined using the saturation current parameter 16 and the calculation formula [Equation 4].

Next, in a delayed power supply coefficient determining step S34, a power supply voltage coefficient (= Vddi / Vdd0) which is a value of a ratio of Vddi to a reference power supply voltage Vdd0, and an operation power supply voltage V
After calculating the current coefficient (= Idsp0 / Idspi), which is the ratio of the drain saturation current Idspi at ddi to the drain saturation current Idsp0 at the reference power supply voltage Vdd0, calculate the product of the power supply voltage coefficient and the current coefficient. Power supply voltage V
Calculate the delay power supply coefficient Kv (Vddi) for ddi.

As a specific method for assigning the relationship between the operating power supply voltage Vddi and the index αi, for example, a method using a table model in a table format or the like can be considered.

As described above, the power supply voltage dependence of the delay time can be easily and reliably calculated only by obtaining the relationship between the operating power supply voltage Vddi and the index αi of the operating power supply voltage Vddi.

The advantage that the relationship between the operating power supply voltage Vddi and the drain saturation current Idspi is defined by the index αi is that there are only two elements that change the drain saturation current Idspi, the operating power supply voltage Vddi and the index αi. That is, a smooth change in the current characteristic can be expressed with a smaller number of data than when the drain saturation current Idspi is directly defined.

FIG. 5 shows a calculation flow for determining the delay power supply coefficient Kv (Vddi) from the relational expression between the operation power supply voltage Vddi and the drain saturation current Idspi. This example expresses the drain saturation current Idspi based on the current equation of the SPICE transistor model BSIM3ver2 proposed by the University of California, Berkeley, as shown in the following equations (Equation 6) and (Equation 7). .

[0075]

(Equation 6)

[0076]

(Equation 7)

The following shows each variable.

Vsat: carrier saturation speed W: gate width of MOSFET L: gate length of MOSFET Cox: capacitance per unit area of gate oxide film Vdsat: drain-source voltage at which drain current is saturated Abulk: substrate charge effect Coefficient (coefficient calculated based on SPICE parameter) Esat: Critical electric field (SPICE) at which carrier velocity is saturated
Value calculated based on parameters)

As shown in FIG. 5, the procedure for determining the delay power supply coefficient is as follows. First, in the operation power supply voltage determining step S31, a predetermined operation power supply voltage Vddi is determined from the operation power supply voltage data 15 shown in FIG. Saturation current determination step S3
In 3B, the drain saturation current Idspi at the operating power supply voltage Vddi is calculated according to the saturation current parameter 16 and the equations [Equation 6] and [Equation 7].

The subsequent steps are the same as the delayed power coefficient determining step S34 shown in FIG.

As described above, according to the present embodiment, only by determining the relationship between the operating power supply voltage Vddi and the drain saturation current Idspi of the P-channel MOSFET, the cell determined by the power supply voltage under one condition as a reference is obtained. The power supply voltage dependence of the delay time of the logic circuit can be easily calculated using the delay data of the library.

In this embodiment, a circuit block of a building block type integrated circuit using standard cells is taken as an example. However, a gate array or a custom designed circuit block may be used.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 6 shows an integrated circuit in which a delay calculation device for a logic circuit according to a second embodiment of the present invention is a target of delay calculation and has a built-in circuit block that operates at a plurality of different power supply voltages. In FIG. 6, reference numeral 50 denotes an integrated circuit to be calculated by the present delay calculating apparatus, which includes a circuit block 50a operating at the first operating power supply voltage Vdd1 and a first operating power supply voltage Vdd1 because high-speed operation is required. Second higher than
A high-speed operation circuit block 50b which operates at the operation power supply voltage Vdd2, and a low power consumption circuit block 50c which operates at the third operation power supply voltage Vdd3 lower than the first operation power supply voltage Vdd1 because low power consumption is required. And an input / output circuit block 50d operating at a fourth operating power supply voltage Vdd4 determined by an external peripheral device of the integrated circuit 50.

FIG. 7 shows an operation flow of the delay calculation device for a logic circuit according to the second embodiment of the present invention. 7, the description of the components shown in FIG. 3 will be omitted by retaining the same reference numerals. Reference numeral 17 denotes a circuit block 50 which is held in the operating power supply voltage information providing means and is, for example, a circuit block 50 shown in FIG.
a, 50b, 50c, and 50d are circuit block operation power supply voltage data assigned to each block.

Here, the steps different from those of the first embodiment will be described. In the delayed power coefficient determining step S03A, the delayed power coefficient determining means includes the circuit block operating power voltage data 17 and the circuit block operating power voltage data. 1
The delay power supply coefficient Kv for each circuit block is determined based on the saturation current parameters 16 such as carrier mobility and oxide film thickness based on 7 and the circuit connection information 13.

Next, in the same manner as in the first embodiment, in the effective delay calculating step S04, the effective delay calculating means uses the respective delay power supply coefficients Kv determined by using the calculation formula [Equation 5]. The delay time of each circuit block of the integrated circuit 50 is determined.

As described above, despite the use of a plurality of different operating power supply voltages for the integrated circuit 50, the delay calculation step S0
The delay time corresponding to each operation power supply voltage can be corrected in the effective delay calculation step S04 of the final stage using the delay data 14 generated by the reference power supply voltage Vdd0 up to 2, so that the delay is different for each power supply voltage as in the prior art. Since it is not necessary to use a cell library having data, it is possible to reduce the time required for creating a library.

As described above, according to the present embodiment, the delay calculation of the integrated circuit 50 composed of the circuit blocks having different operation power supply voltages for the purpose of increasing the operation speed and reducing the power consumption is performed.
It can be easily and reliably calculated using the cell delay data 14 created under standard power supply voltage conditions.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

In this embodiment, a voltage fluctuation occurs in the power supply line of the integrated circuit, and a delay occurs when the power supply voltage applied to the power supply terminal of the integrated circuit is different from the power supply voltage effectively applied to the internal circuit. The calculation method and the delay calculation device will be described.

First, the effect of the delay in the signal propagation time due to the voltage fluctuation of the wiring parasitic elements of the VDD line and the VSS line will be described with reference to FIG.

In general, m (where n is an integer of 1 or more) m
Consider an integrated circuit to which (where m is an integer equal to or greater than 1) circuit blocks. As shown in FIG. 8, it is assumed that m circuit blocks are connected to n pairs (here, n = 2) of VDD lines and VSS lines. A power supply voltage of the reference potential Vdd0 is applied to a power supply terminal of the integrated circuit, and m circuit blocks are connected to the power supply terminals. The average current consumption of each of the circuit blocks 1,..., M is Ii (where i = 1, 2,..., M−1, m is an integer). The existing VDD line and VSS line have the same wiring length and the same wiring width. Further, each wiring resistance, each wiring capacitance, and each inductance are equal to each other, and are sequentially designated as R, C, and L.

FIG. 9 shows a first equivalent circuit of the integrated circuit shown in FIG. 8. For example, it is assumed that the average current consumption I1 of the block 1 is obtained by connecting two current sources of I1 / 2 to each other in parallel. The wiring parasitic element of the power wiring includes the resistance, inductance, and capacitance of the wiring. Further, the first equivalent circuit is connected to a capacitance due to a diode junction between the source and the substrate of the MOSFET, and becomes an equivalent circuit of the power supply wiring as shown in FIG.

FIG. 10 is a second equivalent circuit in which the integrated circuit shown in FIG. 8 is most simplified and has a pair of power supply lines. The wiring parasitic element of the power supply wiring is simplified, and in this embodiment,
The second equivalent circuit is an analysis model for calculating a voltage drop due to the wiring resistance of the VDD line and the VSS line. Using the second equivalent circuit shown in FIG. 10, the potential Vm of the mth node of the VDD line furthest from the power supply and the potential Um of the mth node of the VSS line are calculated.

When Kirchhoff's current law is applied to the potentials V1, V2,..., Vm of the nodes of the VDD line in the circuit blocks 1,..., M shown in FIG. Is led.

[0097]

(Equation 8)

Expression (1), Expression (2),..., Expression (m-1),
After adding the left and right sides of equation (m), respectively,
By solving for the potential Vm of the m-th node of the VDD line, the following equation (Equation 9) is obtained.

[0099]

(Equation 9)

The potential Vm at the m-th node of the VDD line
The potential U at the m-th node of the VSS line is
When m is obtained, the following calculation formula [Equation 10] is obtained.

[0101]

(Equation 10)

The voltage drop amount of the VDD line is equal to the reference power supply voltage V
difference between the potential dd0 and the potential Vm of the m-th node of the VDD line (Vdd
0 -Vm). On the other hand, the amount of voltage drop (rise) of the VSS line is represented by the potential Um of the m-th node of VSS. The sum of the two becomes the voltage drop amount of the VDD line and the VSS line. Further, the wiring resistance R is changed to the sheet resistance ρ of the wiring.
s, the wiring width W, and the wiring length L0, the voltage drop amount Vdr
“op” is represented by the following equation [Equation 11].

[0103]

[Equation 11]

The effective power supply voltage Vddeff actually applied to each of the circuit blocks 1,..., M is a voltage resulting from the difference between the reference power supply voltage Vdd0 applied to the power supply terminal and the voltage drop Vdrop, and is shown below. It is represented as a calculation formula [Equation 12].

[0105]

(Equation 12)

Next, a numerical calculation example of the effective power supply voltage Vddeff will be shown taking a specific integrated circuit as an example.

FIG. 11A is a layout diagram of an integrated circuit to be analyzed for the effective power supply voltage Vddeff. Here, as in the case shown in FIG. 10, only the resistance is considered as the wiring parasitic element of the power supply wiring. As shown in FIG. 11A, the first VDD terminal 51 is connected to a first VDD line 55.
, And the second VDD terminal 52 is connected to the second VDD line 5.
6, the first VSS terminal 53 is connected to the first VSS line 57, and the second VSS terminal 54 is connected to the second VSS
Connected to line 58. The first circuit block 61, the second circuit block 62, the third circuit block 63, and the fourth circuit block 64 include a first VDD line 55, a second V
DD line 56, first VSS line 57, and second VSS line 5
8 respectively.

The integrated circuit shown in FIG. 11A is different from the integrated circuit shown in FIG. 8 in that the first circuit block 61, the second circuit block 62, the third circuit block 63, and the fourth circuit block 64 are different from the integrated circuit shown in FIG. 4 circuit blocks and 2 pairs of VD
D line and VSS line are provided, and VDD line and V line
This is equivalent to the condition that the wiring length of each SS line is 5 mm and the wiring length L0 per block of each VDD line and VSS line is 1.25 mm. The integrated circuit shown in FIG. 11A has a sheet resistance ρ of each of the first VDD line 55 and the second VDD line 56, and the first VSS line 57 and the second VSS line 58.
s is 50 mΩ / □ respectively.

The integrated circuit shown in FIG.
5A shows an equivalent circuit of the integrated circuit shown in FIG.
The average current consumption flowing through the circuit block 61, the second circuit block 62, the third circuit block 63, and the fourth circuit block 64 is denoted by I61, I62, I63, and I64, respectively.

FIG. 12 shows the wiring width W of the VDD line and the VSS line.
12 is a graph showing the relationship between the power supply voltage Vddeff and the circuit blocks 61, 62, 6 shown in FIG.
This is a calculation result of calculating the effective power supply voltage Vddeff using the calculation formula [Equation 12] when it is assumed that the average current consumptions I61, I62, I63, and I64 of Eq. In FIG. 12, 171A indicates the case where the current consumption is 5 mA, 172A indicates the case where the current consumption is 10 mA, 173A indicates the case where the current consumption is 15 mA, and 17
4A represents the case where the current consumption is 20 mA.

FIG. 13 is a graph showing the relationship between the wiring width W of the VDD line and the VSS line and the relative value of the delay time. Each of the circuit blocks 61 and 62 shown in FIG.
Average current consumption I61, I62, I of four circuits 63, 64
It is a calculation result when assuming that 63 and I64 are both equal. In FIG. 13, 171B has a current consumption of 5 m.
A, 172B when the current consumption is 10 mA,
173B indicates the case where the current consumption is 15 mA, and 174B
Indicates the case where the current consumption is 20 mA.

A specific calculation method is as follows. After calculating the effective power supply voltage Vddeff using the calculation formula [Equation 12], the P-channel M
The effective power supply voltage Vdd is added to the gate-source voltage Vgs in the formula [Equation 4] for calculating the drain saturation current of the OSFET.
Then, the relative value (= Kv (Vdd)) of the delay time is calculated by using a calculation formula [Equation 5] for calculating the delay time.

In the conventional circuit design of the integrated circuit, it is assumed that the power supply voltage VDD and the ground voltage VSS of the integrated circuit are ideal power supplies, and the power supply voltages applied to the VDD terminal and the VSS terminal of the integrated circuit are the power supply voltage VDD, respectively. And the ground voltage VSS.

However, for example, when four circuits having an average current consumption of 10 mA are connected to the VDD line and the VSS line having a wiring width of 30 μm, the curve 172A in FIG.
As shown in (1), the sum of the voltage fluctuation amounts of the VDD line and the VSS line is about 0.2 V when the power supply voltage VDD is 3.3 V. Further, as shown by a curve 172B in FIG. 13, the increase in the delay time is 5% or more. Therefore, when realizing high-speed operation with a frequency of 100 MHz or more, the current consumption increases, and the VDD line and the VSS
Delay fluctuations due to line voltage fluctuations cannot be ignored.

Further, in a process requiring fine processing such as a 0.5 μm CMOS process, the number of metal wiring layers is increased in order to achieve high integration. However, it is easy to flatten an insulating film between wiring layers. Therefore, the thickness of each wiring layer tends to be reduced. As a result, the sheet resistance of the wiring layer increases, and the voltage fluctuation of the VDD line and the VSS line tends to increase.

FIG. 14 shows a third embodiment of the present invention.
5 shows an operation flow of the delay calculation device in consideration of voltage fluctuations of a VDD line and a VSS line in a logic circuit. FIG.
In FIG. 3, the description of the components shown in FIG. 3 will be omitted by retaining the same reference numerals.

As shown in FIG. 14, layout data 1
Reference numeral 8 denotes layout data of an integrated circuit whose delay time is to be analyzed, and includes layout wiring information of VDD lines and VSS lines in addition to wiring data and layout data of standard cells. The circuit activation rate data 19 has information on the switching rate at which the current of each node switches in the circuit connection information 13. The cell current consumption data 20 is current consumption data of a standard cell used in a logic circuit.

The operation of the delay calculator configured as described above will be described below.

First, in the power supply (VDD / VSS) wiring parasitic element extraction step S10, the power supply wiring extraction means is connected to the integrated circuit to be analyzed using the layout data 18, the wiring parameters 12, and the circuit connection information 13. ,
A wiring parasitic element of a power supply line composed of a VDD line and a VSS line is extracted, and connection information of a logic element connected to the VDD line and the VSS line is extracted. In a signal wiring extraction step S01, wiring resistance and wiring capacitance are extracted.

Thereafter, in the current consumption calculating step S11, the current consumption calculating means includes the wiring resistance and the wiring capacitance extracted in the signal wiring extracting step S01, the circuit activation rate data 19, the cell current consumption data 20, and the power supply voltage initial value. 21, the current consumption of the integrated circuit is calculated.

For example, in order to calculate the current consumption Idgate of each gate, the following equation (Equation 13) is used.

[0122]

(Equation 13)

Here, Icl of the first term is a current required when the cell charges or discharges a load capacitance, Ks is a circuit activation rate, f is an operating frequency, Cl is a load capacitance, and Vdd.
Is the power supply voltage. The second term, Ipen, represents a through current flowing between the VDD line and the VSS line during cell switching. When the input voltage of the cell is VS
In a switching period Ts for switching from S to VDD or from VDD to VSS, the value when the current flowing through the pull-up circuit formed by the PMOS and the pull-down circuit formed by the NMOS is equal and the maximum is the maximum through current Ipp. The triangle wave approximation is performed on the assumption that The switching period Ts is determined by the driving capability of the cell, the wiring capacitance and the wiring resistance.

The circuit activation rate Ks is obtained, for example, by performing a simulation at the stage of creating a gate-level netlist by logic synthesis from the function description in the function design stage in the circuit design of the integrated circuit, and obtaining the switching frequency of each node. Can be calculated. Circuit activation rate K
Since s does not depend on the wiring capacity or the current data of the cell library, by giving a test pattern to the netlist even if there is no information on the load capacity or resistance capacity of the actual wiring,
The circuit activation rate Ks of each node can be calculated.
Once the circuit activation rate Ks is obtained, when the manufacturing process is changed, when the operating conditions such as the operating frequency and the power supply voltage are changed, and when the layout shape is appropriately changed like a soft macro library In such a case, it is not necessary to re-simulate the consumption current Idgate by giving a test pattern to the netlist again.

As described above, by using the calculation formula [Equation 13], the consumption current Idgate can be statically calculated from the circuit activation rate, the wiring capacitance, the wiring resistance, and the current consumption data of the cell, which are obtained in advance. There is an advantage.

Further, there is a method of using a logic value transition probability based on a logic function of a netlist as the circuit activation rate Ks. This example will be described with reference to the circuit diagram of the full adder shown in FIG. 15A and the truth table shown in FIGS. 15B and 15C. As shown in FIG. 15A, the full adder according to the present embodiment includes an intermediate sum generation circuit A that outputs an intermediate sum s and an intermediate carry generation circuit B that outputs an intermediate carry co.

Intermediate sum generation circuit A has a first NAND terminal having one input terminal connected to node b, the other input terminal connected to node ci, and the output terminal connected to node u.
A gate G1 and one input terminal are connected to the node b;
A first NAND-OR composite gate G2 having the other input terminal connected to node ci, the other input terminal connected to node u, and the output terminal connected to node v, and one input terminal connected to node a EX- connected with the other input terminal connected to the node v and the output terminal connected to the node s.
FIG. 15B shows a truth table of the intermediate sum generation circuit A.

Intermediate carry generation circuit B has one input terminal connected to node b, the other input terminal connected to node ci, the other input terminal connected to node a, and the output terminal connected to node w. A second NAND-OR composite gate G4 connected thereto, and one input terminal connected to the node b;
A second NAND gate G5 having the other input terminal connected to the node ci, the output terminal connected to the node x, one input terminal connected to the node w, the other input terminal connected to the node x, The output terminal comprises a third NAND gate G6 connected to the node co.
(C) shows a truth table of the intermediate carry generation circuit B.

As shown in FIG. 15B, the probability that the logical value of the node u is "1" is 3/4, and the logical value of the node u is "0".
Is 1/4. When the probability that the logical value of the node u transitions is obtained based on this result, the probability that the logical value “1” transitions to the logical value “0” is 3/4 × １ ／ = 3 /
Sixteen. The probability of transition from the logical value “0” to the logical value “1” is ４ × 3/4 = 3/16. Similarly, for the other nodes v, w, and x, the probabilities of transition from the logical value “0” to “1” or from the logical value “1” to “0” can be obtained.

The transition from the logical value “0” to “1” means charging from the VDD line by switching of the P-channel MOSFET in the logical element. At the time of this charging, a voltage drop occurs on the VDD line. Further, the transition from the logical value “1” to “0” means a discharge to the VSS line due to the switching of the N-channel MOSFET in the logical element, and a voltage drop (actually a voltage rise) occurs in the VSS line. . As described above, the transition probability of the logical value is obtained using the logical function included in the netlist, and the VDD line or the VS
The current flowing through the S line can be calculated.

Note that a method of dynamically calculating the current consumption Idgate using the test pattern may be used.

Next, using the current consumption calculated by the current consumption calculation means in the current consumption calculation step S11 and the wiring parasitic element extracted by the power supply wiring extraction means in the power supply wiring parasitic element extraction step S10, the power supply (VDD · VS
S) The effective power supply voltage applied to the circuit by the effective power supply voltage calculation means in the effective power supply voltage calculation step S13 after the voltage fluctuation amounts of the VDD line and the VSS line are calculated in the wiring voltage fluctuation calculation step S12. Effective power supply voltage V
ddeff is calculated.

Thereafter, in the same manner as described in the first embodiment, the processing is performed in the order of the delay calculation step S02, the delay power supply coefficient determination step S03, and the effective delay calculation step S04, and the effective processing of the integrated circuit to be analyzed is performed. The effective delay time can be calculated.

As described above, according to the present embodiment, the increase in the delay time due to the voltage fluctuation of the VDD line and the VSS line caused by the miniaturization of the manufacturing process can be reliably estimated when performing the logic level delay calculation. be able to.

Note that the switching frequency may be directly used as the circuit activation rate Ks instead of the transition probability.

In this embodiment, the delay calculation is performed on the design data after the layout design is completed. However, even before the layout design, the delay calculation is performed by calculating the wiring resistance based on the estimated data from the floor plan. The increase in time can be estimated.

Although a building block type circuit using standard cells is assumed, a circuit such as a gate array may be used.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

In the third embodiment, the current consumption is treated as DC. Actually, the current consumption dynamically changes according to the operation time of the circuit. Therefore, if the current consumption assumed on a DC basis is used, the amount of voltage fluctuation of the VDD line and the VSS line is underestimated or overestimated. Cases can arise.

In the present embodiment, the current consumption and the voltage fluctuation of the power supply line according to the operation time of the circuit are calculated using a static method so that the current consumption dynamically changing in the actual circuit operation can be handled. Thus, the accuracy of the effective power supply voltage is improved by introducing a method and means for performing the above.

FIG. 16 shows an operation flow of the delay calculation apparatus according to the present embodiment, which considers the operation time of the logic element in the voltage fluctuation of the VDD line and the VSS line in the logic circuit. Here, in FIG. 16, the same components as those in FIG. Third
The difference from this embodiment is that the dynamic current consumption calculating step S200
, The calculation result of the delay calculation step S02 and the power supply (VD
And (D.VSS) wiring parasitic element extraction step S10.

FIG. 17 shows a detailed flow of the dynamic current consumption calculation step S200 in FIG. 16. As shown in FIG. 17, the circuit delay determination step S201 receiving the calculation result of the delay calculation step S02 determines that the circuit delay is maximum. This is a step of determining whether a gate output in another delay path and another gate output are a rising delay or a falling delay, respectively. It is assumed that a current flows through the VDD line when a rise delay occurs and a current flows through the VSS line when a fall delay occurs. Therefore, in the case of a rise delay,
In the VDD line consumption current waveform calculation step S202, one V
The consumption current flowing through the DD line is calculated in accordance with the operation time of the logic element connected to the VDD line. On the other hand, in the case of the fall delay, the VSS line consumption current waveform calculation step S203
, The consumption current flowing through one VSS line is calculated in accordance with the operation time of the logic element connected to the VSS line.

Normally, the delay calculation result is obtained by using a static timing analysis technique. If the sum of the current consumptions of all the logic elements is obtained using the same static method, the sum of the current consumptions includes the current consumption of the logic elements that do not operate at the same time. In order to avoid this, in the effective power consumption calculation step S204, only the logic elements operating at one operation time using the circuit activation rate data 19 are targeted.
Find a more realistic current consumption.

The VDD line consumption current waveform calculation step S202 and the VSS line consumption current waveform calculation step S203 shown in FIG.
Will be described with reference to FIG. FIG. 18 shows an example using the full adder according to the third embodiment shown in FIG.
The relationship between the VSS line and the VDD line for each logic gate that performs switching is shown. In FIG. 15, the first
, The first NAND-OR composite gate G2, the second NAND-OR composite gate G4, and the second
NAND gate G5 is connected to one VDD line / VSS line pair, and the EX-NOR gate G3 and the third NA
It is assumed that the ND gate G6 is connected to another VDD line / VSS line pair. Here, the maximum delay path is the node b,
a path passing through u, v, s and nodes b, u, v, s
, That is, each logical value is {b, u, v, s} =
From {0,1,0,1} to {b, u, v, s} = {1,
Assume a transition to 0,1,0}. At this time, the logical values of the other nodes can be determined from the result of the static timing analysis and the like.

Each node b, u, v, s of the maximum delay path
When a test pattern that can be activated as in the above potential change is found, a current flows through the VDD line when each node in the logic circuit transitions from “0” to “1”. When the value transits from “1” to “0”, it is assumed that a current flows through the VSS line. When simplifying this assumption, the maximum delay path is set to the logical value transition of the above node, and the other nodes are set to the VDD line and the VSS line based on the transition probability determined from the logical function shown in the third embodiment. Of which the current flows.

FIG. 19A shows an example of the components of the cell current consumption data 20 used for calculating the current consumption in the library shown in FIG. 17, and as shown in FIG. In the library, the consumption current I is approximated by a triangular wave, and a load capacitance and a wiring resistance (time constant RC), a peak current Ipeak corresponding to the load capacitance and the wiring resistance, and a half-width ΔT of the transition time are described. .

First, as shown in FIG. 18A, the logical values of the nodes b and v transition from 0 to 1, so that the voltage value V of the nodes increases, and the logical values of the nodes u and s change from 1 to 0. , The voltage value V of the node is falling. The times of the peak currents Ipeak approximated by triangular waves shown in FIG. 18B are matched so as to correspond to the switching times of these logic elements, respectively, and the current waveforms of the logic elements are superimposed to form the VDD line or the VSS. The current consumption flowing through the line is calculated. At this time, VD
The current consumption waveforms of the logic elements connected to one VDD line / VSS line pair are overlapped with reference to the extraction result of the D / VSS line wiring parasitic element extraction step S10. In the case of the full adder shown in FIG. 15, the first NAND gate G1, the first
NAND-OR composite gate G2, second NAND-O
The waveforms of the currents flowing through the R composite gate G4 and the second NAND gate G5 overlap each other.

Next, as shown in FIG. 18C, the effective current consumption flowing through the full adder is calculated. As described above, when a static method is used to calculate the sum of the current consumption of all the logic elements, the sum is calculated including the current consumption of the logic elements that do not operate at the same time. Will be lost. In order to solve this, in the logic elements in the maximum delay path (path to be analyzed), the consumption current of the logic change when the logic element becomes the maximum delay path is set, and in the other logic elements, the circuit activation rate is set. The effective current consumption is calculated by multiplying the current consumption by the circuit activation rate Ks in the data 19.

When a test pattern for the maximum delay path is obtained, the circuit activation rate data 19 is set based on a change in the output state of each logic element at that time. Further, in the case of further simplification, the calculation may be performed using the transition probability determined by the logical function, as described in the third embodiment.

Next, as shown in FIG.
After calculating the amount of voltage drop from the current consumption flowing through the line / VSS line pair, the effective power supply voltage is calculated for each logic element as in the third embodiment, and the effective delay time corrected for the delay time Δt Is calculated. The delay time Δt can be obtained by using the voltage drop amount Vdrop in [Equation 11], the effective power supply voltage Vddeff in [Equation 12], and the effective current consumption Idgate in [Equation 13]. Note that [Equation 1
As shown in [3], the time dependence of the consumption current Idgate is
It depends on the switching period Ts of the logic element. Accordingly, the delay time Δt is corrected sequentially from the logic element having the earlier operation time, and the time dependence of the current consumption is calculated again using the corrected delay time, whereby the current consumption I
It can deal with the time dependency of dgate. In FIG. 18D, only the delay of the node u, which is the output of the first NAND gate G1, is described, but the same correction is performed for the outputs of other logic elements.

As described above, according to the present embodiment, the increase in the delay time due to the voltage fluctuation of the VDD line and the VSS line, which occurs with the miniaturization of the manufacturing process, is used to reduce the consumption current when calculating the logic level delay. It can be reliably estimated by considering dynamic changes.

Similarly, the impedance change of the power supply line having the frequency dependence due to the capacitance (C) component or the inductance (L) component connected to the VDD line and the VSS line can be similarly obtained from the time dependence of the current consumption. it can.

In this embodiment, the delay calculation is performed on the design data after the layout design is completed. However, even before the layout design, the delay calculation is performed by calculating the wiring resistance based on the estimated data from the floor plan. The increase in time can be estimated.

Further, although a building block type circuit using standard cells is assumed, a circuit such as a gate array may be used.

(Fifth Embodiment) Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.

FIG. 20 shows a fifth embodiment according to the present invention.
5 shows an operation flow of the delay calculation device in consideration of voltage fluctuations of a VDD line and a VSS line in a logic circuit.

As a feature of this embodiment, since the current consumption and the effective power supply voltage are interdependent, the calculation of the current consumption and the calculation of the voltage fluctuation of the power supply line in the delay calculator shown in the third embodiment are performed. The accuracy of the effective power supply voltage is improved by introducing a calculation loop means L14 for performing calculations recursively and a convergence condition determination means S14.

Hereinafter, the operation of the delay calculator configured as described above will be described.

Explaining only the differences from the third embodiment, in the current consumption calculating step S11, the current consumption calculating means calculates the current consumption Idd ( After performing the calculation of 0),
In the effective power supply voltage calculating step S13, the effective power supply voltage calculating means firstly calculates the effective power supply voltage Vdd in consideration of the voltage fluctuation of the VDD line and the VSS line based on the current consumption Idd (0).
Calculate (0). The current consumption Idd (1) is calculated again based on the effective power supply voltage Vdd (0), and the effective power supply voltage Vdd (1) is further calculated. Thus, the recursive consumption current I
The calculation of dd (i) (where i = 1, 2,...) and the effective power supply voltage Vdd (i) (where i = 1, 2,...) are repeated, Convergence condition determination step S14
In the above, the convergence condition determining means determines whether or not the convergence condition shown in the following determination formula [Equation 14] is satisfied.

[0160]

[Equation 14]

Here, Vdd (i) is the effective power supply voltage determined by the i-th calculation loop L14, and Vdd (i-1)
Is the effective power supply voltage determined by the (i-1) -th calculation loop L14, and δ is the upper limit of the convergence range of the effective power supply voltage, for example, a value of about 1% of the power supply voltage. If the judgment formula [Equation 14] is satisfied, the process exits the calculation loop L14,
Finally, the calculated power supply voltage Vdd (i) is converted to the effective power supply voltage Vdd.
eff.

Thereafter, in the same manner as described in the third embodiment, the processing is performed in the order of the delay calculation step S02, the delay power supply coefficient determination step S03, and the effective delay calculation step S04, and the integrated circuit to be analyzed is processed. An effective delay time can be calculated.

As described above, according to the present embodiment, since the current consumption and the effective power supply voltage of the circuits having a strong mutual dependency are calculated by forming a recursive loop, the calculation accuracy of the delay time is further improved. be able to.

(Sixth Embodiment) Hereinafter, a sixth embodiment of the present invention will be described with reference to the drawings.

FIG. 21 is a layout diagram of an integrated circuit to be analyzed by the delay calculation method and the delay calculation device in the logic circuit according to the sixth embodiment of the present invention.

The present embodiment is characterized in that from the external power supply terminal of the integrated circuit to the power supply terminal of the circuit block disposed inside the integrated circuit, and from the circuit block to the standard cell disposed inside the block. The delay time of the standard cell is calculated by hierarchically obtaining the voltage fluctuation of each power supply line up to the power supply terminal.

In FIG. 21, a first VDD terminal 71 as an external power supply terminal is connected to a first VDD line 75,
The second VDD terminal 72 is connected to a second VDD line 76, the first VSS terminal 73 is connected to a first VSS line 77, and the second VSS terminal 74 is connected to a second VSS line 78. ing. The first circuit block 91A, the second circuit block 92A, the third circuit block 93A, and the fourth circuit block 94A include a first VDD line 75, a second VDD
D line 76, first VSS line 77 and second VSS line 78
Connected to each other.

The first VDD line 75 includes a VDD power supply terminal 711 for the first block, a VDD power supply terminal 712 for the second block, a VDD power supply terminal 713 for the third block, and a VDD power supply terminal for the fourth block. 714 are provided,
The first VSS line 77 has a first block VSS power terminal 731, a second block VSS power terminal 732,
A third block VSS power terminal 733 and a fourth block VSS power terminal 734 are provided.

Similarly, the second VDD line 76 is connected to the fifth block VDD power terminal 721 and the sixth block V
A DD power supply terminal 722, a seventh block VDD power supply terminal 723, and an eighth block VDD power supply terminal 724 are provided, and the second VSS line 78 is connected to the fifth block V
An SS power terminal 741, a sixth block VSS power terminal 742, a seventh block VSS power terminal 743, and an eighth block VSS power terminal 744 are provided.

In the first circuit block 91A, the VDD line 79 in the first block and the VDD line 8 in the second block are provided.
0, a first block VSS line 81 and a second block VSS line 82 are provided. First VDD line 7
9, the second VDD line 80, the first VSS line 81 and the second
Power supply terminals (not shown) for the VSS lines 82
Standard cell 91 connected via the
1, a second standard cell 912, a third standard cell 913, a fourth standard cell 914, and the like are arranged.

Note that, like the first circuit block 91A, a plurality of standard cells are arranged in the second circuit block 92A, the third circuit block 93A, and the like.

FIG. 22A is a first equivalent circuit diagram of the integrated circuit shown in FIG. In FIG. 22A, 91B
Represents a first equivalent circuit of the first circuit block 91A, and 92B
Is the equivalent circuit of the second circuit block 92A, and 93B is the third circuit block.
The equivalent circuit of the circuit block 93A and the equivalent circuit 94B represent the equivalent circuit of the fourth circuit block 94A, respectively.
I91 is an average current consumption of the first equivalent circuit 91B of the first circuit block, and I92 is an equivalent circuit 92 of the second circuit block.
The average current consumption of B, I93 represents the average current consumption of the equivalent circuit 93B of the third circuit block, and I94 represents the average current consumption of the equivalent circuit 94B of the fourth circuit block.

FIG. 22 (b) is a second equivalent circuit diagram of the first circuit block shown in FIG. 22 (a). FIG.
21B, reference numeral 91C denotes a second equivalent circuit of the first circuit block, I911 denotes an average current consumption of the first standard cell 911 shown in FIG. 21, and I912 denotes an average current consumption of the second standard cell 912. , I 913 is the average current consumption of the third standard cell 913 and I 914 is the fourth
Mean average current consumption of the standard cell 914.

In order to calculate the delay of the signal propagation time in consideration of the voltage fluctuation of the VDD line and the VSS line in the integrated circuit configured as described above, the calculation of the current consumption and the calculation of the power supply voltage are sequentially performed in layers. It is necessary to do it.

FIG. 23 shows an operation flow of the delay calculation device in consideration of the hierarchical structure in the logic circuit according to the sixth embodiment of the present invention. 23, the description of the components shown in FIG. 20 will be omitted by retaining the same reference numerals.

As a feature of this embodiment, as shown in FIG. 23, in each step of calculating the current consumption and the effective power supply voltage, a block-level current-consumption calculating means for performing calculation for each circuit block, A chip-level current-consumption calculating means for calculating the total current consumption calculated for each circuit block by the calculating means and calculating the current consumption of the entire integrated circuit to be analyzed; a chip-level power supply based on the chip-level current consumption Chip-level VDD / VSS wiring voltage fluctuation calculating means for calculating the voltage fluctuation of the wiring, and block-level VDD / VSS for calculating the voltage fluctuation of the block-level power wiring using the voltage fluctuation of the chip-level power wiring Wiring voltage fluctuation calculation means.

Hereinafter, the calculation procedure of the current consumption and the calculation of the effective power supply voltage in the delay calculator configured as described above will be described.

As shown in FIG. 23, first, in a block-level current consumption calculation step S111, the block-level current consumption calculation means converts a power supply voltage initial value 21 which is a power supply voltage as an operation reference of an integrated circuit to be analyzed. Based on this, the current consumption for each standard cell (or logic gate) in the circuit block is calculated. For example, the block-level consumption current calculation refers to the average consumption current I 911 of the first standard cell 911 and the average consumption current of the second standard cell 912 in the first circuit block 91C in the equivalent circuit shown in FIG. This corresponds to calculating the current I912 and the like.

Next, a chip level consumption current calculation step S1
In 12, the chip level current consumption calculation means calculates the current consumption of each circuit block in the integrated circuit using the current consumption data calculated by the block level current consumption calculation means. For example, the chip-level current consumption calculation refers to calculating the average current consumption I91 of the first circuit block 91B, the average current consumption I92 of the second circuit block 92B, and the like in the equivalent circuit shown in FIG. Corresponding to

Next, in the chip-level VDD / VSS wiring voltage fluctuation calculation step S121, the chip-level fluctuation voltage calculation means uses the chip-level current consumption data to calculate the power supply terminals of the chip to the power terminals of each circuit block. Of the VDD line and the VSS line are calculated as chip-level fluctuation voltages. For example, the calculation of the fluctuation voltage at the chip level refers to the calculation of the average consumption current I91 of the first circuit block 91B and the average consumption current I92 of the second circuit block 92B in the equivalent circuit shown in FIG. This corresponds to calculating the amount of voltage fluctuation of the first VDD line 75, the first VSS line 77, and the like.

Next, in a block-level VDD / VSS wiring voltage fluctuation calculation step S122, the block-level fluctuation voltage calculating means converts each power supply terminal of the standard cell from each power supply terminal of the circuit block based on the current data of the block level. The voltage fluctuation amount as the fluctuation voltage of the block level of the VDD line and the VSS line to the terminal is calculated. For example, the calculation of the fluctuation voltage at the block level is shown in FIG.
In the equivalent circuit shown in FIG. 7, the average current consumption I of the first standard cell 911 in the first circuit block 91C is shown.
Average current consumption I of 911 and second standard cell 912
From 912 and the like, this corresponds to calculating the amount of voltage fluctuation of the VDD line 79 in the first block, the VSS line 81 in the first block, and the like.

Next, in the effective power supply voltage calculating step S13, the effective power supply voltage calculating means calculates the block-level fluctuation voltage, which is the block-level voltage fluctuation, and the chip-level fluctuation voltage, which is the chip-level voltage fluctuation. Of the standard cells 911, 912, 913, 91 by subtracting the sum of the fluctuating voltages from the power supply voltage applied to the first VDD line 75, the first VSS line 77, and the like.
4 and so on.

In the convergence condition determining step S14, the accuracy of the effective power supply voltage is improved by recursively calculating the current consumption and the effective power supply voltage, as in the fifth embodiment. .

Thereafter, the processing is performed in the order of the delay calculation step S02, the delay power supply coefficient determination step S03, and the effective delay calculation step S04, so that the effective delay time of the integrated circuit to be analyzed can be calculated.

As described above, the calculation of the current consumption and the calculation of the effective power supply voltage are performed hierarchically, so that even in a large-scale integrated circuit designed by the building block method or the like, the entire circuit (= 1 chip) can be obtained. Delay verification can be reliably realized.

In this embodiment, as described in the fourth embodiment, the calculation result of the delay calculation step S02 and the power supply (VDD / VSS) wiring parasitic element extraction step are added to the block level current consumption calculation step S111. By including a dynamic current consumption calculation step of calculating a dynamic change in current consumption based on the extraction result of S10, it is possible to more reliably estimate the amount of change in the delay time due to the voltage fluctuation of the power supply wiring. .

(Seventh Embodiment) Hereinafter, a seventh embodiment of the present invention will be described with reference to the drawings.

In this embodiment, a description will be given of a calculation method for incorporating the influence of a change in the delay time of a logic circuit due to a power supply voltage as delay data into a logic library.

FIG. 24 is a processing flow of a calculation method for obtaining delay data of a delay library according to the seventh embodiment of the present invention.

Here, in order to simplify the calculation of the delay time, it is assumed that the delay time has two components: a cell-specific delay that does not depend on the load capacity, and a dependent delay that increases depending on the load capacity. The cell delay data extracted at the reference power supply voltage Vdd0 is shown in the following formula [Equation 15].

[0191]

(Equation 15)

Here, Td0 is a signal delay time at the reference power supply voltage Vdd0, t0_0 is a delay time independent of the load capacitance, and Δt_0 is a delay time proportional to the load capacitance Cl.

Hereinafter, the calculation procedure of the power supply voltage dependence of the delay data t0_0 and Δt_0 shown in the calculation formula [Formula 15] will be described. As shown in FIG. 24, the delay data t0_0 and Δt_0 at the reference power supply voltage Vdd0 are reference power supply voltage delay data D001, and the saturation current parameter D002 that determines the drain saturation current Idspi such as carrier mobility and oxide film thickness is set in advance. It is prepared. It is assumed that the drain saturation current Ids of the P-channel MOSFET is represented by a calculation formula [Equation 4].

First, as shown in FIG. 24, in the operation power supply voltage setting step S001, the operation power supply voltage V
When ddi is given to a desired cell, an index determining step S00
In step 2, the index αi is determined according to the voltage value given to the operating power supply voltage Vddi.

Next, a drain saturation current determining step S003
After determining Idspi in accordance with the calculation formula [Equation 4], in a delayed power supply coefficient calculation step S004, a power supply voltage coefficient (= Vddi / Vdd0) which is a value of a ratio of Vddi to Vdd0 serving as a reference, and a reference for Idspi. A current coefficient (= Idsp0 / Idsp0) which is a value of a ratio to the current Idsp0
i) is calculated, and the product of the power supply voltage coefficient and the current coefficient is calculated to calculate the delayed power supply coefficient Kv.

Next, in the delay data determination step S005, the product of the reference power supply voltage delay data D0001 and the delay power supply coefficient Kv is obtained, and the delay data D003 (= t0, Δ
Determine t). These two delay data and the calculation formula [Equation 1]
Using the calculation result of [5], the delay time Td is represented by the following calculation formula [Equation 16].

[0197]

(Equation 16)

As a specific method for providing the correlation between the operating power supply voltage Vddi and the index αi, for example, a method using a table model in a table format or the like can be considered.

As described above, according to the present embodiment, the power supply of the delay data in the standard cell is performed only by applying the operating power supply voltage Vddi to the cells in the logic circuit and determining the relationship between the operating power supply voltage Vddi and the index αi. Voltage dependency can be easily and reliably calculated.

Also, as a feature of this embodiment, in the case of a multi-input gate such as a multi-bit addition cell, the delay value obtained under a certain voltage condition can be used, so that the delay data extraction time is shortened. Therefore, the development period of the cell library can be shortened.

(Eighth Embodiment) Hereinafter, an eighth embodiment of the present invention will be described with reference to the drawings.

The present embodiment is a calculation method for incorporating the effect of the change in the delay time of the logic circuit due to the power supply voltage into the logic library as delay data.
A method of obtaining the power supply voltage dependency for each of the rise delay time and the fall delay time will be described.

In the logic circuit, when the output load impedance is large, the ratio of the delay for driving the output node to the delay for driving the internal node of the cell becomes large. The cell delay in the logic circuit includes a rising delay in which the output node is driven by a P-channel MOSFET and the output potential rises from the ground voltage Vss to the power supply voltage Vdd, and a rising delay in which the output node is driven by the N-channel MOSFET and the output potential is There is a fall delay from Vdd to ground voltage Vss.

In this embodiment, a P-channel MOS
Since the FET and the N-channel MOSFET have different power supply voltage dependencies of the drain current, a delay power supply coefficient for a rise delay and a delay power supply coefficient for a fall delay are individually provided.

FIG. 25 is a processing flow of a calculation method for obtaining delay data of a delay library according to the eighth embodiment of the present invention.

Here, in order to simplify the calculation of the delay time, the delay time is calculated by using the same format as that shown in the equation (15), so that the delay time is independent of the load capacity and the rising cell-specific delay. It is assumed that there are four components: a falling intrinsic delay, and a rising dependent delay and a falling dependent delay that increase depending on the load capacity. Reference power supply voltage Vdd
The rising cell delay data extracted by “0” is shown in a calculation equation [Equation 17], and the falling cell delay data is shown in a calculation equation [Equation 18].

[0207]

[Equation 17]

[0208]

(Equation 18)

Here, Tdr0 is a signal delay time at the reference power supply voltage Vdd0, and tr0_0 is a load capacitance Cl.
Δtr_0 is a rise delay time proportional to the load capacitance Cl, Tdf0 is a fall delay time of a signal at the reference power supply voltage Vdd0, tf0_0
Is the fall delay time independent of the load capacitance Cl, Δt
f_0 is a fall delay time proportional to the load capacitance Cl.

Hereinafter, a description will be given of a calculation procedure of the power supply voltage dependency between the rising delay data tr0_0 and Δtr_0 shown in the equation [Equation 17] and the falling delay data tf0_0 and Δtf_0 shown in the equation [Equation 18]. For simplicity, only components different from those in FIG. 24 will be described, and in FIG. 25, the same components as those shown in FIG. 24 will be denoted by the same reference numerals and description thereof will be omitted. Reference power supply voltage V
The rising delay data tr0_0, Δtr_0 and the falling delay data tf0_0, Δtf_0 at dd0 are prepared in advance as reference power supply voltage delay data D011. Note that a P-channel MOSFET and an N-channel MO
It is assumed that the drain saturation current Ids of the SFET is represented by a calculation formula [Equation 4].

First, as shown in FIG. 25, in the operation power supply voltage setting step S001, the operation power supply voltage V
When ddi is given to a desired cell, an index determining step S01
In step 2, the index αni of the N-channel MOSFET and the index αpi of the P-channel MOSFET are determined in accordance with the voltage value given to the operating power supply voltage Vddi.

Next, a drain saturation current determining step S013
In accordance with the formula [Equation 4], the N-channel MOS
FET drain saturation current Idsni and P-channel MOSF
The drain saturation current Idspi of the ET is determined.

Next, in a delayed power supply coefficient calculation step S014, a power supply voltage coefficient (= Vddi / Vdd0) which is a value of a ratio of Vddi to Vdd0 as a reference, and a P-channel MO
A first current coefficient (= Idsp0) which is a value of a ratio of a drain saturation current Idspi of the SFET to a reference current Idsp0.
/ Idspi), and calculates the product of the power supply voltage coefficient and the first current coefficient to calculate the rise delay power supply coefficient Kvp. Similarly, a second current coefficient (= Idsn0 / Idsni), which is a value of a ratio of a reference current Idsn0 to a drain saturation current Idsni of the N-channel MOSFET, is calculated, and a power supply voltage coefficient and a second current coefficient are calculated. The product is calculated to calculate the falling delay power supply coefficient Kvn.

Next, in the delay data determination step S015, tr0_0, tr0_0,
The product of Δtr — 0 and the rise delay power supply coefficient Kvp is obtained to determine rise delay data D013 (= tr0, Δtr). Similarly, tf0_0 and Δtf_0 in the reference power supply voltage delay data D011 and the falling delay power supply coefficient Kvn
And the falling delay data D014 (= t
f0, Δtf). As shown in the calculation formula [Equation 19], the rise delay time Tdr is expressed using these two rise delay data and the calculation result of the calculation formula [Equation 17]. As shown, the fall delay time Tdf is represented by using two fall delay data and the calculation result of Expression [18].

[0215]

[Equation 19]

[0216]

(Equation 20)

The operating power supply voltage Vddi and each index αpi,
As a specific method of providing a correlation with αni, for example,
A method using a tabular table model or the like is conceivable.

As described above, according to the present embodiment, the operation power supply voltage Vddi is applied to the cells in the logic circuit, and the relationship between the operation power supply voltage Vddi and each of the indices αpi and αni is obtained. Power supply voltage dependence of data can be easily and reliably calculated.

Further, since the rising delay data and the falling delay data are individually calculated as the delay data in the standard cell, the power supply voltage dependence of the delay data can be expressed in more detail, so that the accuracy of the delay data can be further improved. Can be improved.

Also, as a feature of this embodiment, in the case of a multi-input gate such as a multi-bit addition cell, the delay value obtained under a certain voltage condition can be used, so that the delay data extraction time is shortened. Therefore, the development period of the cell library can be shortened.

[0221]

According to the delay calculation method of the first logic circuit according to the present invention, a power supply voltage coefficient consisting of a value of a ratio of the second power supply voltage to the first power supply voltage is obtained. A current coefficient consisting of a value of a ratio of a drain saturation current of the FET when the first power supply voltage is applied to a drain saturation current of the FET when the voltage is applied is obtained, and a logic when the first power supply voltage is applied is obtained. A product of the delay time of the circuit, the power supply voltage coefficient, and the current coefficient is calculated, and the calculation result is referred to as a second delay time of the logic circuit when the second power supply voltage is applied.
When the relationship between the power supply voltage and the drain saturation current of the FET is determined in order to obtain the delay time, the dependency of the delay time of the logic circuit on the power supply voltage is calculated using the delay data extracted from the cell library at the first power supply voltage. Can be easily and analytically determined.

According to the second delay calculation method for a logic circuit according to the present invention, a power supply voltage coefficient consisting of a value of a ratio of a power supply voltage for each circuit block to a reference power supply voltage is obtained, and a power supply voltage for each circuit block is applied. F when done
A current coefficient consisting of a value of a ratio of a drain saturation current of the FET when the reference power supply voltage is applied to a drain saturation current of the ET is obtained, and each of the delay times of the circuit block when the reference power supply voltage is applied is calculated. The power supply voltage coefficient and the current coefficient corresponding to the circuit blocks are multiplied to calculate the delay time when the power supply voltage is applied to each circuit block, so that the power supply voltage for each circuit block and the drain saturation current of the FET are calculated. When the relationship is determined, it is possible to easily and analytically determine the power supply voltage dependence of the delay time for each of the plurality of circuit blocks provided with the logic circuit using the delay data extracted from the cell library at the reference power supply voltage. Can be.

According to the third delay calculation method of the logic circuit according to the present invention, a power supply voltage coefficient consisting of a value of a ratio of an effective power supply voltage reflecting a voltage variation with respect to a reference power supply voltage is obtained, and the effective power supply voltage is applied. The current coefficient consisting of the value of the ratio of the drain saturation current of the FET when the reference power supply voltage is applied to the drain saturation current of the FET when the reference power supply voltage is applied is calculated as the delay time of the circuit block when the reference power supply voltage is applied. By multiplying the power supply voltage coefficient and the current coefficient when the effective power supply voltage is applied, the delay time when the effective power supply voltage is applied is calculated, so that the effective power supply voltage reflecting the voltage fluctuation amount is calculated. Once the relationship with the FET drain saturation current is determined, the effective power supply voltage of the logic circuit is applied using the delay data extracted from the cell library at the reference power supply voltage. The power supply voltage dependency of the delay time easily and can be determined analytically when the.

In the third logic circuit delay calculation method,
The current consumption of the logic circuit is defined as the sum of the current consumption of the specific logic elements operating together at one operation time among the plurality of logic elements, and the specific logic element is connected based on the sum of the current consumption. If the voltage fluctuation of the power supply line is calculated and the voltage fluctuation of the power supply line is regarded as the fluctuation voltage, the delay time considering the dynamic voltage fluctuation of the power supply line due to the time change of the current consumption can be easily and analytically calculated. You can ask.

In the first to third logic circuit delay calculation methods, if the FET is a P-channel MOSFET, the power supply voltage dependence of the drain saturation current is reduced by the P-channel MOSFET.
Is larger than that of the N-channel MOSFET, the power supply voltage dependence of the delay time substantially matches the value of the power supply voltage to drain saturation current value, and thus the power supply voltage dependence of the delay time when the power supply voltage is applied. Can be reliably obtained.

In the first to third logic circuit delay calculation methods, a value obtained by raising the drain saturation current of the FET to the power of the difference between the power supply voltage and the threshold voltage of the FET by a predetermined coefficient and raising the power to the power Is multiplied by the current gain coefficient, the drain saturation current of the FET can be reliably obtained.

According to the delay calculation device for the first logic circuit of the present invention, the power supply voltage coefficient consisting of the value of the ratio of the second power supply voltage to the first power supply voltage is obtained, and the second power supply voltage is applied. Delay power coefficient determining means for obtaining a current coefficient comprising a value of a ratio of the drain saturation current of the FET when the first power supply voltage is applied to the drain saturation current of the FET when the first power supply voltage is applied. Delay calculating means for calculating the delay time of the logic circuit when the delay is calculated, and calculating the product of the delay time calculated by the delay calculating means, the power supply voltage coefficient, and the current coefficient, and calculating the second power supply voltage Since there is provided an effective delay calculating means for calculating an effective delay time of the logic circuit when the voltage is applied, when the relationship between the power supply voltage and the drain saturation current of the FET is determined, the first value is obtained from the cell library.
The power supply voltage dependence of the delay time of the logic circuit can be easily and analytically determined using the delay data extracted with the power supply voltage of (1).

In the first logic circuit delay calculating device,
Means for determining a power supply voltage coefficient for each block that defines a value of a ratio of a power supply voltage of each circuit block to a reference power supply voltage, and an FE when the power supply voltage of each circuit block is applied
Means for determining a current coefficient for each block that defines a value of a ratio of a drain saturation current of the FET when a reference power supply voltage is applied to a drain saturation current of T,
If the relationship between the power supply voltage for each circuit block and the drain saturation current of the FET is determined, the delay time for each of the plurality of circuit blocks provided with the logic circuit is determined using the delay data extracted from the cell library at the reference power supply voltage. Can be easily and analytically determined.

According to the second logic circuit delay calculator of the present invention, the voltage fluctuation of the power supply wiring is calculated from the current consumption and the wiring parasitic element of the power supply wiring, and the power supply voltage applied to the power supply terminal and the voltage fluctuation are calculated. Effective power supply voltage calculating means for calculating an effective power supply voltage which is an effective power supply voltage by determining a difference from the potential of the power supply, and a power supply voltage coefficient which is a value of a ratio of the effective power supply voltage to the power supply voltage. Delay power coefficient determining means for determining a current coefficient which is a value of a ratio of a drain saturation current of the FET when a power supply voltage is applied to a drain saturation current of the FET when an effective power supply voltage is applied; Delay calculation means for calculating a delay time when a power supply voltage is applied from the delay data of the element and the logic element, and a product of the delay time calculated by the delay calculation means, a power supply voltage coefficient and a current coefficient Calculated, since a effective delay calculating means for the effective delay time of the logic circuit results output the calculated, effective power supply voltage and the FET which is the amount of voltage change is reflected
Is determined by using the delay data extracted from the cell library at the reference power supply voltage, and the power supply voltage dependence of the delay time when the effective power supply voltage of the logic circuit is applied. Can be easily and analytically determined.

In the delay calculation device for the second logic circuit,
Current consumption calculating means for calculating a sum of current consumption for each of a plurality of logic elements operating together at one operation time, and an effective power supply voltage calculating means for calculating a sum of the current consumption and a power supply The voltage variation of the power supply wiring to which the specific logic element is connected is calculated using the wiring parasitic element of the wiring, and the delayed power supply coefficient determining means sequentially determines the logic By calculating the power supply voltage coefficient and the current coefficient for each logic element using the effective power supply voltage applied to the logic element, it is possible to easily set the delay time in consideration of the dynamic voltage fluctuation of the power supply wiring due to the time change of the current consumption. And it can be obtained analytically.

In the delay calculation device for the second logic circuit,
The current consumption calculating means has a block level current consumption calculating means for calculating the current consumption of the circuit block, and a chip level current consumption calculating means for calculating the current consumption of the integrated circuit from the current consumption of the circuit block. The power supply voltage calculation means includes a chip level effective power supply voltage calculation means for calculating a chip level effective power supply voltage and a block level effective power supply voltage calculation means for calculating a block level effective power supply voltage. When the effective delay time of the integrated circuit is calculated based on the power supply voltage, large-scale integration is performed by sequentially calculating the current consumption and the effective power supply voltage hierarchically at a chip level, a block level, and a cell level. The delay time can be reliably obtained in the circuit.

In the delay calculation device for the second logic circuit,
The current consumption calculation means is configured to output
Calculate the sum of the current consumption of each specific standard cell operating together at one operation time, determine the current consumption of the standard cell, and specify the current consumption of the standard cell and the wiring parasitic capacitance of the power supply wiring. Of the power supply wiring to which the standard cell is connected, the delay power coefficient determining means calculates the effective power supply voltage applied to the logic element in order from the logic element having the earlier operation time among the plurality of logic elements. When the power supply voltage coefficient and the current coefficient are calculated for each standard cell, the delay time can be easily and analytically determined in consideration of the dynamic voltage fluctuation of the power supply wiring due to the time change of the current consumption.

In the delay calculation device for the second logic circuit,
The current consumption calculating means has switching frequency data giving means for giving a switching frequency for each node of the connection information, and calculates the current consumption of the integrated circuit from the switching frequency, the current consumption data of the parasitic element of the signal wiring and the standard cell. Since the switching frequency does not depend on the parasitic element of the wiring or the current data of the cell library, the switching frequency can be calculated without information such as the load capacitance of the actual wiring and the resistance capacitance of the actual wiring. For this reason, even if the manufacturing process is changed, operating conditions such as operating frequency and power supply voltage are changed, or even if the layout shape is changed as in the case of the soft macro library, the test pattern must be reassigned. Since there is no need to re-simulate the current consumption, the number of integrated circuit development steps is reduced.

In the delay calculation device for the second logic circuit,
Consumption current calculation means calculates a transition probability of a logical value that transitions from one logical value to another logical value using a logical function included in the connection information, and calculates a transition probability, a parasitic element of a signal wiring, and a consumption of a standard cell. When the current consumption of the integrated circuit is calculated using the current data, when the manufacturing process is changed, when the operating conditions such as the operating frequency and the power supply voltage are changed, and when the layout shape is changed like a soft macro library Even if there is, there is no need to re-provide the test pattern and re-simulate the current consumption, so that the man-hour for developing the integrated circuit is reduced.

In the delay calculation device for the second logic circuit,
It is determined whether or not the difference between the current calculation result of the effective power supply voltage calculation means and the stored calculation result falls within a predetermined range. If the convergence condition determining means for repeating the power supply voltage calculating means is provided, since the current consumption and the effective power supply voltage of the circuits having a strong mutual dependency are calculated in a recursive loop, the calculation accuracy of the delay time is calculated. Can be further improved.

In the delay calculation device of the first or second logic circuit, if the FET is a P-channel MOSFET, the power supply voltage dependence of the drain saturation current is a P-channel MOSFET.
Since ET is larger than N-channel MOSFET,
The power supply voltage dependency of the delay time substantially matches the value of the ratio of the power supply voltage to the drain saturation current. This makes it possible to reliably determine the power supply voltage dependency of the delay time when the power supply voltage is applied.

In the delay calculating device for the first or second logic circuit, the drain saturation current of the FET is determined by the power supply voltage and the FE.
If the difference between T and the threshold voltage is raised to a power by a predetermined coefficient and the value obtained by raising the power is multiplied by the gain coefficient of the current, the drain saturation current of the FET is reliably calculated.

According to the first method for calculating delay data of the delay library according to the present invention, the second
And a power supply voltage coefficient defining step of defining a power supply voltage coefficient which is a value of a power supply voltage ratio of the power supply voltage when the first power supply voltage is applied to the drain saturation current of the FET when the second power supply voltage is applied. A current coefficient defining step of defining a current coefficient which is a value of a ratio of a drain saturation current of the FET; and a first coefficient defining a first delay time which is a delay time of a logic circuit when a first power supply voltage is applied. Calculating the product of the first delay time, the power supply voltage coefficient, and the current coefficient to obtain a second delay which is a delay time of the logic circuit when the second power supply voltage is applied. Determine the time, the second
And determining the relationship between the power supply voltage and the drain saturation current of the FET by using the delay data extracted from the cell library at the first power supply voltage. Thus, the power supply voltage dependency of the delay time of the logic circuit can be easily and analytically obtained. For this reason, the extraction time of the delay data can be reduced, so that the cell library can be developed in a short time.

In the delay data calculation method of the first delay library, when the FET is a P-channel MOSFET, the power supply voltage dependence of the drain saturation current is equal to the P-channel M
Since the OSFET is larger than the N-channel MOSFET, the dependency of the delay time on the power supply voltage substantially matches the value of the ratio of the power supply voltage to the drain saturation current. This allows
The power supply voltage dependency of the delay time when the power supply voltage is applied can be reliably obtained.

In the first delay data calculation method of the delay library, the drain saturation current of the FET is raised to a value obtained by raising the difference between the power supply voltage and the threshold voltage of the FET to a power by a predetermined coefficient, and raising the power. When the current is multiplied by the gain coefficient of the current, the drain saturation current of the FET can be reliably obtained.

According to the second delay data calculation method of the present invention, the effect of the first delay library delay data calculation method can be obtained, and the P-channel MO
Regarding the rise delay that occurs when driving the SFET,
By calculating a product of a first rise delay time caused by the first power supply voltage, a power supply voltage coefficient, and a first current coefficient, a rise delay time of the logic circuit when the second power supply voltage is applied And the second rise delay time is determined as rise delay data. On the other hand, regarding the fall delay generated when the N-channel MOSFET is driven, the first rise delay caused by the first power supply voltage is determined. Calculates the product of the fall delay time of the power supply voltage coefficient and the second current coefficient to obtain a second fall delay which is a fall delay time of the logic circuit when the second power supply voltage is applied. The time is determined, and the second fall delay time is obtained as fall delay data. As a result, since the delay data can be individually obtained as the rising delay data and the falling delay data, a more detailed delay library can be created, and the accuracy of the delay library is improved.

In the second method for calculating delay data of a delay library, a P-channel MOSFET and an N-channel M
The drain saturation current of each OSFET is determined by comparing the power supply voltage with each MO.
When the difference from the threshold voltage of the SFET is raised to a power by a predetermined coefficient, and the value obtained by raising the power is multiplied by the current gain coefficient, the drain saturation current of each MOSFET is reliably obtained. Can be.

[Brief description of the drawings]

FIG. 1 is a graph showing power supply voltage dependence of a delay time of a basic CMOS gate according to the present invention.

FIG. 2 is a graph showing the power supply voltage dependence of the delay time of a circuit block equivalent to 3000 gates and a 4 KB static RAM circuit according to the present invention.

FIG. 3 is a diagram showing an operation flow of the logic circuit delay calculation device according to the first embodiment of the present invention.

FIG. 4 is an operation flowchart for determining a delay power supply coefficient in the delay calculation device for a logic circuit according to the first embodiment of the present invention.

FIG. 5 is an operation flow chart for determining a delay power supply coefficient in the logic circuit delay calculator according to the first embodiment of the present invention.

FIG. 6 is a configuration diagram of an integrated circuit to be subjected to delay calculation by a delay calculation device for a logic circuit according to a second embodiment of the present invention;

FIG. 7 is a diagram illustrating an operation flow of a delay calculation device for a logic circuit according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram of an integrated circuit to be subjected to delay calculation by a delay calculation device for a logic circuit according to a third embodiment of the present invention.

FIG. 9 is a first equivalent circuit diagram of an integrated circuit whose delay calculation is to be performed by the delay calculation device for a logic circuit according to the third embodiment of the present invention;

FIG. 10 is a second equivalent circuit diagram of an integrated circuit whose delay is to be calculated by the delay calculation device for a logic circuit according to the third embodiment of the present invention;

FIG. 11A is a layout diagram of an integrated circuit to be subjected to delay calculation by a delay calculation device for a logic circuit according to a third embodiment of the present invention. (B) is an equivalent circuit diagram of an integrated circuit whose delay calculation is to be performed by the logic circuit delay calculator according to the third embodiment of the present invention.

FIG. 12 is a graph showing a relationship between a wiring width of a VDD line and a VSS line and an effective power supply voltage according to a third embodiment of the present invention.

FIG. 13 is a graph showing a relationship between a wiring width of a VDD line and a VSS line and a relative value of delay time according to a third embodiment of the present invention.

FIG. 14 is a diagram illustrating an operation flow of the delay calculation device for a logic circuit according to the third embodiment of the present invention.

FIG. 15A is a circuit diagram illustrating a full adder which is an example of a logic circuit according to a third embodiment of the present invention. (B)
And (c) is a diagram showing a truth table of a full adder which is an example of a logic circuit according to the third embodiment of the present invention.

FIG. 16 is a diagram illustrating an operation flow of the delay calculation device for a logic circuit according to the fourth embodiment of the present invention.

FIG. 17 is a diagram showing a detailed flow of calculating a dynamic current consumption in the delay calculation device for a logic circuit according to the fourth embodiment of the present invention.

FIG. 18 is a diagram illustrating a method for calculating current consumption of a logic element and a method for correcting a delay time in a delay calculation device for a logic circuit according to a fourth embodiment of the present invention.

FIG. 19A is a diagram illustrating an example of cell consumption current data in a delay calculation device for a logic circuit according to a fourth embodiment of the present invention. (B) is a diagram showing a cell consumption current waveform in the delay calculation device for a logic circuit according to the fourth embodiment of the present invention.

FIG. 20 is a diagram showing an operation flow of the logic circuit delay calculation device according to the fifth embodiment of the present invention.

FIG. 21 is a layout diagram of an integrated circuit to be subjected to delay calculation by a delay calculation device for a logic circuit according to a sixth embodiment of the present invention;

FIG. 22 is an equivalent circuit diagram of an integrated circuit whose delay calculation is to be performed by the delay calculation device for a logic circuit according to the sixth embodiment of the present invention;

FIG. 23 is a diagram illustrating an operation flow of the delay calculation device for a logic circuit according to the sixth embodiment of the present invention.

FIG. 24 is a flowchart illustrating a method of calculating delay data of a delay library according to a seventh embodiment of the present invention.

FIG. 25 is a flowchart showing a method of calculating delay data of a delay library according to the eighth embodiment of the present invention.

[Explanation of symbols]

1 2-input NAND gate 2 2-input NOR gate 3 4-input NAND gate 4 4-input NOR gate 5 Ratio of power supply voltage to drain saturation current of P-channel MOSFET 6 Ratio of power supply voltage to drain saturation current of N-channel MOSFET 7 Logic block 8 Static RAM 9 Ratio of power supply voltage to drain saturation current of P-channel MOSFET 10 Ratio of power supply voltage to drain saturation current of N-channel MOSFET 11 Layout data 12 Wiring parameters 13 Circuit connection information 14 Cell delay data 15 Operating power supply voltage data 16 Saturation current Parameter 17 Circuit block operation power supply voltage data 18 Layout data 19 Circuit activation rate data 20 Cell current consumption data 21 Power supply voltage initial value S01 Signal wiring extraction step S10 Power supply (V D / VSS) wiring parasitic element extraction step S11 current consumption calculation step S200 dynamic current consumption calculation step S201 circuit delay determination step S202 VDD line consumption current waveform calculation step S203 VSS line consumption current waveform calculation step S204 Effective current consumption calculation step S111 block Level consumption current calculation step S112 Chip level consumption current calculation step S12 Power supply (VDD / VSS) wiring voltage fluctuation calculation step S121 Chip level VDD / VSS wiring voltage fluctuation calculation step S122 Block level VDD / VSS wiring voltage fluctuation calculation step S13 Effective power supply voltage Calculation step S14 Convergence condition determination step L14 Calculation loop means S02 Delay calculation step S03 Delay power supply coefficient determination step S03A Delay power supply coefficient determination step S31 Operating power supply voltage determination step S32 Index determination step S33A Drain Sum current determination step S33B Drain saturation current determination step S34 Delay power supply coefficient determination step S04 Effective delay calculation step 50 Integrated circuit 50a Circuit block 50b High-speed operation circuit block 50c Low power consumption circuit block 50d Input / output circuit block 51 First VDD terminal 52 2nd VDD terminal 53 1st VSS terminal 54 2nd VSS terminal 55 1st VDD line 56 2nd VDD line 57 1st VSS line 58 2nd VSS line 61 1st circuit block 62 2nd Circuit block 63 third circuit block 64 fourth circuit block I61 average current consumption of the first circuit block I62 average current consumption of the second circuit block I63 average current consumption of the third circuit block I64 fourth circuit Average current consumption of block G1 First NAND gate G2 First NAND-O Composite gate G3 EX-NOR gate G4 Second NAND-OR composite gate G5 Second NAND gate G6 Third NAND gate a node b node ci node co node (intermediate carry) s node (intermediate sum) u node v Node w node x node 71 first VDD terminal 711 first VDD terminal for block 712 second VDD terminal for block 713 third VDD terminal for block 714 fourth VDD terminal for block 72 second VDD terminal 721 Fifth block VDD terminal 722 Sixth block VDD terminal 723 Seventh block VDD terminal 724 Eighth block VDD terminal 73 First VSS terminal 731 First block VDD terminal 732 Second block VDD terminal 733 for third block VDD terminal 7 for third block 4 Fourth Block VDD Terminal 74 Second VSS Terminal 741 Fifth Block VDD Terminal 742 Sixth Block VDD Terminal 743 Seventh Block VDD Terminal 744 Eighth Block VDD Terminal 75 First VDD line 76 Second VDD line 77 First VSS line 78 Second VSS line 79 VDD line inside first block 80 VDD line inside second block 81 VDD line inside first block 82 Inside second block VDD line 91A First circuit block 911 First standard cell 912 Second standard cell 913 Third standard cell 914 Fourth standard cell 91B First equivalent circuit of first circuit block 91C First circuit block Second equivalent circuit 92A Second circuit block 92B Equivalent circuit of second circuit block 3A Third circuit block 93B Equivalent circuit of third circuit block 94A Fourth circuit block 94B Equivalent circuit of fourth circuit block I91 Average current consumption of first equivalent circuit of first circuit block I92 Second Average current consumption of equivalent circuit of circuit block I93 Average current consumption of equivalent circuit of third circuit block I94 Average current consumption of equivalent circuit of fourth circuit block I911 Average current consumption of first standard cell I912 Second standard Average current consumption of cell I913 Average current consumption of third standard cell I914 Average current consumption of fourth standard cell 171A 5mA curve 172A 10mA curve 173A 15mA curve 174A 20mA curve 171B 5mA curve 172B 10mA curve 173B Curve of 15 mA 174B Curve of 20 mA D00 1 Reference power supply voltage delay data D011 Reference power supply voltage delay data D002 Saturation current parameter D003 Delay data D013 Rising delay data D014 Falling delay data S001 Operating power supply voltage setting step S002 Index determination step S012 Index determination step S003 Drain saturation current determination step S013 Drain Saturation current determination step S004 Delay power supply coefficient calculation step S014 Delay power supply coefficient calculation step S005 Delay data determination step S015 Delay data determination step

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-239865 (JP, A) JP-A-6-124318 (JP, A) JP-A-9-54798 (JP, A) JP-A 9-54 147005 (JP, A) JP-A-11-3366 (JP, A) JP-A 9-160956 (JP, A) JP-A 8-77240 (JP, A) JP-A 5-303604 (JP, A) JP-A-5-101131 (JP, A) JP-A-5-40801 (JP, A) Table 9-511597 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50 JICST file (JOIS)

Claims (22)

(57) [Claims] 1. A method for calculating a delay in a signal propagation time due to a power supply voltage of a logic circuit when performing a simulation of a logic circuit including a plurality of logic elements including an FET, the method comprising: The value of the ratio of the second power supply voltage to the power supply voltage is a power supply voltage coefficient. When the first power supply voltage is applied to the drain saturation current of the FET when the second power supply voltage is applied. The value of the ratio of the drain saturation current of the FET as a current coefficient, a first delay time which is a delay time of the logic circuit when the first power supply voltage is applied, the power supply voltage coefficient and the current coefficient And calculating the product as a second delay time which is a delay time of the logic circuit when the second power supply voltage is applied. 2. A delay of a signal propagation time due to each effective power supply voltage of a plurality of circuit blocks which constitute one logic circuit, each of which comprises a plurality of logic elements including FETs, and which operates at mutually different effective power supply voltages. Calculating a power supply voltage coefficient which is a value of a ratio of a power supply voltage of each circuit block to a reference power supply voltage, and when an effective power supply voltage of each circuit block is applied. Calculating a current coefficient that is a value of a ratio of a drain saturation current of the FET when the reference power supply voltage is applied to a drain saturation current of the FET; and the respective circuit blocks when the reference power supply voltage is applied. The product of the reference delay time, which is the delay time of the above, and the power supply voltage coefficient and the current coefficient for each of the circuit blocks is calculated, and the calculation result is calculated for each time. A delay calculation method for a logic circuit, wherein an effective delay time is a delay time of a road block. 3. A delay calculation method for a logic circuit, comprising: calculating a delay of a signal propagation time due to a voltage change of a power supply voltage of the logic circuit when performing a simulation of a logic circuit including a plurality of logic elements including an FET. Calculating a fluctuation voltage due to a current consumption of the logic circuit and a voltage fluctuation caused by a wiring parasitic element of a power supply line, and calculating a difference between a reference power supply voltage applied to a power supply terminal and the fluctuation voltage, thereby obtaining the logic circuit An effective power supply voltage that is an effective power supply voltage applied to the reference power supply voltage is calculated, and a power supply voltage coefficient that is a value of a ratio of the effective power supply voltage to the reference power supply voltage is calculated. A current coefficient which is a value of a ratio of a drain saturation current of the FET when the reference power supply voltage is applied to a drain saturation current of the FET is calculated. A product of the delay time serving as a reference of the logic circuit calculated based on the reference power supply voltage, the power supply voltage coefficient, and the current coefficient is calculated, and the calculation result is obtained when the effective power supply voltage is applied. A delay calculation method for a logic circuit, wherein the delay time is an effective delay time which is a delay time of the logic circuit. 4. The current consumption of the logic circuit is defined as the sum of the current consumption of each of the specific logic elements operating together at one operation time among the plurality of logic elements, based on the sum of the current consumption. The delay time calculation method according to claim 3, wherein a voltage fluctuation amount of a power supply line to which the specific logic element is connected is calculated, and the voltage fluctuation amount of the power supply line is set as the fluctuation voltage. 5. The method according to claim 1, wherein the FET is a P-channel MOSFET. 6. The drain saturation current of the FET is raised by raising a difference between a power supply voltage and a threshold voltage of the FET by a predetermined coefficient, and multiplying a value obtained by raising the power to a current gain coefficient. The method according to claim 1, wherein the delay is calculated. 7. A delay calculating apparatus for a logic circuit, which calculates a delay of a signal propagation time due to a power supply voltage of the logic circuit when performing a simulation of a logic circuit including a plurality of logic elements including FETs, Layout data providing means for providing layout data for determining the arrangement of elements in the logic circuit; connection information providing means for providing connection information for the logic circuit; and determining wiring of the logic circuit and electrical characteristics of the logic element. A process parameter providing unit for providing process information to be performed, a library data providing unit for providing delay data of the logic element, and a power supply voltage coefficient which is a value of a ratio of the second power supply voltage to the first power supply voltage. And the first power supply with respect to the drain saturation current of the FET when the second power supply voltage is applied. A delay power supply coefficient determining unit that determines a current coefficient that is a value of a ratio of a drain saturation current of the FET when a voltage is applied, based on the delay data, the layout data, the process information, and the connection information, A delay calculating means for calculating a delay time of the logic circuit when the first power supply voltage is applied; and calculating a product of the delay time calculated by the delay calculating means, the power supply voltage coefficient, and the current coefficient. An effective delay calculating means for setting the calculation result as an effective delay time of the logic circuit when the second power supply voltage is applied. 8. The logic circuit operates with different power supply voltages from each other and includes a plurality of circuit blocks constituting one logic circuit, and power supply voltage information for giving each power supply voltage information of the logic circuit and the circuit block. The delay power supply coefficient determining means further includes: a power supply voltage coefficient for each block that defines a value of a ratio of a power supply voltage of each circuit block to a reference power supply voltage; and a power supply voltage of each circuit block. Means for determining a block-by-block current coefficient that defines a value of a ratio of a drain saturation current of the FET when the reference power supply voltage is applied to a drain saturation current of the FET when the FET is applied. The delay calculation device for a logic circuit according to claim 7, wherein: 9. A delay calculation device for a logic circuit, which calculates a delay of a signal propagation time due to a voltage change of a power supply voltage of the logic circuit when performing a simulation of a logic circuit including a plurality of logic elements including an FET. Layout data providing means for providing layout data for determining the arrangement of the logic element in the logic circuit; connection information providing means for providing connection information for the logic circuit; wiring of the logic circuit and electricity of the logic element A process parameter assigning unit for assigning process information for determining characteristics; a library data assigning unit for assigning delay data and current consumption data of the logic element; and extracting a parasitic element of a signal wiring using the layout data and the process parameter. Signal wiring extracting means, and the layout data and process parameters Power line parasitic element extracting means for extracting a line parasitic element of a power line to which a power terminal and the logic circuit are connected by using a power source terminal, and a logic element of the logic circuit using the parasitic element of the signal line and current consumption data. Current consumption calculating means for calculating current consumption; calculating a voltage variation of the power supply wiring using the current consumption and a wiring parasitic element of the power supply wiring; and calculating a power supply voltage applied to the power supply terminal and the voltage fluctuation. An effective power supply voltage calculating means for calculating an effective power supply voltage that is an effective power supply voltage by obtaining a difference from the voltage corresponding to the amount; and a power supply voltage coefficient being a value of a ratio of the effective power supply voltage to the power supply voltage. And a current coefficient that is a value of a ratio of a drain saturation current of the FET when the power supply voltage is applied to a drain saturation current of the FET when the effective power supply voltage is applied. Delay power coefficient determining means for determining, a delay element when the power supply voltage is applied using a parasitic element of the signal line and the delay data of the logic element, and the delay calculating means Calculating a product of the calculated delay time, the power supply voltage coefficient, and the current coefficient, and using the calculation result as an effective delay time of the logic circuit. Circuit delay calculator. 10. The effective power supply voltage calculation means, wherein the current consumption calculation means calculates a sum of current consumption of each of the plurality of logic elements, which is operated together with one operation time, for each specific logic element. Calculating a voltage fluctuation amount of a power supply line to which the specific logic element is connected, using a sum of the current consumption and a wiring parasitic element of the power supply line; The power supply voltage coefficient and the current coefficient are calculated for each logic element by using an effective power supply voltage applied to the logic element in order from a logic element having an earlier operation time among the elements. The delay time calculation device according to the above. 11. The integrated circuit comprising at least one circuit block each having at least one standard cell, wherein the integrated circuit is provided with an external power supply terminal to which a power supply voltage is applied, The at least one circuit block includes a block power terminal connected to the external power terminal and to which a voltage for driving the circuit block is applied. The at least one standard cell includes the block power terminal. A power supply terminal for a cell, to which a voltage for driving the standard cell is applied, wherein the current consumption calculating means uses a parasitic element of the signal line and current consumption data of the standard cell. Block level current consumption calculating means for calculating current consumption of a circuit block; Chip level current consumption calculating means for calculating the current consumption of the integrated circuit using the current consumption of the integrated circuit, wherein the effective power supply voltage calculating means uses the current consumption of the circuit block from the external power supply terminal. A chip-level fluctuation voltage calculating means for calculating a chip-level fluctuation voltage that is a voltage fluctuation amount of the power supply wiring up to the block power supply terminal; and a power supply voltage applied to the external power supply terminal and the chip-level fluctuation voltage. A chip level effective power supply voltage calculating means for calculating a chip level effective power supply voltage by calculating a difference; and a voltage variation from the block power supply terminal to the cell power supply terminal based on the current consumption data of the standard cell. A block-level fluctuation voltage calculating means for calculating a block-level fluctuation voltage, which is a quantity, Block level effective power supply voltage calculating means for calculating a block level effective power supply voltage by calculating a difference between a voltage and the block level fluctuation voltage; and the integrated circuit based on the block level effective power supply voltage. 10. The delay calculation device for a logic circuit according to claim 9, wherein the effective delay time is calculated. 12. The current consumption calculating means calculates the sum of the current consumption of each of a plurality of standard cells, the current consumption of each specific standard cell operating together at one operation time, and calculating the current consumption of the standard cell. Calculating a voltage fluctuation amount of a power supply line to which the specific standard cell is connected, using a current consumption of the standard cell and a wiring parasitic capacitance of the power supply line; 12. The power supply voltage coefficient and the current coefficient are calculated for each standard cell by using an effective power supply voltage applied to the standard cell in order from a standard cell having an earlier operation time among standard cells. 2. The delay time calculation device according to 1. 13. The current consumption calculating means includes switching frequency data giving means for giving a switching frequency for each node of the connection information, wherein the switching frequency, the parasitic element of the signal wiring, and the current consumption of the standard cell are provided. The delay calculation device for a logic circuit according to claim 9, wherein a current consumption of the integrated circuit is calculated using data. 14. The current consumption calculating means calculates a transition probability, which is a probability of transition from one logical value to another logical value, using a logical function included in the connection information; 12. The logic circuit delay calculation device according to claim 9, wherein a current consumption of the integrated circuit is calculated by using current consumption data of a wiring parasitic element and the standard cell. 15. A calculation result output from said effective power supply voltage calculation means is stored, and whether or not a difference between a current calculation result of said effective power supply voltage calculation means and the stored calculation result falls within a predetermined range. The method further comprises: a convergence condition determination unit that repeats the current consumption calculation unit and the effective power supply voltage calculation unit until the difference falls within the predetermined range. 9-1
3. The delay calculation device for a logic circuit according to any one of 2. 16. The FET is a P-channel MOSFET
The delay calculation device for a logic circuit according to any one of claims 7 to 15, wherein: 17. The drain saturation current of the FET is obtained by raising a difference between a power supply voltage and a threshold voltage of the FET to a power by a predetermined coefficient, and multiplying a value obtained by raising the power to a gain coefficient of the current. 2. The method according to claim 1, wherein the value is obtained.
6. The delay calculation device for a logic circuit according to any one of items 5. 18. A method for calculating a delay data of a signal propagation time of a delay library used in a simulation of a logic circuit including a logic element including an FET, wherein the ratio is a value of a ratio of a second power supply voltage to a first power supply voltage. A power supply voltage coefficient defining step of defining a power supply voltage coefficient; and a drain saturation current of the FET when the first power supply voltage is applied with respect to a drain saturation current of the FET when the second power supply voltage is applied. A current coefficient defining step of defining a current coefficient which is a value of a ratio of: a first delay time defining a first delay time which is a delay time of the logic circuit when the first power supply voltage is applied Defining the product of the first delay time, the power supply voltage coefficient, and the current coefficient, thereby delaying the logic circuit when the second power supply voltage is applied. The second determines the delay time, the delay data calculation method of the delay library, characterized in that the delay time of the second and a delay data determination step of the delay data is time. 19. The FET is a P-channel MOSFET
The method for calculating delay data of a delay library according to claim 18, wherein: 20. The drain saturation current of the FET is obtained by raising a difference between a power supply voltage and a threshold voltage of the FET to a power by a predetermined coefficient, and multiplying a value obtained by raising the power to a gain coefficient of the current. 20. The method for calculating delay data of a delay library according to claim 18 or 19, wherein the calculation is performed. 21. A method for calculating delay data of a signal propagation time of a delay library used in a simulation of a logic circuit including a logic element including a P-channel MOSFET and an N-channel MOSFET, wherein a second power supply with respect to a first power supply voltage is provided. A power supply voltage coefficient defining step of defining a power supply voltage coefficient which is a value of a voltage ratio; and the first power supply voltage with respect to a drain saturation current of the P-channel MOSFET when the second power supply voltage is applied. P-channel MOSFET when
A first current coefficient defining step of defining a first current coefficient which is a value of a ratio of a drain saturation current of the N-channel MOSFET to a drain saturation current of the N-channel MOSFET when the second power supply voltage is applied. The N-channel MOSFET when one power supply voltage is applied
A second current coefficient defining step of defining a second current coefficient which is a value of a ratio of a drain saturation current of the logic circuit, a first rise delay time of the logic circuit when the first power supply voltage is applied, and A first delay time defining step of defining a first fall delay time; and calculating a product of the first rise delay time, the power supply voltage coefficient, and the first current coefficient, thereby obtaining the second delay time. Determining a second rising delay time, which is a rising delay time of the logic circuit when the power supply voltage is applied, and using the second rising delay time as rising delay data; 1 to calculate the product of the power supply voltage coefficient and the second current coefficient, whereby the fall delay of the logic circuit when the second power supply voltage is applied is calculated. A delay fall data determining step of determining a second fall delay time, which is a time, and using the second fall delay time as fall delay data. Method of calculation. 22. A value obtained by raising each of the drain saturation currents of the P-channel MOSFET and the N-channel MOSFET to a power of a difference between a power supply voltage and a threshold voltage of each of the MOSFETs by a predetermined coefficient. 22. The method for calculating delay data of a delay library according to claim 21, wherein the calculation is performed by multiplying the delay gain by a current gain coefficient.