JPH1011477A - Generating device for input file for simulation of integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate an input file by which a high-precision simulation result can be obtained. SOLUTION: Circuit information on an integrated circuit to be simulated is inputted from a circuit information input means 1 to generate a circuit information file (a). A net list generating means 2 utilizes a subcircuit library (b) to substitute circuit constituent element of transistor level for respective logic elements included in the circuit information file (a), thereby generating a net list (c). In a process parameter library (d), process parameters of oxide film thickness, impurity density, etc., are prepared by models. An input file generating means 3 selects a specific model based upon transistor size by referring to a model selection table (f) as to each transistor in the net list (c) and sets process parameters regarding the selected model for individual transistors to generate an input file (e) for simulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for creating an input file for simulation, and more particularly, to an input file to be given to a circuit simulator in order to execute a simulation for an integrated circuit in the course of design in an integrated circuit design stage. Related to the device to be created.

[0002]

2. Description of the Related Art Integrated circuit design work is usually performed using a dedicated C
This is performed using an AD system. In this CAD system, various data libraries are constructed as past design assets, and a designer designs a new integrated circuit having a target function while appropriately using data in the data library. Will do. Generally, since an integrated circuit is composed of an enormous number of logic elements, sequential circuits, and the like, a circuit simulation is appropriately performed during the design, and the operation of changing the design based on the result is repeated.

[0003] Simulation of an integrated circuit is usually performed using a dedicated circuit simulator. As such a dedicated circuit simulator, for example, “SP
Devices such as "ICE" are widely known. When performing a simulation with this type of circuit simulator, it is necessary to create an input file for simulation in advance and provide the input file to the circuit simulator. The simulation input file is a file including a netlist indicating a circuit configuration to be simulated and information indicating process parameters such as an oxide film thickness and an impurity concentration in a semiconductor manufacturing process.
The circuit simulator constructs a virtual semiconductor device based on the information included in the input file, and simulates a physical phenomenon occurring in the virtual device.

[0004]

As described above, the simulation performed by the circuit simulator is executed in the form of an arithmetic process based on a simulation input file prepared in advance. Therefore, the quality of the simulation result is determined by the quality of the input file, and the task of creating a more accurate input file is very important. However, there are many process parameters that govern actual physical phenomena, and it is practically impossible to create a simulation input file in consideration of all these process parameters. For this reason, at present, input files are usually created in consideration of only very limited process parameters. Therefore, there is a limit to a circuit simulation using a simulation input file created by a conventional method, and it is difficult to obtain a simulation result with ideal accuracy.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an apparatus for creating a simulation input file for an integrated circuit, which can easily create a simulation input file capable of obtaining more accurate simulation results. .

[0006]

[Means for Solving the Problems]

(1) A first aspect of the present invention is a circuit information input means for inputting circuit information expressing an integrated circuit to be simulated as a set of logic elements to generate a circuit information file, and Using a sub-circuit library consisting of a set of sub-circuits for replacing with a transistor-level circuit component, each logic element included in the circuit information file is replaced with a transistor-level circuit component, and a netlist is generated. Utilizing a netlist generating means and a process parameter library comprising a set of process parameters in a semiconductor manufacturing process, setting process parameters for each transistor-level circuit component included in the netlist, and setting the set process parameters and nets. For simulation by list A simulation input file generating means for generating an input file, wherein a plurality of models are prepared as process parameters in a process parameter library in an apparatus for creating a simulation input file to be given to a circuit simulator for executing a simulation. Then, a model selection table for selecting a specific model based on the size of the transistor is prepared, and the input file generation unit refers to the model selection table based on the size of each transistor included in the netlist based on the size. A specific model is selected, and process parameters corresponding to the selected model are set for each individual transistor.

(2) The second aspect of the present invention is the above-mentioned first aspect.
In the apparatus for creating an input file for simulation of an integrated circuit according to the aspect, the size of each transistor is determined based on the gate length L or the gate width W.

(3) A third aspect of the present invention is the above-described first aspect.
Alternatively, in the apparatus for creating an input file for simulation of an integrated circuit according to the second aspect, a process parameter indicating a thickness of a gate oxide film is prepared for a plurality of models, and a transistor having a large size indicates a larger oxide film thickness. This is to select a model.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on an embodiment shown in the drawings. FIG. 1 is a block diagram showing a basic configuration of an apparatus for creating an input file for simulation of an integrated circuit according to an embodiment of the present invention. Here, the circuit information input means 1 is a means for inputting circuit information expressing an integrated circuit to be simulated as a set of logic elements. The information for specifying an integrated circuit designed by a designer includes the circuit information. It is input by the input means 1 and output in the form of a circuit information file a. Further, the netlist generating means 2 has a function of applying the sub-circuit library b to the circuit information file a to generate a netlist c. The sub-circuit library b is an aggregate of sub-circuits for replacing individual logic elements with transistor-level circuit components. Individual logic elements included in the circuit information file a are replaced with specific subcircuits in the subcircuit library b, and a netlist c indicating connection relationships between circuit components at the transistor level is created. become.

On the other hand, the input file generating means 3 sets and sets the process parameters for each transistor-level circuit component included in the netlist c by using a process parameter library d composed of a set of process parameters. It has a function of generating a simulation input file e from the process parameters and the netlist c. Here, the process parameters are various physical or electrical parameters related to the semiconductor manufacturing process. For example, the thickness value of the gate oxide film of the MOS transistor, the impurity concentration value of the semiconductor substrate, and the ON state of the MOS transistor / OFF threshold value. In other words, while the netlist c is data including a plane figure for representing an integrated circuit with transistor-level circuit components, the process parameters represent the physical / electrical properties of each plane figure. It can be said that it shows. After all, the simulation input file e generated by the input file generating means 3 includes the netlist c indicating the planar figure of the circuit, the process parameters indicating the physical / electrical properties of each planar figure determined by the semiconductor manufacturing process, and The simulation input file e is provided to the circuit simulator, and an actual circuit simulation is executed.

As described above, the process parameter is a parameter determined by the semiconductor manufacturing process, and is usually a parameter commonly applied to all transistors formed on one semiconductor substrate.
For example, although the thickness of the gate oxide film and the like may be different between the P-type transistor and the N-type transistor, the same type of transistor formed on the same semiconductor substrate usually has a different thickness. , The same film thickness is set. Similarly, parameters such as impurity concentration values are set to the same value on the same substrate, and different values are not set for individual transistors. This is because, in a semiconductor manufacturing process, a layer forming step, an impurity diffusion step, and the like are usually performed on the entire surface of the substrate, so that the film thickness and the impurity concentration cannot be changed for each region.

Therefore, from the viewpoint of faithfully simulating a semiconductor device obtained by an actual manufacturing process, common parameters should be used for the entire semiconductor substrate. For this reason, conventionally, a process parameter common to each transistor is set from the process parameter library d to generate the simulation input file e.

The basic idea of the present invention is to review such a conventional viewpoint and set a different process parameter for each transistor, thereby obtaining a simulation result with high accuracy. Such a basic idea deviates from the viewpoint of faithfully simulating a semiconductor device obtained by an actual manufacturing process as it is. For example, when two P-type MOS transistors T1 and T2 are formed on the same semiconductor substrate, the gate oxide films of both transistors have the same thickness in consideration of a normal semiconductor planar process (of course, each transistor has a different thickness). Although it is possible to change the film thickness every time, a common film forming process cannot be performed on the entire semiconductor substrate, and it cannot be said that the current semiconductor manufacturing technology is a realistic manufacturing method.) The basic idea of the present invention is to recognize the fact that the simulation deviates from a faithful simulation and dare to set different process parameters for each transistor to obtain a simulation result with higher accuracy. It is.

According to the present invention, for example, different oxide film thicknesses are set for two P-type MOS transistors T1 and T2 on the same semiconductor substrate. More specifically, for example, in an actual design, a P-type M
It is assumed that the oxide film thickness of the OS transistor is set to 1 μm. In this case, if the device is manufactured as designed, the oxide film thickness of all the P-type MOS transistors in this device is 1 μm.
Therefore, in order to perform a faithful simulation,
As the process parameter indicating the oxide film thickness, naturally, 1
μm must be set. However, in the present invention, for example, parameters are set such that the oxide film thickness of the transistor T1 is 0.9 μm and the oxide film thickness of the transistor T2 is 1.1 μm.

The inventor of the present application has higher accuracy when executing a simulation in which different process parameters are set for each transistor than in setting a correct process parameter in common for each transistor and executing a faithful simulation. They have found that sometimes results can be obtained. In particular, it was confirmed that more accurate results could be obtained by setting different process parameters depending on the size of the transistor. For example, even for a transistor having an oxide film thickness of 1 μm, a slightly small film thickness of 0.9 μm is set for the small-sized transistor T1 and a slightly large film thickness of 1.10 μm is set for the large-sized transistor T2. When 1 μm is set, a simulation result with higher accuracy (that is, a result close to an actual device) can be obtained as compared with a case where the film thickness is uniformly set to 1.0 μm for all transistors.

The reason why such a phenomenon occurs is not strictly analyzed theoretically, but the present inventor thinks as follows. In other words, the physical or electrical factors that affect the phenomena occurring in an actual semiconductor device are so large that they cannot be enumerated, and it is extremely difficult to describe them with a limited number of process parameters. It is. For example, ambient temperature conditions, humidity conditions, or dimensional changes due to thermal expansion of a semiconductor are not taken into account in a normal simulation, and process parameters indicating such physical quantities are not usually set. Thus, some of the parameters that were not considered in previous simulations are
It is considered that some parameters have different degrees of influence based on the type and size of the transistor. The basic idea of the present invention is that the factors included in the parameters not considered are reflected in the parameters considered. However, at this time, it is not necessary to theoretically analyze how the parameter not considered acts on the parameter considered. It is sufficient if it can be experimentally confirmed that a more accurate simulation result can be obtained.

For example, in the above-described example, a slightly larger oxide film thickness than the original is used for a large transistor, and a slightly smaller oxide film is used for a small transistor. Then
Based on the experimental fact that simulation results with higher accuracy than simulation results using uniform oxide film thickness values were obtained, process parameters indicating different film thicknesses for each transistor size were determined. You will be using it. At this time, if the film thickness value is changed in accordance with the transistor size, a theoretical analysis of why a highly accurate simulation result is obtained is not always necessary, and the object of the present invention to obtain a highly accurate simulation result is not necessarily achieved. Such a theoretical analysis is not necessary. While observing the consistency between the simulation results and the measurement results of the actual semiconductor device, an empirical rule was obtained on how to set the process parameters for each transistor in order to further improve the consistency. If possible, it becomes possible to set an optimum process parameter for each transistor based on this rule of thumb. The individual process parameters are originally
Although it is a numerical value having a specific physical meaning (for example, the thickness of an oxide film of a transistor), a process parameter taken into a simulation input file is treated as a simple coefficient in performing a simulation calculation. As described above, the basic idea of the present invention is to consider process parameters as simple coefficients and correct the coefficient values appropriately to obtain more accurate simulation results.

Based on such a basic idea, the process parameter library d of the apparatus according to the present invention shown in FIG.
Inside, a plurality of models are prepared as process parameters. For example, a parameter model to be applied to a large-sized transistor and a parameter model to be applied to a small-sized transistor are separately prepared. Then, in order to select this model, a model selection table f for selecting a specific model based on the size of the transistor is separately prepared. Then, based on the size, a specific model is selected with reference to the model selection table f, and processing for setting a process parameter corresponding to the selected model for each individual transistor is executed. For this reason, as the process parameters included in the simulation input file e, for example, different parameters are set for a large transistor and a small transistor.

It is easy to determine the size of a MOS transistor by using the gate length L or the gate width W of the transistor. The individual sub-circuit information prepared in the sub-circuit library b includes graphic information indicating the configuration of each part of the transistor, and in the case of a MOS transistor, includes data indicating the gate length L and the gate width W of the transistor. Have been. Therefore, the input file generating means 3 determines, for each MOS transistor included in the netlist c,
The model may be selected based on the gate length L or the gate width W.

[0020]

Next, the operation of the apparatus for creating an input file for simulation of an integrated circuit shown in FIG. 1 will be described with reference to a more specific embodiment. Here, a specific example in which a designer designs a specific integrated circuit as shown in the circuit diagram of FIG. 2 and simulates the integrated circuit will be described below. The circuit shown in FIG. 2 includes a NAND gate A1 and an inverter B
1, a NOR gate C1, a NAND gate A2, and an inverter B2.
Although it is a simple circuit that outputs signals to the two output terminals O1 and O2 based on the logic signal given to I4, an actual integrated circuit usually has a huge number of tens of thousands or hundreds of thousands of gates. Logic gates.

The designer adds a circuit as shown in FIG.
The design is performed by a circuit design tool using D. When designing a circuit using such a circuit design tool,
The circuit to be designed is given as circuit information composed of digital data described in a predetermined format. This circuit information is usually prepared as data indicating the connection relationship between the individual logic elements. The circuit information input means 1 is a means for inputting such circuit information, and the input circuit information is output as a file having a predetermined format called a circuit information file a.

FIG. 3 is a diagram showing an example of the circuit information file a. According to the format of this example, the circuit shown in FIG. 2 is described by 11 lines of character strings. That is, the heading “Circuit Name” is described in the row number 1, and the circuit name “SEQ01” is described in the row number 2. Line number 3 is a heading “circuit input / output terminal information”, line number 4 is input terminal information “INPUT I1, I2, I3, I4”, and line number 5 is “OUTPUT O1, O2”.
2 is described. Further, the line number 6 has a heading “Circuit Connection Information”, and the line number 7 has “N”.
“AND A1 (N1, I1, I2)”, the input / output terminal information of the NAND gate A1, and the row number 8 includes “INV B1
(N2, I3) ", the input / output terminal information of the inverter B1 and the row number 9 include" NOR C1 (N3, N1, N
2) ", the input / output terminal information of the NOR gate C1, the row number 10 is the input / output terminal information of the NAND gate A2" NAND A2 (O1, N3, N4) ", and the row number 11 is" INV B2 (O2, O1) "is described.

FIG. 4 shows a part of the sub-circuit library b. Here, the sub-circuit information of the inverter, the NAND gate, and the NOR gate is shown. That is, the “inverter IN
V "is an input terminal IN1, an output terminal OUT1, and a power supply terminal V
DD and a ground terminal GND are described. In row number 2, the first transistor M1 constituting the “inverter INV” includes a source electrode connected to the ground terminal GND, a gate electrode connected to the input terminal IN1, and a drain connected to the input terminal IN1. The electrodes are NMOS transistors connected to the output terminal OUT1, respectively. The gate length is 0.8 μm and the gate width is 15.0 μm.
In the row number 3, the second transistor M2 has a source electrode connected to the power supply terminal VDD, a gate electrode connected to the input terminal IN1, and a drain electrode connected to the output terminal OUT.
1 are PMOS transistors respectively connected to
It is described that the gate length is 0.8 μm and the gate width is 15.0 μm. Line number 4 is a line indicating that the description of the “inverter INV” ends here.

In the row No. 6, the "NAND gate" has the input terminals IN1 and IN2 and the output terminal OUT.
1, a power supply terminal VDD and a ground terminal GND are described. In row number 7, the first transistor M1 forming the "NAND gate" has a source electrode connected to the power supply terminal VDD, and a gate electrode connected to the input terminal. It is described that IN1 is a PMOS transistor having a drain electrode connected to the output terminal OUT1 and a substrate region connected to the power supply terminal VDD. The gate length is 0.8 μm and the gate width is 13.0 μm. Has a second transistor M2
A PMOS having a source electrode connected to the power supply terminal VDD, a gate electrode connected to the input terminal IN2, a drain electrode connected to the output terminal OUT1, and a substrate region connected to the power supply terminal VDD.
It is described that the transistor has a gate length of 0.8 μm and a gate width of 13.0 μm, and the row number 9 shows that the third transistor M3 has a source electrode of the node N
1, an NMOS transistor having a gate electrode connected to the input terminal IN1, a drain electrode connected to the output terminal OUT1, and a substrate region connected to the ground terminal GND. The gate length is 1.0 μm and the gate width is 13.0 μm. Is described, and the fourth transistor M4
Is an NMOS transistor in which the source electrode is connected to the ground terminal GND, the gate electrode is connected to the input terminal IN2, the drain electrode is connected to the node N1, and the substrate region is connected to the ground terminal GND. The gate length is 1.0 μm and the gate width is : 1
It is described to be 3.0 μm. Line number 11
Is a line indicating that the description of the “NAND gate” ends here.

Further, in the row number 13, this "NOR gate" has input terminals IN1 and IN2, and an output terminal OUT.
1, the power supply terminal VDD and the ground terminal GND are described. In the row number 14, the first transistor M1 constituting the "NOR gate" includes a source electrode connected to the ground terminal GND, and a gate electrode connected to the input terminal. It is described in IN1 that the NMOS transistor has a drain electrode connected to the output terminal OUT1 and a substrate region connected to the ground terminal GND, and has a gate length of 0.8 μm and a gate width of 15.0 μm. Has a second transistor M2
Is an NMOS having a source electrode connected to the ground terminal GND, a gate electrode connected to the input terminal IN2, a drain electrode connected to the output terminal OUT1, and a substrate region connected to the ground terminal GND.
It is described that the transistor has a gate length of 0.8 μm and a gate width of 15.0 μm. In row number 16, the third transistor M3 has a source electrode of node N
1, a PMOS transistor having a gate electrode connected to the input terminal IN1, a drain electrode connected to the output terminal OUT1, and a substrate region connected to the power supply terminal VDD. The gate length is 1.0 μm and the gate width is 15.0 μm. Is described, and the fourth transistor M4
Is a PMOS transistor in which the source electrode is connected to the power supply terminal VDD, the gate electrode is connected to the input terminal IN2, the drain electrode is connected to the node N1, and the substrate region is connected to the power supply terminal VDD. The gate length is 1.0 μm and the gate width is : 1
It is described to be 5.0 μm. Line number 18
Is a line indicating that the description of the “NOR gate” ends here.

The sub-circuit library b contains:
In addition to the above, descriptions showing the circuit configuration at the transistor level are prepared for various logic elements, but are not shown here. The netlist generation means 2
The sub-circuit in the sub-circuit library b is applied to each logic element included in the circuit information file a to generate a netlist. For example, for NAND gates A1 and A2 shown in FIG. 2, four transistors M1 to M1 described in row numbers 6 to 11 in FIG.
M4 is performed, and inverters B1 and B1 shown in FIG.
B2 is replaced by the two transistors M1 and M2 described in row numbers 1 to 4 in FIG. 4, and the NOR gate C1 shown in FIG.
The replacement by the four transistors M1 to M4 described in 18 will be performed. The netlist c generated by the netlist generation means 2 is such a MOS list.
It becomes circuit configuration information described at the transistor level.

FIG. 5 is a diagram showing a part of the process parameter library d used in the present invention. In the example shown here, two models of “NMOS1” and “NMOS2” are prepared as NMOS transistors,
Two models of “PMOS1” and “PMOS2” are prepared as transistors. That is, row number 1
1 describes a heading indicating that it is a parameter of a transistor “NMOS1” as one transistor model of the NMOS, and the row number 12 describes
This transistor model has a simulation level “L
EVER = 2 ”and that its threshold voltage VTO is 0.9 V. The row number 13 shows the gate oxide film thickness T of this transistor model.
It is described that OX is 1.0 μm and that the impurity concentration of the N-type substrate region is 1.0. Similarly, the process parameters for the transistor model NMOS2 are described after the row number 21, the process parameters for the transistor model PMOS1 are described after the row number 31, and the transistor parameters for the transistor model PMOS2 are described after the row number 41. The process parameters are described.

As a model selection table f for selecting each model, for example, a table as shown in FIG. 6 may be prepared. This table contains N
This shows a model to be selected based on the gate width W and the gate length L of each of the MOS transistor and the PMOS transistor. For example,
The NAND gate A1 in the circuit shown in FIG. 2 corresponds to the MOS transistor M specified in the row numbers 7 to 10 of the sub-circuit library b shown in FIG.
1 to M4. Here, the transistor M1 has a gate length L = 0.8 μm and a gate width W = 1.
Since it is a 3.0 μm PMOS transistor, a transistor model of PMOS1 is selected from the table of FIG. Similarly, transistors M2 and M
3 and M4, respectively, the transistor model PM
OS1, NMOS2, and NMOS2 are selected. Thus, the input file generation means 3 sets the process parameters defined by the selected transistor model for each transistor, and generates the simulation input file e.

The simulation input file e generated in this way includes a netlist c and a process parameter as shown in FIG. 7. This process parameter is set for each transistor. For example, the transistors M1, M2, M3, and M4 forming the NAND gate A1 have transistor models PMOS1, PMOS1, and NMO, respectively.
The process parameters of S2 and NMOS2 are set, and the transistors M1 and M2 constituting the inverter B1 are
The process parameters of the transistor models NMOS3, PMOS3 are respectively set, and the transistors M1, M2, M3, M4 forming the NOR gate C1 are respectively provided with the transistor models NMOS3, NMOS3, PM
The process parameters of OS4 and PMOS4 are set. Of course, the values of the process parameters set for each transistor in this way deviate from the values as actual physical parameters, but function as coefficients for obtaining more accurate simulation results. Become.

[0030]

As described above, according to the apparatus for creating an input file for simulation of an integrated circuit according to the present invention,
This makes it possible to easily create a simulation input file from which a more accurate simulation result can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a basic configuration of an apparatus for creating an input file for simulation of an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a specific integrated circuit to be simulated;

FIG. 3 is a diagram showing an example of a circuit information file a for the integrated circuit shown in FIG.

FIG. 4 is a diagram showing an example of a sub-circuit library used to create a netlist.

FIG. 5 is a diagram showing an example of a process parameter library according to the present invention for enabling setting of different process parameters for each transistor model.

FIG. 6 is a diagram illustrating an example of a model selection table for selecting a model for the process parameter library illustrated in FIG. 5;

7 is a diagram showing an example of a simulation input file created for the integrated circuit shown in FIG. 2 using the process parameter library shown in FIG. 5 and the model selection table shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Circuit information input means 2 ... Net list generation means 3 ... Input file generation means a ... Circuit information file b ... Sub-circuit library c ... Net list d ... Process parameter library e ... Model selection table f ... Input file for simulation A1, A2: NAND gates B1, B2: Inverter C1: NOR gates I1 to I4: Input terminals N1 to N3: Nodes O1, O2: Output terminals

Claims (3)

[Claims] 1. Circuit information input means for inputting circuit information expressing an integrated circuit to be simulated as a set of logic elements and generating a circuit information file, and converting each logic element to a transistor-level circuit component Using a sub-circuit library consisting of a set of sub-circuits for replacement, replacing each logic element included in the circuit information file with a transistor-level circuit component, and generating a net list generating means, A process parameter library including a set of process parameters in a semiconductor manufacturing process is used to set process parameters for each of the transistor-level circuit components included in the netlist, and a simulation is performed using the set process parameters and the netlist. A simulation input file generating means for generating an input file; and an apparatus for generating a simulation input file to be given to a circuit simulator for executing a simulation, wherein a plurality of models are set as process parameters in the process parameter library. Preparing, preparing a model selection table for selecting a specific model based on the size of the transistor, wherein the input file generating means generates the model selection table based on the size of each transistor included in the netlist. An apparatus for creating an input file for simulation of an integrated circuit, wherein a specific model is selected by referring to the model, and a process parameter corresponding to the selected model is set for each transistor. 2. The apparatus according to claim 1, wherein the size of each transistor is determined based on the gate length L or the gate width W. 3. The apparatus according to claim 1, wherein a process parameter indicating a thickness of the gate oxide film is prepared for a plurality of models, and a model indicating a larger oxide film thickness is selected for a large-sized transistor. An apparatus for creating an input file for simulation of an integrated circuit, comprising: