JP2862258B2 - Image reading device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading apparatus, and more particularly, to an image reading apparatus using a multi-channel image sensor that outputs image signals from a plurality of channels.

[Conventional technology]

 FIG. 7 shows a conventional document reading apparatus.

In the figure, reference numeral 901 denotes a three-line color CCD image sensor, which is a dual-channel CCD image sensor 902 to 904.
The charge of the odd-numbered pixels and the charges of the even-numbered pixels are separately transferred, and R, G, and B organic color separation filters are arranged on the sensor element. 71a and 71b are buffer amplifiers, and 72a and 72b are output signals V _OSA and V of the image sensor.
A sample and hold circuit (S / H) for removing reset noise contained in the _OSB , 73a and 73b are variable amplifiers for adjusting the levels of the output signals V _OSA and V _OSB when reading a white board, and 74a and 74.
b is a clamp amplifier that corrects the level difference between the output signals V _OSA and V _OSB and clamps to a predetermined level, for example, GND (= 0V) level, and 75a and 75b amplify and clamp the output signals V _OSA and V _OSB . An A / D converter 76 converts a signal into digital data. A selector circuit 76 switches the digitally converted output signals V _OSA and V _OSB on a pixel-by-pixel basis to convert the output signal into an original one-line read signal.

FIG. 9 shows the configuration of the three-line color CCD image sensor 901 shown in FIG.

In the figure, reference numeral 91 denotes a light receiving unit for performing photoelectric conversion according to the amount of incident light. On the CCD sensor element of the light receiving section 91, R, G, B color separation filters are provided on-wafer. 92 and 93 is a transflector agate, it is to transfer to the CCD shift register 94, 95 in accordance with charges stored in the light receiving section 91 to the shift gate pulse phi _TG. The electric charges accumulated in the even-numbered pixels of the light-receiving unit 91 are transferred to each CCD shift register 95 for the even-numbered pixels by each transfer gate 93, while the electric charges accumulated in the odd-numbered pixels of the light-receiving unit 91 are transferred to each transfer gate. Each CC for odd pixels by Agate 92
The data is transferred to the D shift register 94. CCD shift register 9
4, 95 transfer the electric charge sent from the light receiving section 91 to the output section by CCD (complete transfer) and drive clock φ ₁ (φ _1R , φ _{1
1FR, φ 1G, φ 1FG,} φ 1B, φ 1FB) and φ ₂ (φ _{2R,
φ 2FR, φ 2G, φ 2FG} , φ 2B, are two-phase driven by phi _2FB). Reference numeral 96 denotes an output gate for sending electric charges from the CCD shift registers 94 and 95 to the output capacitors 97a and 97b. Reference numerals 97a and 97b denote output capacitance units for converting the transferred charges into voltages. Reference numerals 98a and 98b denote two-stage source follower amplifiers for lowering the output impedance and preventing noise from being added to the output signal.

Output capacitors 97a and 97b and source follower amplifiers 98a and 98b
Constitute an FDA (Floating Diffusion Amplifier).

OSAR, OSBR, OSAG, OSBG, OSAB, OSBB are signal output terminals, φR
AR, φRBR, φRAG, φRBG, φRAB, φRBB are reset pulse terminals, φ1R, φ1G, φ1B, φ2R, φ2G, φ2B are CCD shift register clock terminals, φ1FR, φ2FR, φ1FG, φ2FG, φ1FB, φ2F
B is the final stage clock pin of the CCD shift register, φTGR, φTG
G and φTGB are transfer gate clock terminals, ODR, ODG, O
DB is a source follower amplifier drain terminal.

In the color image sensor 901 thus configured, the light incident on the light receiving unit 91 is converted into a charge proportional to the amount of light, and this charge is supplied to the CCD shift registers 95 and 94 by the shift gate pulse φ _TG for even-numbered pixels. It is transferred separately for each odd-numbered pixel, and then, according to the drive clocks φ1 and φ2,
At the timing shown in FIG. 2, the data is output one bit at a time to the FDA via the output gate 96, and the output capacitance units 97a, 97a,
At 97b, the charge output is converted to a voltage, and then the two-stage source follower amplifiers 98a, 98b and the respective output terminals OSA, O
Output via SB.

In a state where no light is given to the light receiving section 91, even and odd numbers
Since the potentials applied to the CCD shift registers 95 and 94 are slightly different,
The dark output levels output from the output terminals OSA and OSB are different.

However, in the conventional document reading apparatus, the output signals V _OSA and V _OSB are subjected to signal processing of amplification, DC clamp, and A / D conversion by separate processing systems, and the level difference between the output signals V _OSA and V _OSB is removed. Later, by digitally multiplexing each pixel, an image signal of one line at the time of reading was obtained, so two systems of variable amplifiers and A / D converters were required, limiting the cost of equipment. was there.

 Therefore, a configuration as shown in FIG. 8 is conceivable.

In the figure, reference numeral 901 denotes the same part as FIG. In the present embodiment, the signal processing system for the output signals of the R, G, and B CCD image sensors has the same circuit configuration. Therefore, the R CCD image sensor will be described.

Reference numerals 802a and 802b denote buffer amplifiers, which are an odd pixel signal 801a and an even pixel signal 801b of the R-CCD image sensor 902, respectively.
In response to this, impedance conversion is performed. 803a, 8
03b denotes a sample-and-hold circuit (S / H), which is an odd-numbered pixel signal 80 of the R-CCD image sensor 902 output in time series.
1a, to remove reset noise contained in the even-numbered pixel signal 801b. Reference numerals 804a and 804b denote clamp amplifiers as correction means, each comprising amplifiers 804a-1 and 804b-2 and clamp circuits 804a-2 and 804b-2. The clamp amplifier 804a has a sample-hold circuit 803a from which reset noise is removed. The DC offset level of the odd-numbered pixel signal is clamped to 0 V, and the clamp amplifier 804b removes the reset noise of the even-numbered pixel signal by the sample-and-hold circuit 803b.
The offset level is clamped to the same level (0 V) as the clamp amplifier 804a. A multiplexer 805 receives the odd-numbered pixel signal and the even-numbered pixel signal from the clamp amplifiers 804a and 804b, and sequentially outputs the odd-numbered pixel (ODD) signal at the timing shown in FIG.
By switching between even-numbered pixel (EVEN) signals, serial pixel signals are obtained in the order of pixel arrangement in the light receiving section of the R-CCD image sensor 902 as shown in FIG.

A variable amplifier 806 amplifies the output level of a serial pixel signal output in time series by the multiplexer 805 to the dynamic range of the A / D converter 808. Reference numeral 808 denotes a clamp amplifier which clamps the DC offset level of the serial pixel signal amplified by the variable amplifier 806 to the dynamic range of the A / D converter 808 to the lowest reference level of the A / D converter 808, that is, 0V. Things.

The A / D converter 808 converts an analog pixel signal, which is a serial pixel signal subjected to DC offset correction by the clamp amplifier 807, into a digital pixel signal.

Next, the operation will be described using the R-CCD image sensor 902 as an example.

Since the CCD structure of the sensor 902 is a dual-channel type, and the odd and even charges of the sensor pixel 91 are transferred by separate CCD shift registers 94 and 95, the odd and even CCD shift registers 94 and 95 The difference in potential causes a difference in the output DC offset level between the odd-numbered pixel and the even-numbered pixel.

Output signals 801a and 801b of the R-CCD image sensor 902 having a difference in the output DC offset level between the odd and even pixels.
Are subjected to impedance conversion by the buffer amplifiers 802a and 802b, and then input to the sample and hold circuits 803a and 803b. This input signal is used as a sample and hold circuit 803
The signals a and 803b are sampled and held at the timings shown in FIGS. 2 (8) and (9) to remove reset noise contained in the input signal, and then input to the respective clamp amplifiers 804a and 804b.

Then, the clamp amplifiers 804a and 804b compare the DC output level of the dark output unit from the R-CCD image sensor 902 with a predetermined reference level 0V, and the DC level of the dark output unit is
Clamped to 0V. Therefore, the odd pixel signal and the even pixel signal are clamped to the same reference level, and the DC offset level difference between the odd pixel even pixel signal existing in the output signals of the sample hold circuits 803a and 803b is removed.

The odd and even pixel signals are clamped to the same reference level (0 V) by the multiplexer 805 based on the timing shown in FIG.
The signals are sequentially switched and combined into one line of serial pixel signals. The arrangement of the serial pixel signals synthesized by the multiplexer 805 is the same as the pixel arrangement order of the light receiving unit. The serial pixel signal synthesized by the multiplexer 805 is amplified by the variable amplifier 806, and when the reference white plate is read and scanned by the R-CCD image sensor 902, the output level becomes A / A.
It is approximately approximated to the maximum value of the dynamic range of the D converter 808. Then, A at the white level is
The R signal regulated to the maximum value of the dynamic range in the / D converter is clamped by the clamp amplifier 807 so that the output level in darkness becomes the lowest level of the dynamic range of the A / D converter 808.

The R signal of which the maximum value and the minimum value are regulated with respect to the dynamic range of the A / D converter 808 is converted into a digital image signal by the A / D converter 808.

The R-CCD image sensor has been described above.
G-CCD image sensor 903, B-CCD image sensor 904
Is essentially the same operation, and a description thereof will be omitted.

[Problems to be solved by the invention]

However, in the above-described conventional document reading apparatus, even if the clamp amplifiers 804a and 804b attempt to clamp to the same reference level (0 V), variations in the clamp level due to the clamping accuracy of the clamp amplifiers 804a and 804b and the multiplexing of the multiplexer 805 when multiplexing are performed. Even if a slight difference occurs in the offset level between the even and odd pixels after multiplexing due to the offset error between the channels, etc., the slight difference in the offset level is amplified and expanded by the variable amplifier 806 and the clamp amplifier 807 after multiplexing. A / A by D / D808
After D, it appears as an offset level difference in the data.

In addition, since an offset level difference occurs between even and odd pixels,
Even if an attempt is made by the clamp amplifier 807 to clamp to the reference minimum level of the A / D converter 808 before A / D, an error occurs, and it becomes impossible to clamp to the target level.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image reading apparatus which can solve the above-mentioned problems and can prevent image deterioration.

[Means for solving the problem]

The present invention relates to a multi-channel image sensor for outputting image signals from a plurality of channels in an image reading apparatus, and a first level for correcting a level difference between channels of image signals output from the plurality of channels of the image sensor. Correcting means, synthesizing means for synthesizing the image signals of the plurality of channels, the level difference of which has been corrected by the first level correcting means, and correcting the level of the image signal synthesized by the synthesizing means to a predetermined level. A second level correction unit that performs A / D conversion of an image signal whose level has been corrected by the second level correction unit, and the second level correction unit includes: The level of the image signal synthesized by the synthesizing means is A / D
The level of the image signal is corrected so as to fall within the dynamic range of the conversion means.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In the figure, the color image sensor 901 shows the same parts as in FIG.

In this embodiment, since the signal processing system of the output signals of the R, G, B CCD image sensors has the same circuit configuration, the R CC
The D image sensor will be described.

Reference numerals 102a and 102b denote buffer amplifiers, which are an odd pixel signal 101a and an even pixel signal 101b of the R-CCD image sensor 902, respectively.
In response to this, impedance conversion is performed. 103a, 1
03b is a sample-and-hold circuit (S / H), which is an odd-numbered pixel signal 10 of the R-CCD image sensor 902 output in time series.
1a, to remove reset noise contained in the even-numbered pixel signal 101b.

Reference numerals 104a and 104b denote clamp amplifiers as correction means, and amplifiers 104a-1 and 104b-1 and clamp circuits 104a-2 and 104a, respectively.
4b-2, and the clamp amplifier 104a sets the DC offset level of the odd-numbered pixel signal from which the reset noise has been removed by the sample-and-hold circuit 103a to the reference level V _ref1 = 0.
The clamp amplifier 104b clamps the DC offset level of the even-numbered pixel signal from which the reset noise has been removed by the sample and hold circuit 103b to the reference level _Vref2 output from the voltage control circuit 109.

105 is a multiplexer as a synthesizing means, which receives the odd-numbered pixel signal and the even-numbered pixel signal from the clamp amplifiers 104a and 104b as inputs, and sequentially outputs the odd-numbered pixel (ODD) signal and the even-numbered pixel ( EVEN) signal to obtain a serial pixel signal in the order of pixel arrangement in the light receiving section of the R-CCD image sensor 902 as shown in FIG.

Reference numeral 106 denotes a variable amplifier serving as a variable amplifying unit, which amplifies the output level of the serial pixel signal output in time series by the multiplexer 105 to the dynamic range of the A / D converter 108. Voltage control amplifier (Voltage Control Amplbier: V) whose amplification varies with the output control voltage V _CONT1
CA).

Reference numeral 107 denotes a clamp amplifier, which controls the DC offset level of the serial pixel signal amplified to the dynamic range of the A / D converter 108 by the variable amplifier 106, and a voltage control circuit.
It clamps to the lowest reference level V _BOTTOM of the A / D converter 108 (V _BOTTOM = 0V in this embodiment) according to the control voltage V _CONT2 of 111. A / D converter 108 is a clamp amplifier
An analog pixel signal, which is a serial pixel signal subjected to DC offset correction in 107, is converted into a digital pixel signal.

Here, the voltage control circuits 109, 110, and 111 will be described.

According to FIG. 3, the voltage control circuit 109 comprises an 8-bit multiplying D / A converter 109a and an operation amplifier 109b, 1.
09c and resistors R and 2R, and a multiplying D / A converter 10
CPU not shown with 9a reference input V _ref value
Is multiplied by four quadrants according to the set data value of Output voltage is output.

Since the voltage control circuits 110 and 111 have the same configuration, the description is represented by the voltage control circuit 110.

The voltage control circuit 110 is a voltage control circuit 109
In the same manner as in the above, it is composed of an 8-bit multiplying D / A converter 110a and an operational amplifier 110b (FIG. 4), and the value of the reference input _Vref of the multiplying D / A converter 110a is changed according to the CPU setting data value. , Multiplied by two representations, for example _Are output as V _CONT1 and V _CONT2 .

Here, the difference between the voltage control circuits 110 and 111 is that the voltage control circuit 110 _generates the control voltage V _CONT1 of the voltage control amplifier (VCA) 106 while the voltage control circuit 111 Controls the level setting, and this clamp level
It substantially matches the lowest reference level V _BOTTOM of the A / D converter 108. Therefore, the multiplying A / D of the voltage control circuits 110 and 111
The reference input _Vref of the converter 110a is different depending on the voltage to be controlled.

Next, the operation will be described using the R-CCD image sensor 902 as an example.

Since the CCD structure of the sensor 901 is a dual-channel type and the odd and even charges of the sensor pixel 91 are transferred by separate CCD shift registers 94 and 95, the odd and even CCD shift registers 94 and 95 The difference in potential causes a difference in the output DC offset level between the odd-numbered pixel and the even-numbered pixel.

Output signals 101a and 101b of the R-CCD image sensor 902 having a difference in the output DC offset level between the odd and even pixels.
Is subjected to impedance conversion by the buffer amplifiers 102a and 102b, and then input to the sample and hold circuits 103a and 103b. This input signal is applied to the sample and hold circuit 103
Samples and hold are performed by the signals a and 103b at the timings shown in FIGS. 2 (8) and 9 (9), and the reset noise contained in the input signal is removed. Thereafter, the signals are input to the respective clamp amplifiers 104a and 104b.

Then, the DC output level of the dark output unit from the R-CCD image sensor 902 is compared with a predetermined reference level V _ref1 = 0V by the clamp amplifier 104a, and the DC level of the dark output unit is clamped to approximately 0V.

The other output signal of the R-CCD image sensor 902 is clamped by the clamp amplifier 104b to the reference level _Vref2 in the same manner as the clamp amplifier 104a. At this time, the reference level _Vref2 is finally converted by the A / D converter 108. In this embodiment, the difference between the output data of the ODD / EVEN of the CCD output signal converted into the digital pixel signal is detected by a CPU (not shown) in this embodiment, and in this embodiment, the reference level V _ref1 of the clamp amplifier 104a on the ODD side is detected.
Is fixed at 0V, so that the digital pixel signal
The CPU (not shown) sets data in the voltage control circuit 109 according to the detected value and sets the reference level _{Vref2 so} that the difference between ODD / EVEN is eliminated, thereby turning off DC between the odd-numbered pixel signal and the even-numbered pixel signal. Set level differences are eliminated.

Both the odd and even pixel signals from which the DC offset level difference between the odd and even pixels has been removed are output by the multiplexer 105 as shown in FIG.
The odd-numbered pixel signal and the even-numbered pixel signal are sequentially switched and selected based on the timing shown in FIG.

The arrangement of the serial pixel signals synthesized by the multiplexer 105 is the same as the pixel arrangement order of the light receiving unit.

The serial pixel signal synthesized by the multiplexer 105 is amplified by the variable amplifier 106, and is output to the R-CCD image sensor.
When the reference white plate is read and scanned by 502, the output level is approximately approximated to the maximum value of the dynamic range of the A / D converter 108.

Here, the setting of the amplification degree of the variable amplifier 106 is adjusted by a clamp amplifier 107 described later so that the output level of the R-CCD image sensor 502 in the dark becomes the lowest level of the dynamic range of the A / D converter 108. After reading the reference white plate,
The output data of the A / D converter 108 is read by a CPU (not shown), and the CPU controls the voltage control circuit 110 so that the output data is at a level almost close to the maximum value FF _H of the dynamic range of the A / D converter 108. This is performed by setting data from.

And the A / D converter of the white level by this variable amplifier 106
The R signal restricted to the maximum value of the dynamic range in 108 is clamped by the clamp amplifier 107 so that the output level in darkness becomes the lowest level of the dynamic range of the A / D converter 108.

Here, the setting of the clamp level of the clamp amplifier 107 does not show the output level in the dark after the ODD / EVEN level difference is removed by the clamp amplifiers 104a and 104b.
By reading the data with the CPU and feeding it back to the voltage control circuit 111, the level of the control voltage V _CONT2 is raised or lowered, so that the level is adjusted to a level close to the lowest level V _BOTTOM of the dynamic range of the A / D converter 108. .

The R signal of which the maximum value and the minimum value are regulated with respect to the dynamic range of the A / D converter 108 is converted into a digital image signal by the A / D converter 108.

The R-CCD image sensor has been described above.
The operations of the G-CCD image sensor 903 and the B-CCD image sensor 904 are essentially the same, and a description thereof will be omitted.

In the present embodiment, an example using a dual-channel image sensor has been described.However, even if a dual-channel image sensor such as a quad-channel or a multi-channel image sensor is used, essentially the same operation and effect can be obtained. Can be.

<Another embodiment 1> Fig. 5 shows another embodiment of the present invention.

Comparing the embodiment of FIG. 1 with the embodiment of FIG. 5, the correction means is different. That is, in one embodiment, in order to correct the difference in output level between ODD / EVEN, a clamp amplifier is used.
The reference level V _{ref1 of} 104a is fixed, and the clamp amplifier 104
Although the reference level _{Vref2 of} b is variable with respect to the reference level _Vref1 , in the present embodiment, the reference level _Vref1 of the clamp amplifier 104a is also variable, and the voltage control circuit 1
12 have been newly added.

With such a configuration, in the embodiment of FIG.
The DC output level of the dark output unit from the D image sensor is amplified by the amplifiers 104a-1 and 104b-1, and the clamp circuit 104a
−2,104b-2 clamps to a predetermined level,
At this time, the clamp circuit 104a-2 uses the fixed reference level V
_ref1 is clamped to 0 V, and at 104b-2, the reference level V _ref2 is raised and lowered by the control voltage V _CONT1 of the voltage control circuit 109 so as to match the output level on the ODD side, and ODD / EVE
N output level differences are removed.

On the other hand, in the present embodiment, the clamp circuits 104a-2, 104b-2
The reference levels V _ref1 and V _ref2 of each are variable, and ODD / EVEN
Each final output level is read by a CPU (not shown), and the CPU controls the voltage control circuits 112 and 109 so that the ODD / EVEN separately has the same set level, and the control voltages V _CONT4 ,
By varying the reference levels V _ref1 and V _ref2 of the clamp circuits 104a-2 and 104b-2 with V _CONT1 , the output level difference of ODD / EVEN is removed.

Because of this, the effect of this embodiment is not essentially different from that of the embodiment shown in FIG.

<Another embodiment 2> Fig. 6 shows another embodiment of one embodiment.

When comparing the embodiment of FIG. 6 with the embodiment of FIG.
In the embodiment of the figure, the reference level V _ref1 of the clamp amplifier 104a is fixed, and the reference level V _ref2 of the clamp amplifier 104b is variable with respect to the reference level V _ref1 in order to correct the difference in output level between ODD / EVEN. After completely removing the difference between the output levels of ODD / EVEN, the multiplexer 105 combines the odd and even pixels so as to have the same pixel arrangement as the R-CCD image sensor 902, and the variable amplifier 106 and the clamp amplifier 107 perform A / D conversion. The amplification degree and the offset level were varied so that the synthesized pixel signal could fall within the maximum level V _TOP and the minimum level V _BOTTOM of the dynamic range of the converter 108.

On the other hand, in the present embodiment, the clamp amplifiers 104a, 104
b indicates that the reference levels V _ref1 and V _ref2 are set to the same setting level (V _ref1 = V _ref2 = 0 V in the embodiment), and the clamp operation is performed by the multiplexer 105, the variable amplifier 106, and the clamp amplifier 107.
After completion of DD / EVEN synthesis and adjustment of the dynamic range level of the A / D converter 108, an offset variable amplifier 113 is provided.

The variable offset amplifier 113 includes an amplifier 113a, third and fourth voltage control circuits 115 and 116, and a voltage control circuit 1
It comprises a second multiplexer 115 for switching and synthesizing the output signals V _CONT3 and V _CONT4 according to the arrangement of ODD / EVEN pixels.
The configuration of 16 is the same as that of the voltage control circuit 109 shown in FIG.
The configuration is the same as

Now, the output level difference between ODD / EVEN is ODD / E after A / D conversion.
VEN output data is read by a CPU (not shown) and ODD / EVEN
Data is set in each of the voltage control circuits 115 and 116 so that there is no difference between the output data of _VCONT3 and _VCONT4.
The timing (ODD of the multiplexer 105) shown in FIG.
/ EVEN selection signal) to _generate the combined control voltage V _CONT5 for ODD / EVEN and set the offset level of the amplifier 113a to OD.
Perform D / EVEN correction separately.

Because of this, the effect of this embodiment is not essentially different from that of the embodiment of FIG.

〔The invention's effect〕

As described above, according to the present invention, the level difference between image signals output from a plurality of channels is eliminated, and the level of a synthesized image signal output from a plurality of channels falls within the dynamic range of the A / D converter. By correcting so that it can be input, a high-quality image can be output.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an original reading apparatus according to one embodiment of the present invention, FIG. 2 is a timing chart showing an example of the timing of each part in FIG. 1, and FIG. 3 is a diagram showing a voltage control circuit 109 in FIG. FIG. 4 is a block diagram showing the voltage control circuits 110 and 111 of FIG. 1, FIG. 5 is a block diagram showing a document reading apparatus according to another embodiment of the present invention, and FIG. 6 is still another embodiment of the present invention. 7 and 8 are block diagrams showing a conventional document reading device, and FIG. 9 is a block diagram showing an example of the image sensor shown in FIGS. 7 and 8. FIG. 901 is a color image sensor, 104a and 104b are clamp amplifiers, 109, 110 and 111 are voltage control circuits, and 108 is an A / D
It is a converter.

Claims (4)

(57) [Claims] A multi-channel image sensor that outputs image signals from a plurality of channels; a first level correction unit that corrects a level difference between channels of image signals output from the plurality of channels of the image sensor; Synthesizing means for synthesizing the image signals of the plurality of channels whose level differences have been corrected by the first level correcting means; and a second means for correcting the level of the image signal synthesized by the synthesizing means to be a predetermined level. Level correcting means, and A / D converting means for A / D converting the image signal whose level has been corrected by the second level correcting means, wherein the second level correcting means is synthesized by the synthesizing means. The level of the image signal is corrected so that the level of the image signal falls within the dynamic range of the A / D conversion unit. Image reading device. 2. An apparatus according to claim 1, wherein said first level correcting means corrects the level of the image signal for each channel. 3. An image reading apparatus according to claim 1, wherein said second correction means comprises an amplification means and a clamp means. 4. The amplifying means adjusts an output level when a white reference is read by the reading means so as to be close to a maximum value of a dynamic range of the A / D converter. 4. The image reading apparatus according to claim 3, wherein the dark output level of the reading unit is adjusted to be a minimum level of a dynamic range of the A / D converter.