JP2862246B2 - Image editing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Industrial Application Field] The present invention relates to an image processing apparatus. [Prior Art] Conventionally, an image editing signal generating circuit that sets an image editing signal in a RAM or the like to operate an image signal and perform various image processing in real time, and switches the image processing to a bank of the RAM. There is. [Problems to be Solved by the Invention] However, in a system having a plurality of image processing units, a delay of an image signal may occur in each stage of the plurality of image processing units. It cannot handle such complicated systems. That is, in each stage of the plurality of image processing units, a delay time required for processing in each stage occurs. Therefore, if the image signal corresponding to a predetermined area of the image is switched at the same time in order to switch the processing state in a plurality of stages, such as color conversion and spatial filtering processing, such as color conversion and spatial filtering, the aforementioned delay time The timing of the processing of each stage with respect to the image signal is shifted, which causes a problem that image editing cannot be performed with high accuracy. In view of the above, an object of the present invention is to provide an image processing apparatus that can perform editing with good accuracy even if a delay occurs in each stage of the image processing unit. [Means for Solving the Problems] The present invention has been made to solve the above-described problems, and has been made in consideration of the above circumstances, and has been made in consideration of the above-described circumstances. An image processing apparatus in which units are sequentially connected, wherein an edit signal generating unit generates a signal for instructing a switching of a processing mode in an image processing unit other than the image processing unit including the line delay and the image processing unit including the line delay. Means for outputting a signal generated by the edit signal generating means to an image processing unit including the line delay, or outputting the signal to an image processing unit other than the image processing unit including the line delay. And a method of delaying a signal generated by the editing signal generating means. [Embodiment] Hereinafter, a configuration of an embodiment of an image editing signal generating circuit according to the present invention will be described in detail with reference to FIGS. 1 to 11 of the accompanying drawings. (Explanation of Outline) FIG. 1 shows an outline of a digital color copying machine 10 to which an embodiment of an image recording apparatus according to the present invention is applied. The digital color copying machine 10 is roughly composed of two components. In other words, the copying machine 10 is located at an upper position as one of the major components, and reads a document image in color and outputs digital color image data.
An image scanner (hereinafter, abbreviated as a leader unit) 12 is provided. The reader unit 12 includes a controller unit 14 that performs various image processing of digital color image data and has a processing function such as an interface with an external device. The reader unit 12 is a mechanism for reading an image of a three-dimensional or sheet-like document placed downward on a document table (not shown) below the document holding plate 16 and for reading a large-size sheet-like document. It also has a built-in. An operation unit connected to the controller unit 14 is provided on one side of the upper surface of the reader unit 12.
An operation unit 18 is provided for inputting various information as a copying machine. The controller unit 14 is configured to instruct the reader unit 12 and a printer unit 20, which will be described later, regarding these operations in accordance with information input via the operation unit 18. Further, when a complicated editing process or the like needs to be performed, a digitizer or the like is attached in place of the document holding plate 16 and this is connected to the controller unit 14, thereby enabling advanced image processing. The copier 10 further includes, as another broad element, a printer unit 20 for recording a color digital image signal output from the controller 14 on a recording sheet while being positioned below the reader unit 12. It has. In this embodiment, a printer unit 20 is a full-color ink jet printer using a recording head of an ink bubble jet recording system described in Japanese Patent Application Laid-Open No. 54-59936. . The two major elements described above are separable from each other, and are set so that they can be installed at remote locations by extending the connection cable. (Reader unit) FIG. 2 is a block diagram of the digital color copier 10 shown in FIG.
FIG. 2 is a cross-sectional view schematically showing the internal configuration of the device viewed from the side. First, in the reader unit 12 of the copying machine 10, the exposure lamp
22, a lens 24, a full-color image sensor 26 (in this embodiment, a CCD) capable of reading a line image, an image of a document placed on a platen glass 28, a projected image by a projector, or sheet feeding. The image of the sheet original is read by the mechanism 30. Next, in this way, various image processes are performed by the reader unit 12 and the controller unit.
After that, the read image is recorded on the recording paper by the printer unit 20. (Printer Section) In FIG. 2, the recording paper is a paper feed cassette 32 for storing cut paper of a small fixed size (A4 to A3 size in this embodiment) and a large size (A2 in this embodiment).
(Up to A1 size) from the roll paper 34 for recording. In addition, by feeding recording sheets one by one from the manual feed slot 36 shown in FIG. 1 along the feed unit cover 38, it is possible to feed paper from outside the apparatus (manual feed). .
A pick-up roller 40 is provided above the paper feed cassette 32 mounted on the printer unit 20 to take out the cut paper one by one from the paper feed cassette 32. The cut sheet taken out by the pick-up roller 40 is conveyed to a first sheet feed roller 44 by a cut sheet feed roller 42. On the other hand, the roll paper 34 is continuously fed out by a roll paper feed roller 46, cut into a fixed length by a cutter 48, and conveyed to the first feed roller 44 described above. Similarly, the recording paper inserted from the manual feed slot 36 is
The sheet is conveyed to the first sheet feeding roller 44 by 50. Here, the pick-up roller 40, the cut paper feed roller 42, the roll paper feed roller 46, the first feed roller 44, and the manual feed roller 50 are a feed motor (not shown) (not shown). (Using a motor) so that the on / off control of the rotational drive can be performed at any time by an electromagnetic clutch attached to each roller. Here, when the printing operation is started by an instruction from the controller unit 14, the recording sheet selectively fed by any of the above-described paper feeding paths is conveyed to the first paper feeding roller 44. In order to remove skew of the recording paper,
In this paper feeding, after a predetermined amount of paper loop is formed on the recording paper, the first paper feeding roller 44 is turned on and driven to rotate, and then the recording paper is conveyed to the second paper feeding roller 52. Will be. A paper feed roller 64 disposed above the recording head 56 is disposed between the first paper feed roller 44 and the second paper feed roller 52.
The recording paper is slacked by a predetermined amount to form a buffer in order to perform an accurate paper feeding operation between the recording paper and the second paper feeding roller 52 disposed below. The buffer is provided with a buffer amount detection sensor 54 for detecting a buffer amount as a slack amount of the recording paper. Since the buffer is always formed on the recording paper while the paper is being conveyed, the load applied to the paper feed roller 64 and the second paper supply roller 52 particularly when conveying large-sized recording paper can be reduced. And an accurate paper feeding operation can be performed. In the printer unit 20 having the recording paper transport system as described above, when printing is performed by the recording head 56, the scanning carriage 58 on which the recording head 56 is mounted reciprocates on the carriage rail 60 by the scanning motor 62. Move
The scanning in the main scanning direction is performed. In the forward scan, the image is printed on the recording paper by the recording head 56, and in the backward scan, the paper feed roller 64 is printed.
As a result, a feeding operation in the sub-scanning direction for feeding a predetermined amount of recording paper is performed. Here, the feed amount along the sub-scanning direction is defined as a constant movement amount described later, and here, the recording head 55 is used.
, I.e., a length corresponding to the arrangement width of the suction holes formed over the surface of the platen 74 facing the recording head 56 (not shown). Is set. The suction holes are the same as the suction holes provided in the suction mechanism according to the related art described with reference to FIGS. 11A to 11C, and a description thereof will be omitted. On the other hand, at the time of scanning in this return path, while the buffer amount is detected via the buffer amount detection sensor 54, the drive control of the drive system by the paper feed motor 62 is set so as to always maintain the predetermined buffer amount. ing. Then, the printed recording paper is discharged to the paper discharge tray 66, and a series of printing operations is completed. (Configuration around operation carriage) Next, the configuration around the scanning carriage 58 will be described in detail with reference to FIG. In FIG. 3, a paper feed motor 68 is provided as a drive source for intermittently feeding the recording paper in the sub-scanning direction. The paper feed motor 68 can arbitrarily set and change the amount of rotation, and is configured to drive the second paper feed roller 52 via the paper feed roller 64 and the second paper feed roller clutch 70. ing. The above-described scanning motor 62 is provided as a drive source for scanning the scanning carriage 58 and scanning the main scanning direction indicated by arrows A and B via the belt 72.
In this embodiment, as described above, a pulse motor is used for the paper feed motor 68 and the scanning motor 62 because accurate paper feed control at an arbitrary feed amount is required. Here, when the recording paper reaches the second paper feed roller 52, the clutch 70 for the second paper feed roller and the paper feed motor 68 are turned on, respectively, until the leading end of the recording paper is nipped by the pair of paper feed rollers 64. Is transported on the platen 74. Then, the conveyed recording paper is fed to a paper detection sensor 76 provided on a platen 74.
Thus, it is detected that the sheet has been conveyed past the platen 74, and the sensor information is used for position control, jam control, and the like. When the leading end of the recording paper reaches the paper feed roller 64, the clutch 70 for the second paper feed roller and the paper feed motor 68 are respectively turned off, and then the inner space of the platen 74 becomes negative by the activation of a suction motor (not shown). Pressure is applied and the suction operation is started.
By such a suction operation, the recording paper is brought into close contact with the platen 74. Here, prior to the image printing operation on the recording paper, the scanning carriage 58 is moved to the position where the home position sensor 78 is provided, and then the forward scanning is performed in the direction of arrow A. In this forward scan, cyan C, magenta M, yellow Y, black K
Are ejected from the recording head 56 as appropriate to record (print) an image. When the image recording operation for a predetermined length along the main scanning direction is completed, the driving direction of the scanning motor 62 is reversed, and the scanning carriage 58 is moved in the direction shown by the arrow B, and the backward scanning is started. I do. Then, the scanning motor 62 is driven in reverse until the scanning carriage 58 returns to the position where the home position sensor 78 is provided. During this backward scanning, the paper feeding operation by the length along the sub-scanning direction recorded by the recording head 56 (that is, the width of the recording head 56) is performed by the paper feeding motor 68.
Is started, and the paper feed roller 64 is rotationally driven to perform the operation in the direction along the sub-scanning direction indicated by the arrow C. Here, although the details will be described later, the above-described paper feed amount, that is, the movement amount in the sub-scanning direction is not set only to the above-described width of the recording head 56, that is, only the constant movement amount. There is a case where it is set to the one-side movement amount defined by the width. In this embodiment, the recording head 56 is an ink jet nozzle of the type described above, and 256 nozzles are Y, M,
Assembled for each of C and K. On the other hand, when the scanning carriage 58 stops at the home position specified by the home position sensor 78, the recovery operation of the recording head 56 is performed. This recovery operation is a process for performing a stable recording operation, and in order to prevent unevenness at the start of ejection caused by a change in viscosity of ink remaining in the nozzles of the recording head 56, the sheet feeding time and the apparatus This is a process of performing each pressure operation on each nozzle of the recording head 56 according to pre-programmed conditions such as the internal temperature and the discharge time, and performing an idle discharge operation of ink from each nozzle. By repeating the above operation, the image is recorded over the entire surface of the recording paper. (System Configuration) Next, the processing and control of image signals by the control system in the digital color copying machine 10 of this embodiment will be described with reference to FIGS. 4A to 4C. In FIG. 4A, reference numeral 100 indicates a main CPU as a main controller that controls the entire apparatus. The main CPU 100 includes a printer control CPU 102 for controlling a printer, a reader control CPU 104 for controlling a reading operation, and a main image processing unit 10 for processing an image display operation.
6. The operation unit 108 as an input unit by the operator is connected. Here, the printer control CPU 102 and the reader control CPU 104
Is to control the printer and reader operations, respectively.
The main CPU is set in a master-slave relationship. The main image processing unit 106 is configured to perform processing such as edge enhancement smoothing, masking, black extraction, binarization, and trimming. Also, printer control
A synchronous memory 110 is connected to the CPU 102 and the main image processing unit 106. The synchronous memory 110 is configured to absorb the variation in the time of the input operation and to correct the delay due to the arrangement of the recording heads in the mechanism. This synchronous memory 110 is connected to a recording head 56 as an ink bubble jet head. On the other hand, the printer control CPU1
02 is connected to a printer unit drive system 114 that controls input drive of the printer. The reader control CPU 104 is connected to an input system image processing unit 116 that performs necessary correction processing in a reading system such as shading correction, color correction, and γ correction, and a reader unit driving system 118 that controls input driving of the reader. Have been. Further, the CCD line sensor 26 is connected to the above-described input image processing unit 116, and the input image processing unit 116 is connected to the above-described main image processing unit 106. Here, the reader unit 12 is composed of the main CPU 100, reader control CPU 104, main image processing unit 106, operation unit 108, input system image processing unit 116, reader unit driving system 118, and CCD line sensor 26 as an image sensor. It is configured. Also, the printer control CPU 102, the synchronous memory 110, the recording head 5
6, and the printer unit drive system 114 constitutes the printer unit 20. Next, the configuration of the main image processing unit 106 according to the present invention will be described with reference to FIG. In FIG. 5, 200 is RG
A log conversion unit for converting B luminance data into CMY density data, 201 is an edge enhancement and smoothing unit, 202 is a color conversion unit, 203 is a black extraction unit, 204 and 205 are masking units that correct output characteristics of a printer, γ A correction unit 206 is a binarizing unit that performs a binarizing process, and 207 is a trimming unit. Log converter 20
0, γ correction unit 205 is a look-up table,
Each of the two conversion tables can be set. For example, in the log conversion unit 200, the normal mode is set in the table 1 and the negative mode is set in the table 2, and this is switched by the edit signal 210. Similarly, in the γ correction unit, the normal mode is set in the table 1 and the photograph mode is set in the table 2, and the table is switched by the edit signal 213. The color conversion unit 202 performs processing such as a single color mode and a color conversion mode, and
Turn ON and OFF with. When set to ON, each mode set by the CPU in advance operates, and when set to OFF, the mode becomes through and a normal image flows. The trimming unit 202 performs a trimming process on the binary image signal using the edit signal 213. Edge enhancement, smoothing part
At 201, the image signal is 2 for the sake of the processing (the processing is performed using both data of the surrounding pixels as the target pixel).
Delay about line. Therefore, the edit signals 211, 212, 213
Need to be delayed accordingly, the delayed edit signal B is used. Reference numeral 220 denotes an image editing signal generation circuit that outputs the editing signals 211, 212, and 213. Next, a configuration example and timing of the edit signal generation circuit 220 shown in FIG. 5 will be described with reference to FIG. Timers 150, 153, 154, 155, 161, 171 and 172 are Intel's 8
255 programmable timer counter, m in the figure
ode indicates its operation mode, and detailed description of the operation is omitted since it is described in the manual. Timer 150, selector 151, D type F / F152, timer 15
3,154, D type F / F156,157, NOR gate 159, counter 1
64, a memory 163, a D type F / F 162, a D type F / F 158, timers 155, 161, an inverter 160, and an AND gate 165 are circuits for generating a BVE signal indicating an image effective section of main scanning. is there. The BVE signal is a gate signal to the timer 150 = the driving pulse clock of the main scanning motor 62 after the BTE signal (set by the CPU at the output port) is input = PM
After counting CK for a predetermined clock, the selector 151 selects the count-up output signal = PMTG signal or the signal of the sensor 78 disposed on the main scanning rail = PGS signal (signal RGS).
E) Yes. When the PMTG signal is selected, an image can be output based on an arbitrary moving distance of the reading system. When the RGS signal is selected, an image can be output based on the mounting position of the sensor. An example of a timing chart when the GTE signal is selected is shown in FIG. 6-b. The figure shows how the PMTG signal is generated after counting the number of clocks of the PMCK signal after the input of the GTE signal by the value set by the CPU. When the GTE signal is selected, the scanning time can be shortened because only a minimum approach (from the main scanning speed to the constant speed) is required from an arbitrary position on the document table. When the RGS signal is selected, accurate reading can be performed without being affected by vibration of the drive system. The two use them as needed. The circuit composed of the D type F / Fs 152, 156, 157 and the timers 153, 154 is a circuit for dividing the clock CLKA signal of a fixed frequency and delaying it for an arbitrary time from the trigger ITP signal. It is. In this embodiment, the range of the delay time can be finely changed over a wide range by using two timers 153 and 154. The HS1 signal output from the D-type F / F157 is a signal for initializing a synchronization signal / HS signal for controlling a CCD reading cycle, and loading of the counter 164 (count initialization in this case) is performed by the HS1 signal. Done. This makes it possible to make the image reading position for each main scan coincide with the accumulation time period of the CCD, thereby enabling an accurate reading operation. The counter 164 generates an HS signal (time period from the start of counting from the initial value to the count up), and the count value (Q output) is also used as an address signal for accessing the memory 163. A timing signal is written in the memory 163 in advance. After data is latched by the D-type F / F 162, a signal for timing control of the editing circuit is generated. Timer 155 counts the HS signal and sets the HS
A section signal for a signal pulse = BVEO signal is generated. The BVEO signal is generated by the timer 161 generating a signal delayed by a few pulses at the leading end, and the final main scanning section signal = BV
E signal. In this way, to cut the beginning of the BVEO signal,
This is in consideration of the delay of the cut image processing of the dust image when the CCD is subjected to the initialization operation, so that unnecessary images are not taken in the BVE signal effective section. The timing chart until the generation of the BVE signal is shown in FIG. Next, the edit signal generation block in the lower half of FIG. 6-a will be described. Timers 171 and 172 generate pulses when they count the HS signal and count a predetermined number of pulses. In this embodiment, the CP
In order to reduce the burden on U, the timers 171 and 172 operate alternately, so that the time from when the timer counts up to when one of the timers counts up is secured to allow the CPU to set the count value. The SR latch 170 is set (the Q output is 1) via the AND gate 168 by the BVEO signal. In this embodiment, when the BVEO signal is enabled, the timer 172 starts operating first. N when either timer 171 or 172 counts up
To the clock input of D type F / F167 via AND gate 173
A rising pulse of the BCHG signal is input, and an interrupt is requested to the CPU by the INTR signal at the Q output. When the CPU accepts the interrupt, it gives a negative pulse to the ICR * signal, clears the INTR signal, and prepares for the next interrupt. The CPU sets the count value in the timers 17 and 172 for each interrupt, and sets one address information of the plural edit timing data written in the memory 179 in advance as D.
Write to type F / F175. The address information written in the D type F / F 175 is latched by the D type F / F 176 at the next count-up of the timers 171 and 172. D type F / F176
In this embodiment, the edit timing data at address 0 is selected first because the data is cleared by the BVEO signal. The counter 177 is a counter that generates an address signal for accessing the editing timing data, and when the EDLD * signal is loaded from the D input address, the counting operation is repeated every cycle by the EDCK signal. The selector 178 is connected to the signal from the Q output of the counter 177 and the CPU.
The circuit for switching the address signal controls the select signal = MDS signal and sets the contents of the memory 179 in advance. The memory 179 uses a random access memory in this embodiment, and divides the memory space into a plurality of blocks and stores necessary editing timing data for each block. The contents of the memory 179 are rewritten via the bus transceiver 182. At the time of image editing, the input A of the selector 178 is selected, and the timing signal read from the memory is transmitted to the D-type F / F180.
And the edit signal A is sent to the image processing circuit as the edit signal B via the line delay circuit 181. This is because the generation of the EDLD * signal and the EDCK signal in the memory 163 makes it possible to access the memory 179 only in an arbitrary section and a necessary portion between the HS signals, thereby reducing the memory capacity of the memory 179. This is shown in the timing signal section of FIG. 6-c. Further, in the color copying machine to which the present invention is applied, one pixel data is separated into Y, M, C, and Bk components, and this is processed serially four clocks of the VCK signal. By dividing the frequency and using a signal having a cycle of four clocks of the VCK signal, the memory capacity of the memory 179 can be further reduced. FIG. 6-d shows an operation timing chart of the editing signal generator described above. It can be seen that the CPU can be controlled with a margin. Next, in one embodiment of the present invention, the operation procedure of each of the above-described circuits is described by the main CPU 100, the printer control CPU 102, and the reader control.
The contents of the procedure of the copy sequence executed in the CPU 104 will be described with reference to FIGS. 7 to 10. First, the scanning unit 10
When the start key 8 (shown in FIG. 4) is pressed, the copy sequence task is called and the processing is started. First, in step 1, a copy area is set based on data such as a document size, a scaling ratio, a paper size, and an area designated by the operation unit 108. Here, the area designation is a function of performing a specific image processing only in an arbitrary area in a document by setting a coordinate value of a certain area and an image processing method in the area by an operation unit. As an example, in FIG. 9, area 1 is a cyan single color mode for outputting an image in cyan single color, area 2 is a negative-positive inversion mode, and area 3
FIG. 6 is a diagram showing a state after setting an image in a masking mode for setting a white area in an area to a masking mode. Next, in step 2, data required for initial setting is transmitted to the reader control CPU, that is, initial communication to the reader unit 12 is executed. In step 3, printer control
Data necessary for the initial setting is transmitted to the CPU 102. In the subsequent STEP 4, an area information set for calculating area information in one scan is performed. This will be described in detail with reference to FIG. First, in STEP 4-1 in FIG. 8, the area existing in the current line is determined. For example, in the scan line 1 in FIG. 9A, area 0, which is the entire original document, and area 1,
Since all of 2 and 3 are included, register these. Then S
In TEP4-2, as shown in FIG. 9B, one line is divided for each boundary of the registered area and a

[0], a [1], ... a
[N] small area is formed. For example, area a [3]
In, the upper half 128 pixels are a normal image and the lower half is a negative image. In the following STEP4-3, small area a [n]
Edit interval int corresponding to width of int

[0], int
[1],... Int [n] are calculated. Further, in STEP 4-6, information responding to the small area a [n] is written in the editing memory 179. For example, at the time of the l scan line in FIGS. 9A and 9B, a

For [0], a [2], a [4], a [6], area 0, that is, normal image processing setting is performed for 270 images. For a [1], the color conversion unit 20 in FIG.
For the setting to turn on 2 and the setting for setting the bank of the log conversion unit to the negative side for a [3], the lower half 128 pixels, a [5]
Is set to turn on the image trimming unit 207. Therefore, the relationship between information and addresses in the edit memory is as shown in FIG. 9C. Next, in STEP 4-5, the timer 172 shown in FIG.
Int to timer 173

The values of [0] and int [1] are set respectively. When the BVEO shown in FIG. 6 is in the active state, that is, when the main scanning scan operation starts and the image starts flowing, the timer 172 first sets the HS int.

After counting [0] times, an interrupt signal is generated in the main CPU, and then the timer 171 operates for HS int [1]. Finally, in STEP 4-6, an edit memory address in which information corresponding to a [1] is written is set in the address latch 175. In the example shown in FIG. 9, 270 is set, and the memory 179 is set for each interrupt signal generated by the timers 171 and 172.
Is loaded to the address. After the processing in STEP 4 is completed, the process proceeds to STEP 5 to perform image processing parameter setting. Here, the edge enhancement unit 201, the color conversion unit 202, the masking unit 204, the γ correction unit 205,
Parameters relating to image processing, such as the binarization unit 206, are set. In the example of FIG. 9, since the cyan monochromatic mode is designated in the area 1, when the color conversion unit 202 is turned on by the edit signal, the parameters are set so as to be in the mode. Next, after waiting for the reader unit and the printer unit to enter the scan ready state in STEP 6, a start signal is transmitted to each of the reader and the printer in step 7 so as to synchronize them. When main scan scan starts and BVEO goes high, timer 17
2 starts counting up. int

[0] When the count is completed, an interrupt signal INTR is generated from the FIF 167 to the CPU, whereby the interrupt processing in STEP 8 is performed. This is described in detail in FIG. In FIG. 10, in STEP 8-1, the timer 171,172
Is determined, if the timer 171 is, STEP8-2
If the next interval int [x] is not set in the timer 171, the timer 172 is set in STEP 8-3. Next, the next edit memory address is set in the address latch 175 in STEP8-4, and the interrupt clear signal I is set in STEP8-5.
By turning CR * ON and OFF, the interrupt signal INTR is cleared and the interrupt processing ends. Thereafter, this process is repeated until the end of the main scanning scan. In the example in FIG. 9B, the timer 172 is set to int

[0]
After the count is completed, an interrupt is generated, the memory address corresponding to a [1] is loaded, and the timer 171 operates. Here, the timer 172 has int [2], and the address latch 175 has a
The memory address for [2] is set, and the process is similarly performed until a [6] is reached. The end of the main scanning scan is determined in STEP11, and after the end, STEP
Proceeding to 12, it is determined whether or not all area scanning has been completed, and if not completed, the process returns to STEP 4, and if so, the copying operation is completed. As described above, the present embodiment is a circuit for generating an image editing signal for operating an image editing signal, and operates in a section required by an applicable image processing circuit to generate an image editing signal. This relates to an editing signal, and means for operating the image processing circuit in a section is not limited. For example, a memory is used in the above-described embodiment as means for generating the signals EDLD * and EDCK for operating the editing circuit, but this may be replaced by hard logic. Further, in this embodiment, an example in which the present invention is applied to a digital color copying machine has been described. However, the present invention is not limited to this application. May be applied. As described above, the embodiment is a circuit for generating an image editing signal for operating an image signal, and generating an image editing signal according to a delay of an image processing unit to be applied. The present invention relates to a circuit, and means for delaying an image editing signal is not limited at all. In this embodiment, one line delay is provided.
It is also conceivable to provide a plurality of delay means to cope with a more complicated hardware configuration. In this embodiment, an example in which the present invention is applied to a digital color copying machine has been described. However, the present invention is not limited to such an application as described above. As described above, according to the present embodiment, a circuit that generates an image editing signal in real time generates an image editing signal in which pixels and lines are delayed according to an applied image processing circuit. By doing so, there is an effect that it is possible to perform complicated image editing which has not been performed conventionally. [Effects of the Invention] The present invention is an image processing apparatus in which an image processing unit including an image processing unit including a line delay and an image processing unit other than the image processing unit including the line delay are sequentially connected. And an edit signal generating means for generating a signal for instructing a switching of a processing mode in an image processing section other than the image processing section including the line delay, and a signal generated by the edit signal generating means. The method of delaying the signal generated by the editing signal generating means is changed according to whether the signal is output to the image processing unit including the line delay or to the image processing unit other than the image processing unit including the line delay. Therefore, when the image signals are sequentially processed by the image processing unit including the line delay and the image processing units other than the image processing unit including the line delay, the mode switching is performed with good timing. It becomes reliably possible to realize becomes image editing to be performed and can.

[Brief description of the drawings]

FIG. 1 is a perspective view showing the appearance of an apparatus according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of the apparatus shown in FIG. 1, FIG. FIG. 5 is a block diagram showing the configuration of the processing unit 116 shown in FIG. 4, and FIG. 6-a is a block diagram of the image editing signal generating circuit shown in FIG. FIGS. 6B, 6C, and 6D are timing charts showing the operation of the circuit shown in FIG. 6A, and FIGS. 7, 8, and 10 are diagrams of the main CPU 209 shown in FIG. 9A, 9B, and 9C are diagrams illustrating the operation of the image editing signal generation circuit shown in FIG. 6-a. 208 ... Reader CPU 209 ... Main CPU 211 ... Edit signal A 212 ... Edit signal B 163,179 ... Memory

Claims (1)

(57) [Claims] 1. An image processing apparatus comprising: an image processing unit including an image processing unit including a line delay; and an image processing unit other than the image processing unit including a line delay. And an edit signal generating means for generating a signal for instructing a switching of a processing mode in an image processing unit other than the image processing unit including the line delay, and a signal generated by the edit signal generating means, Or a method of delaying a signal generated by the editing signal generating means according to whether to output to an image processing unit other than the image processing unit including the line delay or to an image processing unit other than the image processing unit including the line delay. Image processing device.