JP2858569B2 - Chip type device mounting method and device manufactured by the mounting method - Google Patents
Chip type device mounting method and device manufactured by the mounting methodInfo
- Publication number
- JP2858569B2 JP2858569B2 JP8313308A JP31330896A JP2858569B2 JP 2858569 B2 JP2858569 B2 JP 2858569B2 JP 8313308 A JP8313308 A JP 8313308A JP 31330896 A JP31330896 A JP 31330896A JP 2858569 B2 JP2858569 B2 JP 2858569B2
- Authority
- JP
- Japan
- Prior art keywords
- type device
- chip
- cavity
- resin
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/10175—Flow barriers
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体チップや弾性
表面波チップ等のチップ型デバイスの実装方法及びそれ
により製造するデバイスに関し、特にフリップチップ実
装されたチップ型デバイスの封止実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a chip-type device such as a semiconductor chip or a surface acoustic wave chip and a device manufactured by the same, and more particularly to a method for sealing and mounting a chip-type device mounted on a flip chip.
【０００２】[0002]
【従来の技術】従来のチップ型デバイスの実装方法にお
いて、特開昭６０−１８９９９２号公報では、基板上に
形成されるランド部が一段下がっていることを特徴とす
るフリップチップ実装方法が示されている。2. Description of the Related Art In a conventional mounting method of a chip type device, Japanese Patent Application Laid-Open No. 60-18992 discloses a flip chip mounting method characterized in that a land formed on a substrate is lowered by one step. ing.
【０００３】図５は、その実装方法の一例を示す断面図
である。基板２３の表面には、凹部２９が形成されてお
り、この凹部２９内にはランド２５が設けられている。
チップ型デバイス２１はバンプ２４を介してランド２５
に実装されたとき、チップ型デバイス２１の表面全体が
基板２３の表面に接触する構造となっている。FIG. 5 is a sectional view showing an example of the mounting method. A concave portion 29 is formed on the surface of the substrate 23, and a land 25 is provided in the concave portion 29.
The chip type device 21 is connected to the land 25 via the bump 24.
When mounted on the substrate 23, the entire surface of the chip-type device 21 comes into contact with the surface of the substrate 23.
【０００４】[0004]
【発明が解決しようとする課題】第１の問題点は、チッ
プ型デバイスの中で弾性表面波デバイスを基板上に搭載
したときに所望の特性が得られないことにある。A first problem is that desired characteristics cannot be obtained when a surface acoustic wave device is mounted on a substrate in a chip type device.
【０００５】その理由は、特開昭６０−１８９９９２号
公報では、チップ型デバイス全面が基板表面に接してし
まうためである。The reason is that, in Japanese Patent Application Laid-Open No. 60-189998, the entire surface of the chip type device comes into contact with the substrate surface.
【０００６】第２の問題点は樹脂封止を行わないため信
頼性上の問題があることにある。The second problem is that there is a problem in reliability because resin sealing is not performed.
【０００７】その理由は、特開昭６０−１８９９９２号
公報ではチップ型デバイス周辺部と基板との間が封止さ
れていないために気密が保てず、接合面に腐食等が起こ
る可能性があるためである。[0007] The reason is that in Japanese Patent Application Laid-Open No. 60-189998, airtightness cannot be maintained because the periphery of the chip type device and the substrate are not sealed, and there is a possibility that corrosion or the like may occur on the joint surface. Because there is.
【０００８】本発明の目的は、チップ型デバイスを封止
するために封止樹脂を用い、基板との間に少なくとも空
間を有する封止構造を得るチップ型デバイスの実装方法
を提供することにある。An object of the present invention is to provide a method of mounting a chip-type device by using a sealing resin for sealing the chip-type device and obtaining a sealing structure having at least a space between the chip-type device and the substrate. .
【０００９】本発明の他の目的は、チップ型デバイス実
装部の小型化を可能とするため、封止樹脂の広がりを抑
えるチップ型デバイスの実装方法を提供することにあ
る。Another object of the present invention is to provide a method of mounting a chip-type device, which suppresses the spread of a sealing resin so that the chip-type device mounting portion can be reduced in size.
【００１０】[0010]
【課題を解決するための手段】本発明のチップ型デバイ
スの実装方法は、搭載すべきチップ型デバイスの下部に
封止樹脂を導くキャビティを設けてなる基板に前記チッ
プ型デバイスを樹脂封止し前記チップ型デバイスと前記
基板との間に少なくとも空間を有して実装し、前記封止
樹脂は、前記キャビティの周囲に前記基板の表面より下
部に設けた凹部から供給され、この凹部と前記キャビテ
ィとの間に存する壁により前記キャビティへの流入制御
がなされるようになっている。According to a method of mounting a chip-type device of the present invention, the chip-type device is resin-sealed on a substrate having a cavity for guiding a sealing resin below a chip-type device to be mounted. The chip type device and the substrate are mounted with at least a space therebetween, and the sealing resin is supplied from a recess provided below the surface of the substrate around the cavity, and the recess and the cavity are provided. The flow existing in the cavity is controlled by a wall existing between the cavity.
【００１１】また、本発明の実装方法により製造するデ
バイスは、搭載すべきチップ型デバイスの下部に封止樹
脂を導くキャビティと、このキャビティの周囲にて表面
より下部に設けた封止樹脂供給用の凹部と、この凹部か
ら前記キャビティへの前記封止樹脂の流入を制御する壁
とを有してなる基板を備え、前記チップ型デバイスを前
記基板の前記キャビティ上に搭載して前記封止樹脂によ
り封止し前記チップ型デバイスと前記基板との間に少な
くとも空間を有して実装する実装方法により製造され
る。A device manufactured by the mounting method according to the present invention includes a cavity for guiding a sealing resin to a lower portion of a chip-type device to be mounted, and a sealing resin supply portion provided around the cavity and below the surface. A substrate having a recess and a wall for controlling the flow of the sealing resin from the recess into the cavity, wherein the chip-type device is mounted on the cavity of the substrate and the sealing resin is provided. , And is manufactured by a mounting method of mounting with at least a space between the chip-type device and the substrate.
【００１２】即ち、本発明のチップ型デバイスの実装方
法は、チップ型デバイス（図１の１）の空間と過剰供給
された封止樹脂（図１の２）を引き込む役割を果たすキ
ャビティ（図１の１０）を有する。より詳細には、基板
（図１の３）の表面より低い位置にチップ型デバイス
（１）搭載部と封止樹脂（２）の供給部を兼ねた凹部
（図１の９）を有し、凹部（９）に溜まる樹脂（２）の
量を一定にする役割を果たす壁（図１の１１）及びチッ
プ型デバイス（特に、弾性表面波デバイス）に必要な空
間と一定量以上の樹脂の溜まり用プールの役割を果たす
キャビティ（１０）を有することを特徴とする。That is, in the method of mounting a chip-type device according to the present invention, a cavity (FIG. 1) serving to draw in the space of the chip-type device (1 in FIG. 1) and the sealing resin (2 in FIG. 1) supplied excessively. 10). More specifically, a recess (9 in FIG. 1) serving as a chip-type device (1) mounting portion and a supply portion of a sealing resin (2) is provided at a position lower than the surface of the substrate (3 in FIG. 1). The space (11 in FIG. 1) and the space required for a chip-type device (particularly, a surface acoustic wave device) serving to make the amount of the resin (2) accumulated in the recess (9) constant, and the accumulation of the resin of a certain amount or more. It has a cavity (10) which plays the role of a pool for use.
【００１３】このような本発明においては、基板（３）
はチップ型デバイス（１）搭載箇所及び樹脂（２）供給
部となり、基板（３）表面より低い位置に形成される凹
部（９）、樹脂（２）供給後にチップ型デバイス（特
に、弾性表面波デバイス）に必要な空間をなすキャビテ
ィ（１０）と、キャビティ（１０）と凹部（９）を隔
て、凹部（９）に溜まる樹脂（２）の量を一定にする壁
（１１）で構成されている。これによって、基板（３）
にチップ型デバイス（１）を搭載した後に樹脂（２）を
樹脂供給部に供給した時、壁（１１）によって凹部
（９）に一定量の樹脂（２）がせき止められ、過剰供給
分の樹脂（２）がキャビティ（１０）底部に流出して溜
められるため、チップ表面に空間を得ることができる。In the present invention, the substrate (3)
Represents a mounting portion of the chip-type device (1) and a supply portion of the resin (2), a concave portion (9) formed at a position lower than the surface of the substrate (3), And a wall (11) separating the cavity (10) and the concave portion (9) and keeping the amount of the resin (2) accumulated in the concave portion (9) constant. I have. Thereby, the substrate (3)
When the resin (2) is supplied to the resin supply unit after the chip type device (1) is mounted on the resin, a certain amount of the resin (2) is blocked by the wall (11) in the concave portion (9), and the excess resin is supplied. Since (2) flows out to the bottom of the cavity (10) and is accumulated, a space can be obtained on the chip surface.
【００１４】[0014]
【発明の実施の形態】次に、本発明について図面を参照
して説明する。Next, the present invention will be described with reference to the drawings.
【００１５】本発明の第１の実施の形態を図１ないし図
３に示し、図１（ａ），（ｂ）はこの実施の形態におけ
る基板の平面図と断面図、図２はチップ型デバイス搭載
後の平面図、図３は基板の凹部の一例を示す断面図であ
る。1 to 3 show a first embodiment of the present invention. FIGS. 1 (a) and 1 (b) are a plan view and a sectional view of a substrate in this embodiment, and FIG. 2 is a chip type device. FIG. 3 is a plan view after mounting, and FIG. 3 is a cross-sectional view illustrating an example of a concave portion of the substrate.
【００１６】図１を参照すると、基板３には、凹部９と
キャビティ１０が形成されている。凹部９はランド５を
有しており、チップ型デバイス１上の電極パッド６に形
成されたバンプ４と接続される。凹部９の深さは、チッ
プ型デバイス１のバンプ形成面が基板３上面より±数１
０μｍの範囲になるように形成されている。図２を参照
すると、凹部９の幅はチップ型デバイス１が搭載された
後に窪みが多少見える程度、例えばチップ型デバイス１
搭載後に凹部が５００μｍ見える幅で設けられ、封止用
の樹脂２供給口となる。Referring to FIG. 1, a concave portion 9 and a cavity 10 are formed in a substrate 3. The recess 9 has a land 5 and is connected to the bump 4 formed on the electrode pad 6 on the chip type device 1. The depth of the concave portion 9 is such that the bump forming surface of the chip-type device 1 is
It is formed to have a range of 0 μm. Referring to FIG. 2, the width of the recess 9 is such that the recess is somewhat visible after the chip device 1 is mounted, for example, the chip device 1.
After mounting, the concave portion is provided with a width that can be seen at 500 μm, and serves as a resin 2 supply port for sealing.
【００１７】図３を参照すると、凹部９の深さがバンプ
４の高さより浅い、例えば２０〜３０μｍ浅い場合、窪
みが見える辺は四辺のうち一辺だけでもよい。封止用の
樹脂２は凹部９の樹脂２供給口より供給され、バンプ
４，ランド５，電極パッド６を封止する。キャビティ１
０は凹部９と同程度あるいはそれ以上深くする。壁１１
は凹部９とキャビティ１０を隔てており、凹部９に留ま
る樹脂２を一定にする働きをする。一定量以上の樹脂２
は壁１１とチップ型デバイス１の隙間の通り、キャビテ
ィ１０に流れ込む。壁１１と搭載後のチップ型デバイス
１間は多少の隙間、例えば２０μｍの隙間を有してい
る。キャビティ１０は、壁１１の樹脂流入制御により、
樹脂２の溜まり用のプール及びチップ型デバイス１の空
間となる。Referring to FIG. 3, when the depth of the recess 9 is shallower than the height of the bump 4, for example, 20 to 30 μm, only one of the four sides may be visible. The sealing resin 2 is supplied from the resin 2 supply port of the concave portion 9 and seals the bumps 4, lands 5, and electrode pads 6. Cavity 1
0 is the same as or larger than the recess 9. Wall 11
Separates the recess 9 from the cavity 10 and serves to make the resin 2 remaining in the recess 9 constant. More than a certain amount of resin 2
Flows into the cavity 10 through the gap between the wall 11 and the chip-type device 1. There is a slight gap between the wall 11 and the mounted chip type device 1, for example, a gap of 20 μm. The cavity 10 is controlled by resin inflow of the wall 11.
A pool for the resin 2 and a space for the chip-type device 1.
【００１８】次に、この第１の実施の形態の動作につい
て、図を参照して説明する。Next, the operation of the first embodiment will be described with reference to the drawings.
【００１９】封止用の樹脂２は凹部９の樹脂２供給口か
ら凹部９に供給される。樹脂２は壁１１によりせき止め
られ、凹部９とチップ型デバイス１の間を封止する。封
止後、樹脂２の過剰供給分は基板３表面より下部にある
壁１１とチップ型デバイス１の隙間を通り、キャビティ
１０へ流出し、キャビティ１０底辺へ至る。The sealing resin 2 is supplied to the recess 9 from the resin 2 supply port of the recess 9. The resin 2 is dammed by the wall 11 and seals between the recess 9 and the chip type device 1. After the sealing, the excess supply of the resin 2 flows through the gap between the wall 11 below the surface of the substrate 3 and the chip type device 1, flows out into the cavity 10, and reaches the bottom of the cavity 10.
【００２０】次に、本発明の第２の実施の形態について
説明する。Next, a second embodiment of the present invention will be described.
【００２１】図４（ａ），（ｂ），（ｃ）は第２の実施
の形態における平面図及び破断部の異なる二つの断面図
である。FIGS. 4 (a), 4 (b) and 4 (c) are a plan view and two cross-sectional views showing different break portions in the second embodiment.
【００２２】図４を参照すると、基板１３の凹部９内に
ランド５及び溝１２が形成される。凹部９内に形成され
るランド５は凹部９底部より上部に、例えば４０μｍ上
部に設けられ、ランド５間に溝１２が構成される。ラン
ド５の深さは、チップ型デバイス１のバンプ形成面が基
板３上面より±数１０μｍの範囲になるように形成され
ている。溝１２の底部は、凹部９の底部と同じもしくは
多少低く、例えば４０μｍ低い位置に、キャビティ１０
に向かって形成される。封止用の樹脂２は、凹部９の樹
脂２供給口に供給され、バンプ４，ランド５，電極パッ
ド６を封止する。壁１１は凹部９、ランド５、溝１２と
キャビティ１０を隔てており、凹部９に溜まる樹脂を一
定にする働きをする。一定量以上の樹脂２は壁１１とチ
ップ型デバイス１の隙間を通り、キャビティ１０に流れ
込む。Referring to FIG. 4, a land 5 and a groove 12 are formed in a recess 9 of a substrate 13. The land 5 formed in the recess 9 is provided above the bottom of the recess 9, for example, above 40 μm, and a groove 12 is formed between the lands 5. The depth of the land 5 is formed such that the bump forming surface of the chip type device 1 is within a range of ± several tens of μm from the upper surface of the substrate 3. The bottom of the groove 12 is the same as or slightly lower than the bottom of the recess 9, for example, at a position lower by 40 μm.
Formed towards. The sealing resin 2 is supplied to the resin 2 supply port in the recess 9 to seal the bumps 4, lands 5, and electrode pads 6. The wall 11 separates the cavity 9 from the recess 9, the land 5, the groove 12, and functions to keep the resin accumulated in the recess 9 constant. A certain amount or more of the resin 2 flows into the cavity 10 through the gap between the wall 11 and the chip type device 1.
【００２３】このような第２の実施の形態によれば、ラ
ンド５間に溝１２を多く設けることにより、凹部９へ供
給される樹脂２の量が多くなるため、上述した第１の実
施の形態に比べ、バンプ４、ランド５、電極パッド６の
封止・保護力を強固にすることができる利点がある。According to the second embodiment, by providing a large number of grooves 12 between the lands 5, the amount of the resin 2 supplied to the concave portion 9 is increased. There is an advantage that the sealing / protective force of the bumps 4, the lands 5, and the electrode pads 6 can be increased as compared with the form.
【００２４】また、請求項３に対応する実施の形態とし
ては、上記にて説明した第１及び第２の実施の形態のご
とき構成とすることにより、図１に示すデバイス１４、
ならびに図４に示すデバイス１５がそれぞれ得られるこ
とから、詳細な説明を省略する。Further, as an embodiment corresponding to the third aspect, by adopting the configuration as in the first and second embodiments described above, the device 14 shown in FIG.
In addition, since the device 15 shown in FIG. 4 is obtained, detailed description is omitted.
【００２５】次に本発明の実施例について図面を参照し
て説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【００２６】図１を参照すると、チップ型デバイス１の
形状が６ｍｍ角、高さ４００μｍの時、厚さ１ｍｍのガ
ラスセラミック基板３上の凹部９は深さが１５０μｍ
で、内部のランド５は厚さ２０μｍ、幅１００μｍの銀
で形成される。ランド５は表面が厚さ１μｍの金メッキ
で覆われている。チップ型デバイス１上の電極パッド６
に形成されるバンプ４は高さが５０μｍの金で形成され
る。チップ型デバイス１がバンプ４を介して基板３と接
続されたとき、凹部９はチップ型デバイス１の一辺から
５００μｍの隙間を開け、樹脂２供給口となる。壁１１
は、凹部９底辺から５０μｍの高さで形成されており、
チップ型デバイス１搭載後、チップ型デバイス１との隙
間は２０μｍとなる。キャビティ１０はチップ型デバイ
ス１搭載部中央に３６ｍｍ角、深さ４００μｍで形成さ
れ、底辺にパターン７、グラウンド８が形成される。封
止用の樹脂２には電気絶縁性の樹脂が使用され、凹部９
とチップ型デバイス１間を封止する。Referring to FIG. 1, when the chip type device 1 has a shape of 6 mm square and a height of 400 μm, the recess 9 on the glass ceramic substrate 3 having a thickness of 1 mm has a depth of 150 μm.
The inner land 5 is formed of silver having a thickness of 20 μm and a width of 100 μm. The surface of the land 5 is covered with gold plating having a thickness of 1 μm. Electrode pad 6 on chip type device 1
Is formed of gold having a height of 50 μm. When the chip-type device 1 is connected to the substrate 3 via the bumps 4, the concave portion 9 opens a gap of 500 μm from one side of the chip-type device 1 and becomes a resin 2 supply port. Wall 11
Is formed at a height of 50 μm from the bottom of the concave portion 9,
After mounting the chip type device 1, the gap with the chip type device 1 becomes 20 μm. The cavity 10 is formed at the center of the mounting portion of the chip-type device 1 with a size of 36 mm square and a depth of 400 μm, and a pattern 7 and a ground 8 are formed at the bottom. As the sealing resin 2, an electrically insulating resin is used.
And the chip type device 1 are sealed.
【００２７】次に、本発明の実施例の動作について図面
を参照して説明する。Next, the operation of the embodiment of the present invention will be described with reference to the drawings.
【００２８】図１を参照すると、封止用の樹脂２はチッ
プ型デバイス１搭載後の凹部９の５００μｍの上部隙間
より供給される。樹脂２は壁１１に沿って凹部９内を充
填する。壁１１とチップ型デバイス１の隙間は基板３の
表面より下方にあるため、樹脂２は凹部９充填後、壁１
１とチップ型デバイス１の隙間２０μｍを通り、キャビ
ティ１０へ流出する。Referring to FIG. 1, the sealing resin 2 is supplied from the upper gap of 500 μm in the recess 9 after the chip type device 1 is mounted. The resin 2 fills the recess 9 along the wall 11. Since the gap between the wall 11 and the chip type device 1 is below the surface of the substrate 3, the resin 2
The liquid flows out of the cavity 10 through a gap 20 μm between the device 1 and the chip type device 1.
【００２９】[0029]
【発明の効果】第１の効果は、チップ型デバイスを封止
するために封止樹脂を用い、空間を有する封止構造を得
ることが可能になるということである。A first effect is that a sealing structure having a space can be obtained by using a sealing resin for sealing a chip type device.
【００３０】その理由は、チップ型デバイス搭載箇所に
凹部、キャビディ及び壁を設けることにより樹脂の流動
を制御したからである。The reason is that the flow of the resin is controlled by providing a concave portion, a cavity, and a wall at the mounting position of the chip type device.
【００３１】第２の効果は、チップ型デバイス実装部の
小型化を可能にしたことである。The second effect is that the chip-type device mounting portion can be reduced in size.
【００３２】その理由は樹脂の供給箇所を基板表面より
下部にし、樹脂供給量が多いとき、壁とチップ型デバイ
スの隙間よりキャビティへ流入するようにしたからであ
る。The reason for this is that the resin supply point is located below the substrate surface, and when the resin supply amount is large, the resin flows into the cavity from the gap between the wall and the chip-type device.
【００３３】[0033]
【図１】本発明の第１の実施の形態における基板を示
し、（ａ）は平面図、（ｂ）は同図（ａ）のａ−ａ′線
による断面図である。FIGS. 1A and 1B show a substrate according to a first embodiment of the present invention, wherein FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line aa ′ of FIG.
【図２】第１の実施の形態におけるチップ型デバイス搭
載後を示す平面図である。FIG. 2 is a plan view showing a state after mounting a chip-type device in the first embodiment.
【図３】第１の実施の形態における基板の凹部の幅の一
例を示す断面図である。FIG. 3 is a cross-sectional view illustrating an example of a width of a concave portion of the substrate according to the first embodiment.
【図４】本発明の第２の実施の形態における基板を示
し、（ａ）は平面図、（ｂ）及び（ｃ）はそれぞれ同図
（ａ）のｂ−ｂ′線による断面図及びｃ−ｃ′線による
断面図である。4A and 4B show a substrate according to a second embodiment of the present invention, wherein FIG. 4A is a plan view, FIGS. 4B and 4C are cross-sectional views taken along the line bb 'in FIG. It is sectional drawing by the -c 'line.
【図５】従来の実施方法の一例を示す断面図である。FIG. 5 is a sectional view showing an example of a conventional implementation method.
１，２１ チップ型デバイス ２ 封止用樹脂 ３，１３，２３ 基板 ４，２４ バンプ ５，２５ ランド ６，２６ 電極パッド ７ 配線パターン ８ グラウンド ９，２９ 凹部 １０ キャビティ １１ 壁 １２ 溝 １４，１５ デバイス 1,21 chip type device 2 sealing resin 3,13,23 substrate 4,24 bump 5,25 land 6,26 electrode pad 7 wiring pattern 8 ground 9,29 recess 10 cavity 11 wall 12 groove 14,15 device
Claims (2)
止樹脂を導くキャビティを設けてなる基板に前記チップThe chip is provided on a substrate provided with a cavity for guiding a resin.
型デバイスを樹脂封止し前記チップ型デバイスと前記基The chip type device and the base are sealed with resin.
板との間に少なくとも空間を有して実装し、前記封止樹Mounting with at least a space between
脂は、前記キャビティの周囲に前記基板の表面より下部The grease is located below the surface of the substrate around the cavity.
に設けた凹部から供給され、この凹部と前記キャビティAnd the cavity and the cavity
との間に存する壁により前記キャビティへの流入制御がControl of the flow into the cavity by the wall between
なされることを特徴とするチップ型デバイスの実装方How to mount a chip-type device characterized by what is done
法。Law.
止樹脂を導くキャビティと、このキャビティの周囲にてAround the cavity to guide the resin and around this cavity
表面より下部に設けた封止樹脂供給用の凹部と、この凹A recess for supplying the sealing resin provided below the surface,
部から前記キャビティへの前記封止樹脂の流入を制御すControlling the flow of the sealing resin from the section into the cavity.
る壁とを有してなる基板を備え、前記チップ型デバイスThe chip type device, comprising a substrate having
を前記基板の前記キャビティ上に搭載して前記封止樹脂Is mounted on the cavity of the substrate, and the sealing resin
により封止し前記チップ型デバイスと前記基板との間にSealed between the chip-type device and the substrate
少なくとも空間を有して実装する実装方法により製造すIt is manufactured by a mounting method that has at least a space.
ることを特徴とするデバイス。Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8313308A JP2858569B2 (en) | 1996-11-25 | 1996-11-25 | Chip type device mounting method and device manufactured by the mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8313308A JP2858569B2 (en) | 1996-11-25 | 1996-11-25 | Chip type device mounting method and device manufactured by the mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10154859A JPH10154859A (en) | 1998-06-09 |
| JP2858569B2 true JP2858569B2 (en) | 1999-02-17 |
Family
ID=18039665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8313308A Expired - Fee Related JP2858569B2 (en) | 1996-11-25 | 1996-11-25 | Chip type device mounting method and device manufactured by the mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2858569B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000223530A (en) * | 1999-02-03 | 2000-08-11 | Matsushita Electric Ind Co Ltd | Flip-chip bonded device and mounting method |
| JP4736948B2 (en) * | 2006-05-22 | 2011-07-27 | 株式会社デンソー | Electronic component mounting method |
| WO2008078746A1 (en) * | 2006-12-26 | 2008-07-03 | Panasonic Corporation | Semiconductor element mounting structure and semiconductor element mounting method |
| JP6704175B2 (en) * | 2016-01-27 | 2020-06-03 | パナソニックＩｐマネジメント株式会社 | LED module and lighting fixture using the same |
-
1996
- 1996-11-25 JP JP8313308A patent/JP2858569B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10154859A (en) | 1998-06-09 |
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