JP2857554B2 - Sensor characteristic adjustment circuit and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sensor characteristic adjusting circuit and a method used for adjusting characteristics of a semiconductor sensor output.

[0002]

FIG. 9 is a circuit diagram of a conventional sensor characteristic adjusting circuit. The output of the semiconductor sensor 1 is connected to the inverting input terminal of the operational amplifier 2 via the resistor 3. The variable resistor 4 is connected between the inverting input terminal and the output terminal of the operational amplifier 2. A resistor 7 and a variable resistor 8 are connected in series between the reference power supply 5 and the ground 6. The positive input terminal of the operational amplifier 2 is connected between the resistor 7 and the variable resistor 8.

Next, the operation of the circuit shown in FIG. 9 will be described.
The output voltage of the semiconductor sensor 1 is Vs, the output voltage of the operational amplifier 2 is Vo, the resistance of the resistor 3 is R3, the variable resistance of the variable resistor 4 is R4, and the input voltage to the positive input terminal of the operational amplifier 2 is Vp. Then, Vo can be expressed as Vo = Vp (1 + R4 / R3) -Vs (R4 / R3).

Assuming that the variable resistance value of the variable resistor 8 is R8, Vp is as follows: Vp = Vref (R8. (R7 + R8)). Therefore, the output voltage Vo of the operational amplifier 2 is as follows: Vo = Vref (R8. (R7 + R8)) (1 + R4 / R3) -Vs (R4 / R3) Here, the first term on the right side represents the offset set value of the sensor characteristic adjustment circuit, and the second term represents the sensitivity setting.

[0005] For example, when the output voltage of the semiconductor sensor 1 is 0, the right side of the last equation is only the first term, and
The term is always constant since it does not depend on Vs. Therefore the first
The term is an offset of the sensor characteristic adjustment circuit. Also the second
The term is proportional to the output Vs of the semiconductor sensor 1 and represents the sensitivity of the sensor characteristic adjustment circuit. Therefore, even if the sensitivity of the output Vs of the semiconductor sensor 1 varies, the output Vo of the operational amplifier 2 (that is, the output of the sensor characteristic adjustment circuit) can be adjusted to a predetermined sensitivity by adjusting the variable resistance value R4.

The adjustment procedure of the sensor characteristic adjustment circuit of FIG. 9 is, for example, as follows. First, the variable resistor 4 is adjusted to set the output sensitivity of the sensor characteristic adjustment circuit. Next, the variable resistor 8
Is adjusted to set the output offset of the sensor characteristic adjustment circuit.

In the sensor characteristic adjusting circuit shown in FIG. 9, the operational amplifier 2 is operated as an inverting amplifier. Therefore, as the output Vs of the semiconductor sensor 1 increases, the output Vo of the sensor characteristic adjustment circuit decreases. However, it is also possible to connect an inverting amplifier to the output of the operational amplifier 2 so that the output of the sensor characteristic adjustment circuit has the same polarity as the output Vs of the semiconductor sensor 1.

[0008]

Since the conventional sensor characteristic adjustment circuit is constructed as described above, variable resistors 4 and 8 for characteristic adjustment are required, and the semiconductor sensor 1 and the operational amplifier 2 are integrated. There was a problem of obstacles on the above.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a sensor characteristic adjusting circuit which does not require a variable resistor.

[0010]

Means for Solving the Problems The first invention of the present invention is:
A sensor characteristic adjustment circuit for adjusting an output characteristic of an analog semiconductor sensor provided with an analog voltage control amplifier having a control terminal on an output side, wherein an external input corresponding to sensitivity and offset adjustment values of the semiconductor sensor is provided. Serial / parallel conversion means for converting the obtained digital serial data into parallel data, a nonvolatile storage device for storing the digital parallel data output from the serial / parallel conversion means, and a nonvolatile storage device for storing the digital parallel data. After digital-to-analog conversion of the offset adjustment value of the digital parallel data, the offset adjustment value is added to the output voltage of the semiconductor sensor, and the sensitivity adjustment value is digital-to-analog converted, and then applied to the control terminal of the voltage-controlled amplifier. Two D / s for setting the amplification factor In the sensor characteristic adjusting circuit and a digital / analog conversion means including a transducer.

According to a second aspect of the present invention, there is provided a sensor characteristic adjusting method for adjusting an output characteristic of an analog semiconductor sensor having a voltage-controlled amplifier connected to an output side, wherein the method adjusts sensitivity and offset adjustment values of the semiconductor sensor. Converting the digital serial data into parallel data, storing the converted parallel data in a non-volatile storage device, and converting the digital parallel data stored in the non-volatile storage device into the sensitivity and offset of the semiconductor sensor. And convert it to an analog signal.
Adding an offset adjustment value of the semiconductor sensor to the output voltage of the semiconductor sensor, applying a sensitivity adjustment value to a control terminal of the voltage control amplifier to set an amplification factor, and based on the analog signal. There is provided a sensor characteristic adjustment method for adjusting the sensitivity and offset of a semiconductor sensor.

According to a third aspect of the present invention, there is provided a sensor characteristic adjusting circuit for adjusting an output characteristic of an analog semiconductor sensor provided with an analog voltage control amplifier having a control terminal on an output side. Serial / parallel conversion means for converting externally input digital serial data corresponding to an offset adjustment value into parallel data, and a nonvolatile storage device for storing digital parallel data output from the serial / parallel conversion means And after digital-to-analog conversion of the offset adjustment value of the digital parallel data stored in the non-volatile storage device, and adding the adjusted value of sensitivity to the digital-to-analog conversion of the semiconductor sensor. Setting the gain by applying to the control terminal of the voltage controlled amplifier, Two D for offset and for sensitivity
Digital / analog conversion means including an A / A converter; and gate means inserted between the serial / parallel conversion means and the nonvolatile storage device, wherein
A gate unit for separating the nonvolatile storage device from the serial / parallel conversion unit after the parallel data output from the parallel conversion unit is written into the nonvolatile storage device.

According to a fourth aspect of the present invention, there is provided a sensor characteristic adjusting circuit for adjusting an output characteristic of an analog semiconductor sensor provided with an analog voltage control amplifier having a control terminal on an output side. Serial / parallel conversion means for converting externally input digital serial data corresponding to an offset adjustment value into parallel data, and a nonvolatile storage device for storing digital parallel data output from the serial / parallel conversion means And dividing the digital parallel data output from the serial / parallel conversion means or the non-volatile storage device into sensitivity and offset adjustment values of the semiconductor sensor. D / D to convert to analog signals separately A digital / analog converting means including a converter, adding an analog-converted offset adjustment value to the output voltage of the semiconductor sensor, applying the sensitivity adjustment value to a control terminal of the voltage control amplifier, and setting an amplification factor; Gate means inserted between said serial / parallel conversion means and digital / analog conversion means,
First gate means for separating the output of the serial / parallel conversion means from the digital / analog conversion means after writing of data from the serial / parallel conversion means to the non-volatile storage device is completed; Gate means inserted between the device and the digital / analog conversion means, wherein the non-volatile storage device is subjected to digital / analog conversion before data is written from the serial / parallel conversion means to the non-volatile storage device. And a second gate means separated from the means.

[0014]

The sensor characteristic adjusting circuit according to the first invention and the second sensor characteristic adjusting circuit
In the sensor characteristic adjusting method according to the invention, the characteristic data is stored in the nonvolatile storage device, and output characteristics such as offset and sensitivity are set based on the data stored in the nonvolatile storage device. Further, in the case of the sensor characteristic adjusting circuit according to the third invention, after writing data to the nonvolatile memory device, the data converting means is separated from the nonvolatile memory device by the gate means. In the case of the sensor characteristic adjustment circuit according to the fourth aspect, the characteristics of the sensor characteristic adjustment circuit are adjusted by the output of the data conversion means before writing data to the nonvolatile storage device, and the nonvolatile storage is performed after the adjustment value is determined. After writing data to the device, the output of the data conversion means is separated from the adjustment means.

[0015]

[Embodiment 1] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows Embodiment 1 of the present invention.
FIG. 2 is a circuit diagram of a sensor characteristic adjustment circuit according to FIG. The adder 9 is connected to the output of the semiconductor sensor 1, adds an offset corresponding to the output of the D / A converter 11 to the output of the semiconductor sensor 1, and inputs this to the voltage control amplifier 10. The control terminal of the voltage controlled amplifier 10 is connected to the output of the D / A converter 12, and the amplification factor of the voltage controlled amplifier 10
2 is determined according to the value of the output. Voltage control amplifier 10
Corresponds to the sensitivity of the sensor characteristic adjustment circuit. 13
Is a nonvolatile storage device for setting input digital data of the D / A converters 11 and 12. Reference numeral 14 denotes a serial / parallel converter that converts serial data stored in the nonvolatile storage device 13 into parallel data to be written in the nonvolatile storage 13.

FIG. 2 is a waveform diagram of a signal input to the serial / parallel converter of the sensor characteristic adjustment circuit of FIG.
Next, the operation of the sensor characteristic adjustment circuit will be described with reference to FIGS. The serial / parallel converter 14 converts serial data input to the data input terminal Di into, for example, 12-bit parallel data D1 to Dn (n = 12) and outputs the data to the nonvolatile storage device 13. This operation is performed as follows.

As shown in FIG. 2, a clock terminal CLK of the serial / parallel converter 14 receives a clock pulse as an operation reference of the serial / parallel converter 14. The serial / parallel converter 14 takes in the serial data input to the terminal Di at the rise of the clock pulse CLK.

When the enable signal (inverted reset signal) applied to the reset terminal (enable terminal) E is "L", the parallel outputs of the serial / parallel converter 14 are all "L". Here, when the enable signal E applied to the terminal E becomes "H", the serial / parallel converter 14 takes in the serial data Di in synchronization with the clock pulse CLK and outputs parallel outputs D1 to Dn.

The non-volatile storage device 13 includes 12 memory cells (storage units) each storing 12-bit parallel data D1 to Dn. After the signal applied to the reset terminal E of the serial / parallel converter 14 becomes “H”, the serial / parallel converter 14 takes in data for n clock pulses and outputs the (n + 1) th clock pulse. At this time, when the write terminal W becomes "H", the parallel data D1 to Dn are written from the nonvolatile storage device 13 to the serial / parallel converter 14. Once the data is written, the data in the nonvolatile storage device 13 cannot be rewritten.

In this manner, the parallel data D1 to Dn are written to the nonvolatile storage device 13. Of the parallel data, for example, the first to m-bit parallel data D1 to
Dm is input to a digital input of the D / A converter 11.
The remaining m + 1 to n-th bits Dm + 1 to Dn are input to the digital input of the D / A converter 12.

The D / A converter 11 has data bits D1 to Dm.
Is converted to corresponding analog data and output to the adder 9. The adder 9 adds the output of the D / A converter 11 to the output of the semiconductor sensor 1 as an offset, and
Enter 0.

The D / A converter 12 has a data bit Dm +
1 to Dn are converted into corresponding analog values and the voltage control amplifier 1
0 is applied to the control terminal. As a result, the voltage control amplifier 1
0 amplifies the input signal from the adder 9 at an amplification factor corresponding to the data Dm + 1 to Dn. As a result, the output of the semiconductor sensor 1 is adjusted by the predetermined offset and sensitivity specified by the data D1 to Dm and Dm + 1 to Dn, and output from the voltage control amplifier 10.

Embodiment 2 FIG. FIG. 3 is a circuit diagram of a sensor characteristic adjustment circuit according to Embodiment 2 of the present invention. The sensor characteristic adjustment circuit of FIG. 3 is configured in the same manner as the sensor characteristic adjustment circuit of FIG. 1, but includes gates 151 to 15n, and the nonvolatile memory device 13 is a memory cell of the (n + 1) th bit connected to the write terminal W. Having. That is, the nonvolatile storage device 13 stores n +
It has one memory cell, of which n D1 to Dn are connected to gates 151 to 15n, respectively. The (n + 1) th bit memory cell Dn + 1 of the nonvolatile memory device 13 is directly connected to the write terminal W.

The input terminals of the gates 151 to 15n are connected to the parallel outputs D1 to Dn of the serial / parallel converter 14, respectively. The inverted input terminals of the gates 151 to 15n are connected to the (n + 1) th bit memory of the nonvolatile memory device 13.
Connected to the output of cell Dn + 1. Each gate 151 ~ 15n
Are the outputs D1 to Dn of the serial / parallel converter 14,
The NAND of the output Dn + 1 of the memory cell of the (n + 1) th bit of the nonvolatile memory device 13 is calculated.
To enter.

Writing of data from the serial / parallel converter 14 to the nonvolatile memory device 13 is performed by the output Dn + of the (n + 1) th bit memory cell of the nonvolatile memory device 13.
This is performed before 1 becomes "H". The write terminal W becomes “H”, and the (n + 1) th bit memory of the nonvolatile memory device 13
After the logical value 1 is written in the cell and the output becomes "H",
The outputs of the gates 151 to 15n are all "L". Therefore, no matter what value the parallel data of the serial / parallel converter 14 has, the inputs of the non-volatile storage device 13 all become "L" and writing becomes impossible. Therefore, even if the serial / parallel converter 14 malfunctions, the nonvolatile memory device 13 is not affected at all, and can be used even in a noisy place.

FIG. 4 is a partial circuit diagram showing the internal configuration of the nonvolatile memory device of the circuit of FIG. Nonvolatile storage device 13
Avalanche diodes 161 to 16n
Consists of +1. The avalanche diodes 161 to 16n + 1 are usually formed by connecting the base-emitter diodes of an npn transistor in reverse, and the breakdown voltage is usually 6 to 9V. The avalanche diodes 161 to 16n + 1 are connected in series with the transistors 171 to 17n + 1, and the serially connected avalanche diodes 161 to 16n + 1 and the transistors 171 to 17n + 1 are connected between the word line 19 and the ground. Connected to. The connection point between each of the transistors 171 to 17n + 1 and the avalanche diodes 161 to 16n + 1 is grounded via resistors 181 to 18n + 1 having a high resistance value.

The bases of the transistors 171 to 17n are connected to the outputs of the gates 151 to 15n, respectively, and when the output of the corresponding gate becomes "H", the transistors 171 to 17n become conductive and write to the avalanche diodes 161 to 16n. . The base of the transistor 17n + 1 is the write terminal W
When the write signal W becomes "H", the avalanche diode 16n + 1 breaks down, and the inverted input Dn + 1 to each of the gates 151 to 15n becomes "H".

The writing of the data D1 to Dn to the avalanche diodes 161 to 16n constituting the memory cells of the nonvolatile memory device 13 is performed as follows. In a state where the avalanche diode 16n + 1 does not break down and the signal W applied to the write terminal is "L", the transistor 17n + 1 is in a non-conductive state, and the gates 151 to 1
The 5n inverted input Dn + 1 is "L". Therefore, in this state, the gates 151 to 15n are open.

Here, when the parallel data D1 to Dn converted by the serial / parallel converter 14 are input to the gates 151 to 15n, the outputs of the gates 151 to 15n are in accordance with the logical values 1 to 0 of the data D1 to Dn. "H" or "L". As a result, the transistors 171 to 17n are turned on or off according to the logical values 1 to 0 of the data D1 to Dn.

When the word line 19 is boosted to a voltage higher than the breakdown voltage of the avalanche diode, for example, about 15 V, a large current of about several tens mA flows through the avalanche diodes 161 to 16n corresponding to the logical value 1 of the data D1 to Dn. The current flows and short-circuits, and the data corresponding to each of the bits D1 to Dn is written to the avalanche diodes 161 to 16n. For example, when the serial signal Di shown in FIG. 2 is supplied to the serial / parallel converter 14, D1 has a logical value of 1. Therefore, a large current flows through the avalanche diode 161, causing breakdown and storing the logical value 1. Dn
Is a logical value 0, and therefore the avalanche diode 16
n does not yield and stores a logical value 0.

After the writing is completed as described above,
When the write terminal W becomes "H", the transistor 17n + 1 becomes conductive and the avalanche diode 16n + 1 breaks down. Here, the voltage of the word line 19 is reduced to 3 to 5V. However, the avalanche diode 16n + 1 is short-circuited, and the transistor 17n + 1 becomes non-conductive after the voltage applied to the write terminal W becomes "L". Therefore, the inverted inputs Dn + 1 to the gates 151 to 15n become "H", and all the gates 151 to 15n are closed.

Thereafter, as long as the write terminal W is maintained at "L", the input Dn + 1 to the gates 151 to 15n is always at "H".
And the gates 151 to 15n are all closed. Therefore, even if the serial / parallel converter 14 malfunctions, it does not affect the nonvolatile storage device 13. The data D1 to Dn stored in each avalanche diode 161 to 16n are connected to a resistor 18
The D / A converter 1 sets the potential at the connection point between 1-18n and each of the avalanche diodes 161-16n to "H" or "L".
1 to the D / A converter 12.

Embodiment 3 FIG. In the second embodiment, the output Dn + 1 of the (n + 1) th bit of the nonvolatile memory device 13 is directly supplied to the gates 151 to 151.
15n, and the serial / parallel converter 14 and the nonvolatile storage device 13 were separated after the writing was completed.
FIG. 5 is a circuit diagram of a sensor characteristic adjusting circuit according to Embodiment 3 of the present invention. In the circuit of FIG. 5, the write terminal W is connected to the input terminal Dn + 1 of the nonvolatile memory device 13 via the gate 15n + 1, and the output Dn + 1 of the nonvolatile memory device 13 is connected via the gate 20. Each gate 151 ~ 15n
To enter. Further, the timer 21 receives the output of the gate 15n + 1 as input, holds the "H" state for a time necessary for the avalanche diode to break down at the rising edge thereof, and inputs it to the inverting terminal of the gate 20.

Data writing to the nonvolatile memory device 13 shown in FIG. 5 is performed as follows. When the write terminal W is “L” and the data has not been written to the nonvolatile memory device 13 yet, the output of the gate 15n + 1 is “L” and the output Dn + 1 of the nonvolatile memory device 13 is also "L".
Therefore, the output of the gate 20 is also "L". Therefore, the inverted inputs of the gates 151 to 15n + 1 are "L", and the gate 151
１５15n + 1 is open.

Here, when the write terminal W is set to "H" and a high voltage is applied to the word line of the nonvolatile memory device 13, data is written as follows. That is, the write terminal W
Is set to "H", the output of the gate 15n + 1 becomes "H",
The output of the timer 21 is kept at "H" for a predetermined time. The inverting input of gate 20 is connected to the output of timer 21. Therefore, the output of the gate 20 is maintained at "L" for a predetermined time, and the gates 151 to 15n + 1 are open during this time. That is, the input terminals D1 to Dn and Dn + 1 of the nonvolatile storage device 13 are maintained at the output values D1 to Dn of the serial / parallel converter 14 and the output value of the write signal W for a predetermined time. Thirteen memory cells are written.

When the output of the timer 21 becomes "L" after the completion of the data writing to the nonvolatile memory device 13, the gate 2
0 is opened, and the value “H” of the output Dn + 1 of the nonvolatile storage device 13
Is output. Therefore, the gates 151 to 15n + 1 whose inverting inputs are connected to the output of the gate 20 are all closed, and the nonvolatile memory device 13 is separated from the serial / parallel converter 14. The holding time of the timer 21 at “H” needs to be set longer than the time during which the write terminal W is maintained at “H”.

Embodiment 4 FIG. FIG. 6 is a circuit diagram of a sensor characteristic adjusting circuit according to Embodiment 4 of the present invention. The circuit of FIG. 6 differs from the circuit of FIG. 1 in the following points. The nonvolatile storage device 13 has a memory cell Dn + 1 directly connected to a write terminal, in addition to a memory cell storing data D1 to Dn. The outputs D1 to Dn of the nonvolatile memory device 13 are input to the D / A converter 11 and the D / A converter 12 via the tristate buffer gates 221 to 22n. To 22n are connected to the output Dn + 1 of the nonvolatile storage device 13. Also, the outputs D1 to Dn of the serial / parallel converter 14
Are the tri-state buffer gates 231 to
23n, the D / A converter 11 and the D / A converter 1
2 corresponding bits. The inversion control terminals of these tristate buffer gates 231 to 23n are connected to the output Dn + 1 of the nonvolatile memory device 13.

The operation of the circuit of FIG. 6 is as follows. When the write terminal W is “L” and no data is written to the nonvolatile memory device 13, the nonvolatile memory device 1
3, the output Dn + 1 is "L". Therefore, in this state, the tri-state buffer gates 221 to 22n are closed while the tri-state buffer gates 231 to 2n are closed.
3n is open. Therefore, when data has not yet been written to the nonvolatile storage device 13 and the output Dn + 1 of the nonvolatile storage device 13 is "L", the outputs D1 to Dn of the serial / parallel converter 14 are tri-state. buffer·
D / A converter 11, D / A via gates 231 to 23n
Input to the converter 12.

Here, when the write terminal W becomes "H" and writing is performed in the nonvolatile memory device 13, the output Dn + 1 of the nonvolatile memory device 13 becomes "H" and the tristate
The buffer gates 221 to 22n are opened, and the tri-state buffer gates 231 to 23n are closed. Therefore, after writing to the nonvolatile storage device 13,
The output Dn + 1 of the nonvolatile storage device 13 becomes "H", and the outputs D1 to Dn of the nonvolatile storage device 13 are supplied to the D / A converter 1 via the tristate buffer gates 221 to 22n.
1, input to the D / A converter 12.

In the sensor characteristic adjusting circuit of FIG. 4, before writing data to the nonvolatile memory device 13, that is, the write terminal W
Before it becomes "H", the D / A converter 11 and the D / A converter 1
The output value of 2 is not set. Therefore, the voltage control amplifier 1
The output offset and sensitivity of 0 are not set.
Therefore, it is not possible to adjust the data D1 to Dn while monitoring the output value of the voltage control amplifier 10 and adjust the sensor characteristic adjustment circuit to a predetermined offset and sensitivity.

The circuit of FIG. 6 solves this problem. In the case of the circuit of FIG. 6, before writing data to the nonvolatile memory device 13, the outputs D1 to Dn of the serial / parallel converter 14 are directly input to the D / A converter 11 and the D / A converter 12. You. Therefore, by monitoring the output of the voltage control amplifier 10 in this state, the data D1
It can be adjusted while checking ~ Dn.

Embodiment 5 FIG. FIG. 7 is a circuit diagram of a sensor characteristic adjusting circuit according to Embodiment 5 of the present invention. The circuit of FIG. 7 is configured similarly to the circuit of FIG. However, the serial / parallel converter 14 has a bit select terminal SE. For example, when the bit select terminal SE is "L", the serial / parallel converter 14 performs serial / parallel conversion on the data bits D1 to Dm and holds the values of the data bits Dm + 1 to Dn. When the bit select terminal SE is "H", the data bits Dm + 1 to Dn are converted from serial to parallel, and the value of the data bits Dm + 1 + Dn is held.

Therefore, before writing data to the nonvolatile memory device 13, the data bits D1 to Dm corresponding to the offset and the data bits Dm + 1 to Dm + 1 to the sensitivity correspond to each other.
The value of Dn can be adjusted separately by monitoring the output of the voltage controlled amplifier 10, so that each data bit can be determined efficiently. The offset and sensitivity settings may affect each other. In such a case, for example, the D / A converter 11 is first adjusted, and then the D / A converter is adjusted.
After adjusting the converter 12, it may be necessary to further adjust the D / A converter 11. In such a case,
After the offset and sensitivity adjustments are repeated, data can be written to the nonvolatile storage device 13 at a time when predetermined characteristics are obtained.

Embodiment 6 FIG. FIG. 8 is a circuit diagram of a sensor characteristic adjustment circuit according to Embodiment 6 of the present invention. In the sixth embodiment, up / down counters 24 and 25 are used instead of the serial / parallel converter 14. Up / down counter 2
Reference numerals 4 and 25 denote a D / A converter 11 and a D / A converter 1, respectively.
2, and outputs data corresponding to offset and sensitivity. Outputs D1 to Dm of the up / down counter 24 are connected to the memory cells D1 to Dm of the nonvolatile storage device 13 and input to the D / A converter 11 via tristate buffer gates 231 to 23m. . The outputs Dm + 1 to Dn of the up / down counter 25 are stored in the memory cells D of the nonvolatile storage device 13.
m + 1 to Dn, and the D / A converter 12 via tristate buffer gates 23m + 1 to 23n.
Is input to

The W terminal of the sensor characteristic adjustment circuit is connected to the write terminal W of the nonvolatile memory device 13 and the memory cell Dn + 1. The count enable terminal CE1 is connected to the count enable terminal of the up / down counter 24, and the count enable terminal CE2 is connected to the count enable terminal of the up / down counter 25, respectively. Also, an up / down terminal U / D, a reset terminal R, and a clock terminal CLK of the sensor characteristic adjustment circuit.
Are the up / down terminals of the up / down counters 24 and 25, the reset terminal R, and the clock terminal C, respectively.
LK. Other configurations are the same as those of the circuit of FIG.

The operation of the up / down counters 24 and 25 in FIG. 8 is as follows. Up / down counter 24, 2
Numeral 5 counts in synchronization with the pulse applied to the clock terminal CLK, stores the count value, and outputs it as parallel data D1 to Dm and Dm + 1 to Dn. Up-count (increase in count value) and down-count (decrease count value) of the up-down counters 24 and 25 are selected by an up / down terminal U / D. That is, when the up / down terminal U / D is "H", the count is up, and when it is "L", the count is down. Up-down counters 24, 2
5 operates independently by the count enable terminals CE1 and CE2. That is, for example, the count enable terminal CE1 is "H" and the count enable terminal CE2 is "L".
In this case, only the up / down counter 24 counts, and the data stored in the up / down counter 25 is held as it is. Therefore, in this case, the output of the up / down counter 25 is fixed, and only the output of the up / down counter 24 changes.

Therefore, for example, only the offset can be adjusted by monitoring the output of the voltage control amplifier 10 before writing data to the nonvolatile memory device 13. In this case, while monitoring the output of the voltage controlled amplifier 10, if the output of the up / down counter 24 becomes too large, the up / down terminal U / D is set to "L" to count down the up / down counter 24. The offset can be fine-tuned. Up / down counter 25
The setting of the sensitivity of the sensor characteristic adjustment circuit determined by the value of (1) can be similarly performed.

Other Embodiments The above-described embodiments 1 to 6 can be combined.
For example, Embodiments 3 and 4 or a combination of Embodiments 3 and 6 can be considered.

[0049]

As described above, in the sensor characteristic adjustment circuit according to the first invention and the sensor characteristic adjustment method according to the second invention, the characteristic data is stored in the nonvolatile storage device. The output characteristics such as offset and sensitivity are set based on the data stored in. Therefore, there is an effect that a sensor characteristic adjustment circuit that does not use a variable resistor that hinders integration can be provided.

In the case of the sensor characteristic adjusting circuit according to the third aspect of the present invention, the data conversion unit is separated from the nonvolatile storage device by the gate unit after writing data to the nonvolatile storage device. Therefore, there is an effect that a sensor characteristic adjustment circuit that operates stably even when used in a place with much noise is obtained.

Further, in the case of the sensor characteristic adjusting circuit according to the fourth aspect of the present invention, the characteristics of the sensor characteristic adjusting circuit are adjusted by the output of the data conversion means before writing data to the nonvolatile memory device, and the adjustment value is determined. Data is written to the nonvolatile storage device later, and the output of the data conversion unit is separated from the adjustment unit. Accordingly, there is an effect that the characteristics of the sensor characteristic adjustment circuit are monitored before writing the data to the nonvolatile storage device and the data value is adjusted, and then the data can be written to the nonvolatile storage device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a sensor characteristic adjustment circuit according to Embodiment 1 of the present invention.

FIG. 2 is a waveform diagram of a signal input to a serial / parallel converter of the sensor characteristic adjustment circuit of FIG. 1;

FIG. 3 is a circuit diagram of a sensor characteristic adjustment circuit according to Embodiment 2 of the present invention.

FIG. 4 is a partial circuit diagram showing an internal configuration of a nonvolatile storage device of the circuit of FIG. 3;

FIG. 5 is a circuit diagram of a sensor characteristic adjustment circuit according to Embodiment 3 of the present invention.

FIG. 6 is a circuit diagram of a sensor characteristic adjusting circuit according to Embodiment 4 of the present invention.

FIG. 7 is a circuit diagram of a sensor characteristic adjusting circuit according to Embodiment 5 of the present invention.

FIG. 8 is a circuit diagram of a sensor characteristic adjustment circuit according to Embodiment 6 of the present invention.

FIG. 9 is a circuit diagram of a conventional sensor characteristic adjustment circuit.

[Explanation of symbols]

 Reference Signs List 1 semiconductor sensor 2 operational amplifier 3 resistor 4 variable resistor 5 reference power supply 6 ground 7 resistor 8 variable resistor 9 adder 10 voltage control amplifier 11 D / A converter 12 D / A converter 13 nonvolatile storage device 14 serial / parallel conversion Container 21 timer 24 up / down counter 25 up / down counter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03G 3/30 H03G 3/20 G01D 3/00

Claims (4)

(57) [Claims] An analog power supply having a control terminal on the output side.
Output of an analog semiconductor sensor equipped with a pressure control amplifier.
A sensor / characteristic adjustment circuit for adjusting characteristics, wherein the serial / parallel conversion means converts externally input digital serial data corresponding to the sensitivity and offset adjustment values of the semiconductor sensor into parallel data; A non-volatile storage device for storing digital parallel data output by the parallel conversion means; and a digital / analog offset adjustment value of the digital parallel data stored in the non-volatile storage device.
After log conversion, add to the output voltage of the semiconductor sensor
After converting the sensitivity adjustment value from digital to analog,
Apply to the control terminal of the voltage controlled amplifier to set the amplification factor
Two D / A converters for fset and sensitivity
Sensor characteristic adjusting circuit and a non-digital / analog converter. 2. An amplifier having a voltage-controlled amplifier connected to the output side.
A sensor characteristic adjusting method for adjusting an output characteristic of a semiconductor sensor of a analog, comprising the steps of: converting digital serial data corresponding to an adjustment value of sensitivity and offset of the semiconductor sensor into parallel data; Storing the data in a storage device; converting the digital parallel data stored in the nonvolatile storage device into analog signals by dividing the sensitivity and offset adjustment values of the semiconductor sensor into analog signals ;
The offset adjustment value is added to the output voltage of the semiconductor sensor.
And adjusts the sensitivity adjustment value to the control terminal of the voltage-controlled amplifier.
A step of applying and setting an amplification factor, and adjusting a sensitivity and an offset of the semiconductor sensor based on the analog signal. 3. An analog power supply having a control terminal on the output side.
Output of an analog semiconductor sensor equipped with a pressure control amplifier.
A sensor / characteristic adjustment circuit for adjusting characteristics, wherein the serial / parallel conversion means converts externally input digital serial data corresponding to the sensitivity and offset adjustment values of the semiconductor sensor into parallel data; A non-volatile storage device for storing digital parallel data output by the parallel conversion means; and a digital / analog offset adjustment value of the digital parallel data stored in the non-volatile storage device.
After log conversion, add to the output voltage of the semiconductor sensor
After converting the sensitivity adjustment value from digital to analog,
Apply to the control terminal of the voltage controlled amplifier to set the amplification factor
Two D / A converters for offset and sensitivity
Digital / analog conversion means, and gate means inserted between the serial / parallel conversion means and the non-volatile storage device, wherein the parallel data output from the serial / parallel conversion means is stored in the non-volatile storage device. A gate unit for separating the nonvolatile storage device from the serial / parallel conversion unit after being written to the device. 4. An analog power supply having a control terminal on the output side.
Output of an analog semiconductor sensor equipped with a pressure control amplifier.
A sensor / characteristic adjustment circuit for adjusting characteristics, wherein the serial / parallel conversion means converts externally input digital serial data corresponding to the sensitivity and offset adjustment values of the semiconductor sensor into parallel data; A non-volatile storage device for storing digital parallel data output by the parallel conversion means; an output of the serial / parallel conversion means or the non-volatile storage device, which is connected to the output of the serial / parallel conversion means and the non-volatile storage device; Two D signals for dividing digital parallel data into sensitivity and offset adjustment values of the semiconductor sensor and separately converting them into analog signals
/ A converter only contains, tone analog conversion offset
The adjusted value is added to the output voltage of the semiconductor sensor to adjust the sensitivity.
Applying the integer value to the control terminal of the voltage-controlled amplifier,
A digital / analog conversion means for setting, a inserted gating means between said serial / parallel conversion means and digital / analog converting means, the writing from the serial / parallel conversion unit of data to the nonvolatile memory device Is completed, first gate means for separating the output of the serial / parallel conversion means from the digital / analog conversion means, and gate means inserted between the nonvolatile storage device and the digital / analog conversion means. And the cereal /
A second gate unit that separates the nonvolatile storage device from the digital / analog conversion unit before data is written from the parallel conversion unit to the nonvolatile storage device.