JP2856452B2 - Mask register control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] For example, a mask element
Regarding the mask register control method for performing operations on data, the aim is to use the same LSI chip configuration and minimize the number of pins as possible. mask·
After incorporating a mask pipeline for calculating element data, the mask pipeline on each mask register is configured to perform substantially the same calculation.

[Industrial applications]

The present invention relates to a mask register control method, and more particularly to a mask register control method for performing an operation on mask element data when performing a vector operation, for example.

In performing the vector operation, the element data constituting each vector are operated together to obtain a new vector having the element data of the operation result as an element. In this case, the same operation is not always performed for all the element data, and a certain element data is masked so that the operation is not performed. What instructs whether or not to apply the mask for this purpose may be considered as the mask element data.

Then, for the mask element data,
The operation of two sets of mask element data may be performed by the mask pipeline.

[Conventional technology]

FIG. 3 shows a conventional mask register control method. 1-i are mask registers, 2-0 are mask pipelines, 3-ij are banks, 4-i are write registers, 5-i are read registers, and 6-0 are 0th inputs. The register 7-0 represents a first input register, and 8-0 represents an output register.

One of the mask element data is stored in the banks 3-00 to 3-07, and is sequentially read out to the read-out register 5-0, and the 0-th input register 6 is read.
It is set to -0, and the other is stored in the banks 3-10 to 3-17, sequentially read out to the readout register 5-1 and set in the first input register 7-0.

Contents of the 0th input register 6-0 and the first input register 7
The contents of -0, that is, two corresponding mask element data are operated in the mask pipeline 2-0, and the result is set in the output register 8-0. The mask pipeline 2-0 is an AND logic,
It is instructed by an instruction to perform one of OR logic, EOR logic, and no operation.

The contents set in output register 8-0 are stored in bank 3
-00 to 3-07 and banks 3-10 to 3-17, respectively.

As described with reference to FIG. 3, the mask element data is sequentially calculated by pipeline processing. In the case of the configuration shown in FIG.
−0 and the configuration of the mask register 1-1 are different. That is, when the LSI configuration is adopted, it is necessary to undesirably create different LSIs.

FIG. 4 shows a conventional mask register control system corresponding to the improvement of the configuration shown in FIG.

Reference numerals 1, 2, 3, 4, 5, 6, 7, 8 in the figure respectively correspond to FIG.

In the case of FIG. 4, the configurations of the mask register 1-0 and the mask register 1-1 are the same. And
In the case shown in FIG. 4, although the configuration of both mask registers is the same, the operation is performed only in the mask pipeline 2-0, and the operation is not performed in the mask pipeline 2-1. It has been cut out of the circuit.

[Problems to be solved by the invention]

4 has the advantage that a common LSI can be used. However, each mask register 1
As indicated by the white circles around -i, the number of pins for connection to the outside is doubled as compared with the case shown in FIG.

SUMMARY OF THE INVENTION It is an object of the present invention to standardize the configuration of an LSI chip and minimize the number of pins.

[Means for solving the problem]

FIG. 1 shows a principle configuration diagram of the present invention. Symbol 1 in the figure
i is a mask register, 2-i is a mask pipeline, 3-ij is a bank, 4-i is a write register, 5-i is a read register, 6-i is a 0th input register, and 7-i is The first input register, 8-i, is the output register, 9-i and 10-
i is a pin, 11-i is a fixed value input pin (1 bit)
Is represented.

One of the mask element data is stored in the banks 3-00 to 3-07, and is sequentially read out to the read-out register 5-0, and is stored in the mask register 1-0.
0th input register 6-0 in 0 and mask register 1
-1 is set to the first input register 7-1, and the other is stored in the banks 3-10 to 3-17.
The data is read by the read register 5-1 and set in the first input register 7-0 in the mask register 1-0 and the 0th input register 6-1 in the mask register 1-1.

In the case of the present invention, a fixed value input pin 11-i for inputting a fixed bit of "0" or "1" is provided for the mask pipeline 2-i. And “0” is pin 11
In the mask pipeline 2-0 input to −0, the 0th input register 6-0 and the first input register 7-0 respectively function as the 0th input register and the 1st input register, respectively. The mask pipeline 2
The gate is controlled within 0. However, on the other hand, “1” is
In the mask pipeline 2-1 input to the first input register 1 and the 0th input register 6-1 and the first input register 7
The gates in the mask pipeline 2-1 are controlled and exchanged respectively with -1. That is, the 0th input register 6-1 plays the role of the first input register, and the first input register 7-1 plays the role of the 0th input register.

[Action]

The two mask pipelines 2-0 and 2-1 are:
The same operation, for example, an AND logic, is performed for each of the input registers 6 and 7 only by differentiating the 0th and the 1st values for the input registers 6 and 7 depending on the pins 11-i.

That is, the mask element data read to the read register 5-0 is {a ₁ , a ₂ , a ₃ ,...}, And the mask element data read to the read register 5-1 is When {b ₁ , b ₂ , b ₃ ,...}, {A ₁ & b ₁ , a ₂ , & b ₂ , a ₃ & b ₃ ,. 4-0, and {a ₁ & b ₁ , a ₂ & b ₂ , a ₃ & b ₃ ,...}} Are also stored in the write register 4-1. It is set sequentially.

That is, the same result as that shown in FIG. 3 is obtained, and the number of pins is increased only by the pins 11-i.

〔Example〕

FIG. 2 shows an embodiment of the mask pipeline in the case of the present invention. Reference numerals 2, 6, 7, and 8 in the figure correspond to FIG. 1, 12 is an AND logical operation unit, 13 is an OR logical operation unit, 14 is an EOR logical operation unit, 15 is a NOP operation unit, and 16 and 17 are Each represents a selection circuit. The marks in the figure represent gates. As for the upper gate in the figure, the straight direction or the cross direction in the figure is selected by the fixed value “0” or “1”. The lower gate in the figure is selectively turned on by the operation code of the instruction.

As shown in FIG. 2, the NOP operation unit 15 is connected only to the selection circuit 17. For this reason, it can be considered that the fixed value input pin 11-i of the present invention is provided.

〔The invention's effect〕

As described above, according to the present invention, the LSI configuration is shared, and the number of pins is slightly increased.

[Brief description of the drawings]

1 is a block diagram showing the principle of the present invention, FIG. 2 is an embodiment of a mask pipeline, FIG. 3 is a conventional mask register control system, and FIG. 4 is an improved conventional mask register. This shows the control method. In the figure, 1 is a mask register, 2 is a mask pipeline, 3 is a bank, 4 is a write register, 5 is a read register, 6 and 7 are input registers, 8 is an output register, and 9 and 10 are pins. , 11 represent fixed value input pins.

Claims (1)

(57) [Claims] A plurality of banks (3-ij) and a write register (4-i) for the plurality of banks (3-ij).
And a plurality of mask registers (1-i) incorporating at least read registers (5-i) from the plurality of banks (3-ij), and a zeroth mask register (1-0) And the mask element data sequentially read to the read register (5-0) in the first mask register (1-1) and the mask element data sequentially read to the read register (5-1) in the first mask register (1-1) An operation including a no operation is performed by the mask pipeline (2), and the write register (4-0) in the zeroth mask register (1-0) and the first mask register (1 Write register in -1) (4-1)
In the mask register control method stored in the bank (3-ij) of each mask register (1-i) via the first and second mask registers (1-i), An input register (6-i) and a first input register (7-i)
And the mask pipeline (2-i) and the output register (8-i), and the zeroth input register (6-i) inputted to the mask pipeline (2-i). i) and the contents of the first input register (7-i) are exchanged, and a fixed pin (11-i) for instructing whether or not to supply to the mask pipeline (2-i) is used. ), And the mask pipeline (2-i) in each mask register (1-i) executes the same operation under the instruction given by the fixed pin (11-i). And supplying the operation result to the write register (4-i) in its own mask register (1-i).