JPS6198443A - Data processor - Google Patents

Abstract

PURPOSE:To enable a control part to control directly an input/output port with no intervention of an executing unit, by providing newly an input/output port which is controlled directly by the control signal delivered from a micro- ROM into a microprocessor. CONSTITUTION:A microinstruction is stored in a micro-ROM11 for each address. The contents of an instruction register 12 are decoded by an address decoder 13 when a macroinstruction read out of a memory 5 is fetched by an instruction register 12 via a data bus 3. Then an access is given to the corresponding address in the ROM11, and a microinstruction is read out. The macroinstruction fetched by the register 12 is executed by reading out plural microinstructions out of the ROM11. Then the following microinstructions are read out successive ly according to the next address written to the next address field of the microinstruction given from the ROM11.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to data processing technology and technology that is effective when applied to a central processing unit (hereinafter referred to as a microprocessor) in a microcomputer system, such as a microprogram type microprocessor. Concerning effective techniques that can be used.

[Background Art] Hard-wired systems and microprogram systems are known as control systems within microprocessors.

Among these, the microprogram method controls the data transfer order and operation order for execution units consisting of adders and registers, and controls gate circuits and registers in a read-only memory (control storage, hereinafter referred to as micro ROM). ) is carried out according to the microprogram stored in the. Further, in the hard-wired method, a control signal for the execution unit is generated by a random logic circuit.

However, in conventional microprogrammed or hard-wired microprocessors, although there is a difference in whether the control section that controls the execution unit is mainly based on a micro ROM or random logic, the general structure of the microprocessor is Both had the configuration shown in FIG.

That is, a microprocessor (CPU) consisting of a control section 1 and an execution unit 2 has an R.
A microcomputer system is configured by connecting a memory 5 such as OM (read only memory) or RAM (random access memory) to an interface chip 6 and the like.

Then, the instruction read from memory 5 (macro instruction)
is taken into the instruction register 12 in the control unit 1 and decoded to form a series of control signals and supplied to the execution unit 2. Then, the execution unit 1 2 operates sequentially in accordance with the control signals and executes processing such as desired calculations and data formation in the interface chip 6 and the like. In other words, not only when a microprocessor performs an operation and outputs the result, but also when the interface chip 6 outputs a control signal to a peripheral device, the conventional microprocessor reads instructions from the memory 5 and sends them to the control unit 1. As a result, the output control signal operates the execution unit 2, and the data is sent to the interface chip 6, where the control signal is generated.

Note that a hard-wired microprocessor is disclosed in, for example, Japanese Patent Application No. 17333/1983.

Incidentally, the time required to execute one instruction in the flow of the memory 5→control unit 1→execution unit 2 is usually about several microseconds or about an instruction cycle (several microseconds). Therefore, when performing normal calculations in a personal computer system, etc., such a required time may be sufficient. , 15, Hui. D, P3-
．． ．． Yuga! When controlling a peripheral device such as a typewriter or a hard disk or floppy disk drive using a 3D controller, the method of sending data from the execution unit 2 to the interface chip 6 to form control signals for the peripheral device is This has the disadvantage that the response speed becomes slow and one peripheral device cannot operate at high speed.

Therefore, conventionally, when configuring a system that controls peripheral devices that require high-speed operation as described above, a dedicated LS such as a disk controller is required for the microprocessor.
I was connected, a control command was sent from the microprocessor, and in accordance with this command, the control LSI formed a specific control signal and output it to the peripheral device.

However, this method of connecting a dedicated control LSI to a microprocessor has the problem that the system becomes complicated and expensive.

[Object of the Invention] An object of the present invention is to provide a data processing technique that can realize high-speed input/output processing functions without using an interface LSI in a system using a microprocessor.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, in a microprogram type microprocessor, the time required to read a microinstruction within the control unit to form an internal control signal (execution of a microinstruction) is approximately 10 times longer than the time required to execute a macroinstruction using an execution unit. Focusing on the fact that it only costs 1/2, micro RO
By newly providing an input/output section (input/output port) inside the microprocessor that is directly controlled by the control signal output from M, the control section can directly control the input/output port without going through the execution unit. This achieves the above objective of speeding up the input/output processing function that operates the input/output ports.

The present invention will be described in detail below along with examples.

[Embodiment] FIG. 1 shows an embodiment of a microprocessor to which the present invention is applied. The part surrounded by a chain line A in the figure is a microprocessor CPU, and the circuit blocks constituting the macroprocessor are as follows: It is formed on a single semiconductor substrate such as silicon.

The microprocessor CPU of this embodiment consists of a control section 1 and an execution unit 2.
to the outside of R via data bus 3 and address by 4.
A memory 5 such as OM or RAM and an interface chip 6 are connected to form a microcomputer system.

The control section 1 is composed of a micro ROM II in which a micro program is stored, an instruction register 2, an address decoder 13, and a micro instruction decoder '14.

The micro ROM II stores one micro instruction for each l address, and when a macro instruction read from the memory 5 via the data bus 3 is fetched into the instruction register 2, the contents of the instruction register are updated to the address. Decoded by the decoder 13, the micro ROMII
The corresponding address within is accessed and one microinstruction is read.

The macroinstruction fetched into the instruction register 2 is executed by reading multiple microinstructions in the microROMII. When the first microinstruction corresponding to the macroinstruction is read out from the microROM 11, the next microinstruction The next microinstruction is read based on the next address written in the address field. In this way, a series of microinstructions are read out one after another, and by being supplied to the microinstruction decoder 14 and decoded, predetermined control signals are sequentially output. The execution unit 2 executes processing corresponding to the above.

On the other hand, the execution unit 2 has a program counter PC
Dedicated registers used for specific purposes such as index registers, accumulators, etc., and general-purpose register group RG for addresses and data used as work areas.
It also has an arithmetic logic unit ALU that performs operations such as addition, subtraction, squaring, and the like. Also, within the execution unit 2, there is an input/output data register DR connected to the data bus to latch input/output data signals, and an address output register MAR to latch the address signal output to the address bus 4. and is provided.

These functional circuits such as registers and ALUs are connected to each other via internal buses 21 to 23, and data is input and output between each functional circuit and the internal buses 21 to 23, respectively. A gate (not shown) is provided. These gates are my own in the control section 1,
By opening and closing the gates in response to control signals output from the microinstruction decoder 14, sequence control according to microinstructions is performed.

Furthermore, in this embodiment, an input/output port 30 is provided which is directly controlled by control signals from a microinstruction decoder 14 that decodes microinstructions read from the microROM II. For example, as shown in FIG. 2, an output buffer 32 and a flip-flop 33 serving as a latch means for determining the output state of the output buffer 32 are connected to an external terminal 31a provided exclusively for the purpose. By controlling the state directly by the control signal from the microinstruction decoder 14 without going through the execution unit 2, control pulses are formed and can be output from the external terminal 31a.

Further, an input buffer 34 is connected to the external terminal 31b provided exclusively for the purpose, so that the input signal applied to the terminal 31b is directly supplied to the control section l via this manual buffer 34. From the input buffer 34 to the control unit 1
The signal supplied to .

For example, it is supplied to the address decoder 13.

The address of the micro ROM is changed to serve as a branch condition for jumping to another appropriate micro instruction.

Therefore, according to this embodiment, like the conventional microprocessor shown in FIG. The micro-instruction directly operates the flip-flop 33 or output buffer 732 of the input/output board 30 to generate an appropriate control pulse, without taking any steps to generate a control pulse for a peripheral device. I can do it.

Therefore, when operating the execution unit 2 to output control pulses from the interface chip 6, as described above, such input/output processing 1 is necessary from fetching the instruction until the actual control pulse is output. It took several to tens of microinstruction cycles to complete. In contrast, according to this embodiment, control pulses can be output from the terminal 31a to the outside by simply reading out a series of microinstructions necessary to execute such input/output processing instructions (macro instructions). . However, since the time required to read one microinstruction is on the order of 1oons, it takes 1μs after fetching the input/output processing instruction.
It becomes possible to output control pulses within a few seconds.

Also, an input buffer 34 controlled by microinstructions
The input signal to the terminal 31b is directly supplied to the control unit 1 through the input terminal 31b to change the address of the micro ROM II, so that when the input signal to the terminal 31b changes, it immediately jumps to another microinstruction. Therefore, there is an advantage that the response of the microprocessor becomes extremely fast.

In the above embodiment, the output buffer 32 and the input buffer 34 constituting the input/output boat 30 are connected to separate external terminals 31a and 31b, respectively.
t-,,,,+t,,mka2,7 tour,□-! The input/output boat can also be configured to be shared with the cover sofa 34. Further, the input/output board 30 is not limited to the configuration consisting of the output buffer 32 and the flip-flop 33, and various modifications such as another configuration having a latch function or a configuration in which the flip-flop 33 is omitted are possible. .

Furthermore, it goes without saying that not only one input/output board 30 may be provided on one chip (microprocessor), but two or more may be provided on one chip (microprocessor).

Furthermore, in the above embodiment, the control unit l is a micro ROMI.
Although the configuration includes a microinstruction decoder 14 that decodes microinstructions read from the microROMII, the microinstruction decoder 14 is omitted and the execution unit 2 and the input/output board 30 are directly controlled by the output from the microROMII. It can also be configured to do so.

Further, in the above embodiment, a macro instruction for directly controlling the input/output board 30 by the output of the control unit (micro ROM) is prepared, and a micro instruction for executing the macro instruction is written in I in the micro ROM. However, it is also possible to make the program of the micro ROM available to users so that they can freely implement high-speed input/output processing functions.

[Effect: The microprocessor is configured in a microprogram format, and an input/output unit (input/output board) is directly controlled by the output of a microROM in which a microprogram is stored or the output from a control decoder that decodes the output. Since it is newly installed inside the microprocessor, the control unit can directly control the input/output board without going through the execution unit, allowing high-speed input/output processing without using a dedicated LSI for the interface. There is an effect that

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, the configuration of the control unit 1 is not limited to the above-mentioned embodiment, and various modifications such as a configuration having a register that holds the next address and a next address decoder that decodes it separately from the address decoder 13 are possible. is possible. The present invention can also be applied to microprocessors that have a multi-chip configuration, that is, where the control section 1 and execution unit 2 are formed not on the same chip but on separate chips. be.

[Field of Application] The above explanation has mainly focused on the application of the invention made by the present inventor to microprocessors constituting a multi-chip microcomputer system, which is the field of application that formed the background of the invention. The present invention is not limited, and can also be used for single-chip microcomputers.

[Brief explanation of the drawing]

1. Fig. 1 is a process diagram showing the configuration of a system using a conventional microprocessor. Fig. 2 is a block diagram showing an embodiment of a microprocessor according to the present invention and a system using the same. It is. CPU...Microprocessor, 1...Control unit, 2...Execution unit, 3...Data bus, 4
...Address bus, 5...Memory, 6...
Interface chip, 11...Memory for microprogram (micro ROM), 12...Instruction registers 1, 13...Address register, 14...
・Micro instruction decoder, 21 to 23...internal bus, 30...input/output section (input/output port), 31a, 3
1b...External terminal, 32...Output buffer, 3
3... Latch means (flip-flop), 34...
・Inner hippo sofa.

Claims (1)

[Claims] 1. A control unit that decodes macro instructions read from a memory in which a program is stored and forms control signals, and has an adder and registers, and is operated by control signals supplied from the control unit; A data processing device comprising an execution unit that performs processing corresponding to a macro instruction, wherein the control section has a microprogram memory in which a microprogram for executing the macro instruction is stored. 1. A data processing device comprising: an input/output section that is directly controlled by an output of the microprogram memory or an output from a microinstruction decoder that decodes the output;