JP2851400B2 - Packet transmission status judgment method - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial application field) The present invention relates to a packet transmission state determination method capable of effectively determining an abnormal packet transmission state.

(Summary of the Invention) In packet transmission according to the present invention, a continuity index whose index monotonically increases for each short packet is added. The present invention observes the discontinuity of the index in an appropriate section, analyzes and identifies the discontinuity of the index according to a predetermined algorithm, accurately detects packet loss, and enables concealment for information loss. This is a determination method in which the received useful packet other than packet loss can be fully utilized.

(Prior Art) In recent years, as a digital transmission method, transmission using cells in an ATM (asynchronous communication mode) in communication and transmission of data packets using fixed-length short packets by data packets have been considered. Also, it is expected that short packet recording will be used for a package medium such as a disk or a tape typified by a CD-ROM.

Conventionally, the continuity index has been used for packet loss detection and rearrangement when the order of packets is changed. In teletext broadcasting, a 4-bit continuity index is set in the prefix part.
It is shown as a complex processing model in the A Teletext Handbook for Teletext Technology and the like. This method is used to check the validity of a packet. The continuity index of the previous packet and the current continuity index are sequentially compared for each packet, and if the index does not continuously increase monotonically, It is determined that the packet is lost.

In the conventional packet communication, the packet arrival order may be changed due to a difference in transmission path. This is rearranged into a formal order using the continuity index, similarly to the former example, and is sequentially performed for each packet.

When a packet is transmitted with a continuity index of several bits added to each packet and the index is received discontinuously, it is considered that one of the following four phenomena has occurred.

(1) Packet loss: Packet loss when the transmission capacity is exceeded, and packet loss due to erroneous delivery due to a header error.

(2) Packet intrusion: Unnecessary packet intrusion due to erroneous delivery due to a header error.

(3) Alteration of packet order: Alteration of the packet arrival order due to a difference in transmission path or the like.

(4) Index number error: change to a different number due to a transmission error of the continuity index.

Failure to accurately identify each of these phenomena can result in the loss of available packet data or the use of unnecessary packets by accidentally discarding the necessary packets.

(Problems to be Solved by the Invention) However, since the conventional teletext method only sequentially compares the continuity index of a packet with the previous continuity index, if there is a packet intrusion, the next correct packet is also discarded. And it is impossible to distinguish between packet order change and index number error.

In addition, the method used in communication has a problem that if there is a packet intrusion or an index error, the packet order change cannot be correctly rearranged, and packet loss cannot be accurately detected.

The present invention monitors the continuity index over an appropriate period, not every packet arrival, and uses the characteristics of each phenomenon that causes the discontinuity index to accurately grasp the discontinuity state and to determine the packet loss. To save useful packet data.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above-mentioned object, the invention according to claim (1) has an n-bit increasing monotonically increasing for each transmission packet as shown in FIG. A continuity index extracting means 103 for observing an incoming packet to which the continuity index 101 is added over at least three consecutive times and extracting a continuity index 102 in each incoming packet.
And a difference value D1 calculating means 104 for obtaining each difference value D1 by a modulo operation for each difference between the extracted index 102 and the expected normal continuity index, and each time series difference adjacent to each difference value D1 A difference value D2 calculating means 105 for calculating each difference value D2 by modulo calculation, a discontinuous section length calculating means 106 for calculating a section length T where the index 102 extracted from the calculation result of the difference value D2 is discontinuous, An addition value S1 calculating means 107 for obtaining an addition value S1 by a modulo operation on a difference value D1 in which the value in the continuous section length T is not 0; An addition value S2 calculating means 108 for obtaining an addition value S2 by an operation;
Simple sum SS2 to find the simple sum SS2 of the difference value D2 that is not
The calculating means 109, the added value S1, the added value S2 and the simple added value
Determining means 110 for determining the transmission state of the incoming packet from each calculation result of SS2.

The invention according to claim (2) is characterized in that the determination means 110
When the addition value S2 = 0 and the addition value S1 ≠ 0 hold, it is determined that there is an error in the continuous index number, and the addition value S2 = 0.
And when the addition value S1 = 0 is satisfied, it is determined that there is alternation in the packet order, and when the addition value S2 ≠ 0 is satisfied, it is determined that packet intrusion or packet loss has occurred, and When the function of the discontinuous section length T + S2 = 2 ⁿ +1 (n is the number of bits of the continuity index) is satisfied, it is determined that there is a packet intrusion, and when the simple addition value SS2 <2 ⁿ is satisfied, there is a packet loss. And T + S2 = 2 ⁿ
When both SS2 and SS2 < ²ⁿ do not hold, it is determined that there is a compound error.

(Operation) According to the above configuration, an incoming packet to which an n-bit continuity index is added is observed for at least three or more continuations, and a continuity index of each packet is extracted. Then, a difference value D1 obtained by modulo operation on a difference between the extracted index and the expected normal continuity index, and each difference value D1 adjacent to the difference value D1
A difference value D2 obtained by a modulo operation for each difference between them and a discontinuous section length T of the extracted index are obtained.

Further, an addition value S1 by a modulo operation on the difference value D1 in which the value within the discontinuous section length T is not 0, an addition value S2 by the modulo operation on the difference value D2, and a simple addition value SS2 on the difference value D2 are obtained. , An error in packet transmission is accurately determined.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of a receiver to which the method of the present invention is applied.

This receiver includes an index extraction circuit 1 constituting a continuity index extraction means 103, a reference index counter 2 and a difference circuit (mod 2 ⁿ ) 3 constituting a difference value D1 calculation means 104, and a difference value D2
The delay circuit 4 and the difference circuit (mod 2
ⁿ ) 5, "0" coincidence detection circuit 6, continuity check circuit 7, delay circuit 8, flip-flop 9 and discontinuous section length counter 10 constituting discontinuous section length computing means 106, and addition value S1 computing means
An adder circuit (mod 2 ⁿ ) 11 forming the adder 107, an adder circuit (mod 2 ⁿ ) 12 forming the adder value S2 calculator 108, an adder circuit 13 forming the simple adder SS2 calculator 109, 11
"0" coincidence detection circuits 14 and 15, which constitute 0, and addition circuits 16, 2 ⁿ
+1 coincidence detection circuit 17, 2 ⁿ comparison circuit 18 and AND circuits 19-2
And three. The output signal of the AND circuit 19 is sent to the index number correction circuit 24, the output signal of the AND circuit 20 is sent to the packet order rearranging circuit 25, the output signal of the AND circuit 21 is sent to the intrusion packet elimination circuit 26, and the output signal of the AND circuit 22 is sent to the The output signal of the lost packet concealment circuit 27 and the output signal of the AND circuit 23 are supplied to the discontinuous section length concealment circuit 28.

In the above configuration, the index extraction circuit 1 observes incoming packets to which an n-bit continuity index that monotonically increases for each transmission packet is added, and extracts a continuity index from each incoming packet.

Next, as shown in the flowchart of FIG. 3, the difference circuit (mod 2 ⁿ ) 3 extracts the continuity index R _i and the expected normal continuity index I _i supplied from the reference index counter 2. And executes a modulo operation on each of the differences based on the expression (1). Note that n indicates the number of bits used for the index.

D1 _i = R _i −I _i [mod 2 ⁿ ] (1) For example, as shown in FIG. 4A, when n = 3 bits, that is, as a continuity index, from 0 to 7 in decimal. Is assumed to be added for each packet, and the extracted continuity index R _i is [4 5 6 4 1 6 2 3], the expected normal continuity index I _i is [4 5 6 7 0 1 2 3], the difference value D1 _i by the modulo operation on the difference for each index is [0 0 0 5 1 5 0 0].

In this way, when the difference value D1 _i is obtained,
Difference value D2 is divided delayed one index by the delay circuit 4, and these delay indicator value a, the difference value D2 _i is the difference circuit modulo operation on the difference between adjacent difference value D1 _i (mod
2 ⁿ ) 5, based on equation (2).

D2 _i = D1 _{i + 1} −D1 _i [mod 2 ⁿ ] (2) Taking the example of FIG. 4A as an example, this difference value D2 _i becomes [0 0 5 4 4 3 0 0] ( Step 201).

Next, the “0” match detection circuit 6 determines whether or not each of the difference values D2 _i is “0”, and if “0”, outputs a match signal b to the continuity check circuit 7; If it is not "0", the mismatch signal c is output to the continuity check circuit 7 and the delay circuit 8.

The continuity check circuit 7 is turned on when a predetermined number m of coincidence signals b are continuously input in order to confirm that the extracted index value is correctly and monotonically increasing, and the non-coincidence signal c is output. A continuation confirmation signal d which is turned off when input is generated and output to the flip-flop 9.

One delay circuit 8 generates a delay signal e obtained by delaying the mismatch signal c by m, and outputs the delay signal e to the flip-flop 9.

The flip-flop 9 receives the continuity check signal d and the delay signal e and outputs a discontinuous section gate signal f to the discontinuous section length counter 10. The discontinuous section length counter 10 obtains the discontinuous section length T by counting the input discontinuous section gate signal f (step 202). In the example shown in FIG. 3A, the discontinuous section length T = 4.

On the other hand, the discontinuous section gate signal f is supplied to the reference index counter 2, and when the index returns from discontinuous to continuous, the current incoming continuity index _Ri is predicted in the reference index counter 2. _Is reset as the normal continuity index Ii.

Next, based on the difference value D1 _i , the difference value D2 _i and the discontinuous section length T, an addition value S1, an addition value S2, and a simple addition value SS2 are obtained as follows (step 203).

The adder circuit (mod 2 ⁿ ) 11 performs a modulo operation on the sum of the periods in which the difference value D1 _i is not 0 to obtain an addition value S1.
When shown FIG. 4 (A) is an example, and S1 = (5 + 1 + 5 ) mod 2 3 = 11mod 8 = 3.

The adder circuit (mod 2 ⁿ ) 12 performs a modulo operation on the sum of the periods in which the difference value D2 _i is not 0 to obtain an addition value S2.
When shown FIG. 4 (A) is an example, and S2 = (5 + 4 + 4 + 3) mod 2 3 = 16mod 8 = 0.

Addition circuit 13 obtains a simple sum of the difference values D2 _i. In the example shown in FIG. 4A, SS2 = 5 + 4 + 4 + 3 = 11.

In the flowchart of FIG. 3, the processing after step 204 is executed by the determination means 110 ("0" coincidence detection circuit 14 to gate circuits 19 to 23). In the determination method of the present invention, it is assumed that only one kind of index discontinuity occurs at the same time. This is because a compound error that occurs when a plurality of phenomena coexist at the same time is stochastically low and is considered to hardly occur.

The “0” match detection circuit 14 determines whether or not the addition value S1 = 0 is established. When S1 ≠ 0, the high-level signal is output as S1 = 0.
In this case, the low level signal is used as the determination signal g and the AND circuit 1
Output to 9,20.

The “0” match detection circuit 15 determines whether or not the addition value S2 = 0 holds, and when S2 ≠ 0, outputs a high-level signal to S2 = 0.
In this case, a low-level signal is used as a determination signal h and each AND circuit
Output to 19-23.

The addition circuit 16 generates an addition signal T + S2 of the discontinuous section length T and the addition value S2, and outputs the signal to the 2 ⁿ +1 coincidence detection circuit 17.

The 2 ⁿ +1 coincidence detection circuit 17 determines whether or not T + S2 = 2 ⁿ +1 is satisfied. If so, the high-level signal is used. If not, the low-level signal is used as the determination signal i, and the AND circuit 21, Output to 22,23.

The ²ⁿ comparison circuit 18 receives the simple addition SS2 signal supplied from the addition circuit 13 and determines whether or not SS2 < ²ⁿ is satisfied. Are the AND circuits 22, 23 using the low level signal as the determination signal o.
Output to

The processing of step 204 and subsequent steps in FIG. 3 shows a packet discrimination method.

That is, the AND circuit 19 inputs the discrimination signals h and g (inverted signals) of the "0" coincidence detection circuits 15 and 14 and when the addition value S2 = 0 and the addition value S1 ≠ 0 hold (step 204 in FIG. 3). , 20
5), the number error is discriminated, and the number error detection signal p is output to the index number correcting circuit 24, and the index of the discontinuous section length T is corrected (steps 206 and 207). FIG. 4A shows a case where the index numbers (4, 1, 6) of three packets are incorrect.

On the other hand, the AND circuit 20 inputs the judgment signals g and h and when the added value S2 = 0 and S1 = 0 hold (step 20).
4, 205), the packet order error is discriminated, and the order error detection signal q is output to the packet order rearranging circuit 25 to cause the packets within the discontinuous section length T to be rearranged in the correct order (steps 208, 209). FIG. 4B shows that the order of the three packets has been changed.

The AND circuit 21 inputs the discrimination signal h (inverted), i, and when the added value S2 ≠ 0 and T + S2 = 2 ⁿ +1 holds (steps 204 and 210), discriminates the packet intrusion and outputs the packet intrusion detection signal. r to the intrusion packet elimination circuit 26 to eliminate 2 ⁿ -S2 intrusion packets (step 21
1,212). FIG. 4C shows a case where three packets have entered.

The AND circuit 22 receives the discrimination signals h (inverted), i (inverted), and o, and the addition value S2 ≠ 0, T + S2 ≠ 2 ⁿ +1, and the simple addition value SS2 <2 ⁿ are all satisfied. When you do (Step 2
04, 210, 213), it is determined that the packet is lost, and the packet loss detection signal s is output to the lost packet concealment circuit 27 to conceal the lost packet (step).
214,215,216). FIG. 4D shows a case where three packets have been lost.

Also, the AND circuit 23 inputs the discrimination signals r, i, o (all inverted) and the addition value S2 ≠ 0 and T + S2 ≠ 2 ⁿ +1 hold, but if SS2 <2 ⁿ does not hold, The composite error detection signal u is output to the discontinuous section length concealment circuit 28 to conceal all packet data of the continuous section length T (steps 217 and 218).

Summarizing the above processing, the addition value S2 = 0 when an error occurs in either the continuity index number or the packet order is changed.

Therefore, it is determined whether or not the added value S1 = 0 (step 20).
5) When S1 is not 0, it is determined that the continuity index number is erroneous, and the index correction processing of the discontinuous section length T which is an error section is executed (steps 206 and 207).

When the addition value S1 = 0, the packet order in the section T is rearranged in the correct order because it is limited to the case where the packet order is changed (steps 208 and 209).

On the other hand, when the addition value S2 is not 0, it means that a packet intrusion or packet loss and a composite error have occurred.

Next, in packet loss and packet intrusion, the number of lost packets has a value of S2, and the number of intruded packets has a value of 2 ⁿ -S2. That is, if the value of S2 is less than 2n, the value does not become 0, so that it can be identified as a phenomenon of packet order change and continuity index number error.

Further, when the relationship of T + S2 = 2 ⁿ +1 is satisfied, the phenomenon is limited to the packet intrusion phenomenon (steps 210 and 211). In this case, intrusion elimination processing of 2 ⁿ -S2 packets is executed (step 212).

On the other hand, in the case of packet loss, SS2 <2 ⁿ is satisfied (steps 213 and 214). In other cases, a composite error is determined (step 217), and correct identification becomes impossible. Therefore, in the case of packet loss, a packet in the discontinuous section T is secured, and concealment of lost data is performed (steps 215 and 216).

Thus, according to the present embodiment, the index number error,
Packet order change, packet intrusion, packet loss, and compound error can be accurately determined.

[Effect of the Invention] As described above, according to the present invention, not only the immediately preceding continuity index but also at least three or more continuity indexes are observed, and various phenomena of the discontinuous index are determined according to a predetermined algorithm. Since analysis and identification are performed, packet loss, packet intrusion, packet order change, and continuity index number error can be accurately determined and identified.

As a result, it is possible to save a packet having necessary data that has been discarded because it cannot be identified conventionally, and use it as information.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of the present invention, FIG. 2 is a block diagram showing an embodiment of a receiver to which the present invention is applied, FIG. 3 is a flowchart showing a processing procedure of an embodiment of the present invention, FIG. 4 is a diagram for explaining the operation of the embodiment. 101: Continuity index 102: Incoming (extracted) index 103: Continuity index extraction means 104: Difference value D1 calculation means 105: Difference value D2 calculation means 106: Discontinuous section length calculation means 107 ... Addition value S1 calculation means 108 ... Addition value S2 calculation means 109 ... Simple addition value SS2 calculation means 110 ... Determination means

Claims (2)

(57) [Claims] A continuity index extracting means for observing at least three consecutive incoming packets to which an n-bit continuity index monotonically increasing for each transmission packet is added and extracting a continuity index in each incoming packet. And a difference value D1 for obtaining each difference value D1 by a modulo operation for each difference between the extracted index and the expected normal continuity index.
Calculation means, difference value D2 calculation means for calculating each difference value D2 by modulo calculation for each difference between adjacent time series difference values D1, and an index extracted from the calculation result of the difference value D2 is discontinuous. A discontinuous section length calculating means for obtaining a section length T; an adding value S1 calculating means for obtaining an addition value S1 by a modulo operation on a difference value D1 having a non-zero value in the discontinuous section length T; Value S2 calculating means for obtaining an addition value S2 by a modulo operation with respect to a difference value D2 having a non-zero value, and a simple addition value of the difference value D2 having a non-zero value within the discontinuous section length T
A packet comprising: a simple addition value SS2 calculating means for obtaining SS2; and a determination means for determining a transmission state of an incoming packet from each calculation result of the addition value S1, the addition value S2 and the simple addition value SS2. Transmission status determination method. 2. The judgment means judges that there is an error in the continuous index number when the addition value S2 = 0 and the addition value S1 成立 0 holds, and the addition value S2 = 0.
And when the addition value S1 = 0 is satisfied, it is determined that there is alternation in the packet order. When the addition value S2 ≠ 0 is satisfied, it is determined that packet intrusion or packet loss has occurred, and When the function of the discontinuous section length T + S2 = 2 ⁿ +1 (n is the number of bits of the continuity index) is satisfied, it is determined that there is a packet intrusion, and when the simple addition value SS2 <2 ⁿ is satisfied, there is a packet loss. The packet transmission state determination method according to claim 1, wherein if T + S2 = ²ⁿ and SS2 < ²ⁿ are not satisfied, it is determined that there is a compound error.