JP2845644B2 - Line slip compatible echo canceller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an echo canceller.

[0002]

2. Description of the Related Art Conventionally, this type of echo canceller 1 '
Is a subtractor 17, a calculation circuit 14, an H (tap coefficient value holding) register 12, an X register 13, a tap coefficient correction circuit 19, a transmission side input terminal 3, a reception side output terminal 4, a transmission side output terminal 5, and a reception side. Echo path 2 consisting of input terminal 6
, An X register 13, a tap coefficient correction circuit 19, an H register 12, and a calculation circuit 14 in the echo canceller 1 'generate a pseudo echo signal, and a subtractor 17 generates a pseudo echo signal and an actual echo signal. In some cases, the actual echo signal is canceled by taking the difference from the signal.

The operation will be described below. The signal transmitted from the far end speaker side on the communication line
It returns to the far-end speaker as an echo due to impedance mismatch of the transformer circuit. The echo canceller 1 'shown in FIG. 2 is used to eliminate this echo signal.
Generally, the circling echo path 2 can be regarded as constantly linear. Therefore, assuming that the impulse response of the echo path 2 is h (i) (i = 0, 1, 2,..., N−1), the actual echo signal Y (j) at the time j is the received signal x
From (j), it can be represented by the following Equation 1.

[0004]

(Equation 1)

An echo path model having the same characteristics is generated inside the echo canceller 1 '. If the impulse response inside the echo canceller 1 'for generating the pseudo echo signal Y' (j) is represented by h '(i), it can be represented by the following equation (2).

[0006]

(Equation 2)

When h (i) = h '(i) holds,
Y (j) = Y ′ (j), and the echo signal Y (j) is deleted. This is the algorithm of the echo canceller. To realize this, an input signal sent from the far-end speaker is input from the receiving input terminal 6, the signal is held in the X register 13, and the H register 12 is
The impulse response is stored as a tap coefficient. The calculation circuit 14 calculates a product h '(i) × (ji) of each tap, and further performs a summation of N products. The value obtained here is the above Y '(j). From the output result of the calculation circuit 14, the echo signal Y input from the transmission-side input terminal 3 is obtained.
(J) is subtracted by the subtractor 17. The operation result of the subtracter 17 is transmitted to the transmission output terminal 5 and sent out of the circuit as a signal from which the echo signal has been deleted. The output of the H register 12, the difference signal of the operation result of the subtractor 17, and the output of the X register 13 are input to the tap coefficient correction circuit 19.
The output of the tap coefficient correction circuit 19 is
Is corrected so that h '(i) becomes as close as possible to h (i). Thus, the echo signal Y (j) is eliminated as much as possible.

[0008]

However, in the above-described echo canceller 1 ', when the data is shifted by one sample period due to the jitter occurring in the digital line or the slip caused by the annual delay fluctuation, etc.
The pseudo echo signal is significantly different from the true echo signal, and the estimation operation in the H register 12 has to be performed, and it takes a considerable time to complete the correction. As a result, immediately after the slip has occurred, there is a drawback that the echo signal remarkably wraps around.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a line slip compatible echo canceller which can remove an echo signal even if data is shifted by one sample period due to a slip caused by a jitter occurring in a digital line or an annual delay variation. is there.

[0010]

According to the present invention, an echo signal generated from a signal transmitted from a far-end talker is deleted by adaptively changing a tap coefficient in accordance with an impulse response of an echo path. In the echo canceller, a first delay unit for delaying the input signal on the transmission side by two taps, a tap coefficient value holding register for holding the tap coefficient value of the echo canceller, and a tap unit for calculating the product sum of the input signal on the reception side. A second delay unit for delaying the tap coefficient value of the numerical value holding register by two taps, three subtractors for subtracting a pseudo echo signal from two outputs of the first delay unit and a transmission side input signal, and three outputs The number of tap delays in the level comparator that compares the level of the result and the tap coefficient value holding register that calculates the sum of products based on the result of the level determination, and the sum of products with the X register An echo canceller is obtained, characterized in that it comprises a switching circuit for determining.

[0011]

Referring to FIG. 1, a line slip compatible echo canceller 1 according to an embodiment of the present invention includes a delay unit 7 for delaying a signal input from a transmission side input terminal 3 by one sample period. The delay unit 8 converts the output signal of the delay unit 7 into 1
Delay by the sample period. H register tap delay unit 9
And 10 each set the tap coefficient in the H register 12 to 1
Delay the tap. The switching circuit 11 is a level comparator 1
From the result of 8, it is determined how many taps the coefficient value of the H register 12 is shifted. The H register 12 estimates the echo path 2 and holds the tap coefficient values of the impulse response for N taps. The X register 13 converts the signal input from the receiving-side input terminal 6 into (the number of taps +
The data of 1) is retained. The calculation circuit 14 has the H register 1
The product of 2 and the contents of the X register 13 is calculated for each tap, and the sum of the products for N taps is calculated. Subtractor 1
7 subtracts the output signal of the calculation circuit 14 from the signal received from the transmission-side input terminal 3. The subtractor 16 subtracts the output signal of the calculation circuit 14 from the signal after the signal received from the transmission-side input terminal 3 has passed only through the delay unit 7. Subtractor 15
Subtracts the output signal of the calculation circuit 14 from the signal that the signal received from the transmission side input terminal 3 has passed through the delay units 7 and 8. The level comparator 18 compares levels of the operation results of the subtracters 15, 16, and 17, and compares the comparison result with the switching circuit 1.
1, the tap coefficient of the H register 12 is not shifted, the tap is delayed by one tap by the delay unit 9, or the tap coefficients are delayed by two taps by the delay units 9 and 10.
The tap coefficient correction circuit 19 uses the difference signal transmitted to the transmission side output terminal 5 and the value of the X register 13
The tap coefficient value within 2 is made closer to the impulse response of the echo path 2.

The operation of the echo canceller 1 shown in FIG. 1 will be described below. The signal transmitted from the far-end speaker is received by the receiving input terminal 6, held in the X register 13, and transmitted to the receiving output terminal 4. The signal output from the transmission output terminal 4 is input to the transmission input terminal 3 through the echo path 2. This is the echo signal. The signal is supplied to the subtractor 17 as it is, the signal supplied to the subtractor 16 after being delayed by one sample by the delay unit 7, and the signal supplied to the subtractor 16 by the delay units 7 and 8.
The signal is divided into three echo signals including a signal delayed by a sample and supplied to the subtractor 15. On the other hand, the calculation circuit 14
Represents the tap coefficient value in the H register 12 and the X register 13
Is calculated for each tap, and the sum of products for N taps is calculated. Subtractors 15, 16 and 17
Subtracts the output result of the calculation circuit 14 from each of the three echo signals. In the standard time, the result of the subtractor 16 is transmitted to the output terminal 5 on the transmission side. The tap coefficient correction circuit 19 uses the result of the subtractor 16 and the value of the X register 13.
Then, the tap coefficient of the H register 12 is corrected to bring the tap coefficient value of the X register 13 closer to the impulse response of the echo path 2. By the way, at this time, one sample period data may be shifted due to a slip caused by a jitter or an annual delay fluctuation on the digital line. When this slip phenomenon occurs, the echo canceller 1 determines that the echo path 2 has significantly changed, and starts correcting the tap coefficient again. It takes a considerable amount of time to complete the correction. However, when a slip phenomenon actually occurs, a shift occurs around one sample. That is, if the impulse response h '(i) inside the echo canceller 1 is sufficiently equal to the impulse response h (i) of the echo path 2, the actual echo signal Y (j) at the time j is Almost coincides with any one of the pseudo echo signals Y '(j), Y' (j-1), and Y '(j-2) shown by Expressions 3, 4, and 5, respectively. There should be.

[0013]

(Equation 3)

[0014]

(Equation 4)

[0015]

(Equation 5)

That is, in the present echo canceller 1, calculation and estimation are performed using the signal Y (j-1) obtained by delaying Y (j) by one sample in the standard time, and the data is shifted forward by slip. When the data is shifted backward, the subtraction is performed by Y '(j), and when the data is shifted backward, the subtraction is performed by Y' (j-2). In order to realize the principle, in the echo canceller 1 of the present invention, the input signal from the transmission-side input terminal 3 is converted into Y (j), Y (j-1), Y (j- In the standard case, a signal obtained by delaying the tap coefficient value in the H register 12 by one sample is supplied to the calculation circuit 14, and the output signal of the calculation circuit 14 and Y 'represented by the following equation (6) are provided. The subtraction with (j) is performed by the subtracters 15, 16, and 17, and the level comparison is performed by the level comparator 18.

[0017]

(Equation 6)

If a slip phenomenon occurs on the line, the output level of the subtractor 17 becomes the lowest if the slip occurs forward, and the output level of the subtractor 15 becomes the lowest if the slip occurs. It is the lowest. If the output level of the other subtractor becomes lower than the output level of the subtractor 16, the correction operation of the H register 12 of the echo canceller is temporarily stopped, and the level of about several tens of samples is detected. Is the lowest, the value of the H register 12 is delayed by one sample only once, and the calculation circuit 14 performs the operation of the following equation (7).

[0019]

(Equation 7)

When the level of the subtractor 17 is the lowest, the arithmetic circuit 14 is caused to perform the operation of the following equation 8 without delaying the value of the H register only once.

[0021]

(Equation 8)

After that, the operation is returned in the same manner as the normal route, the operation is performed using the tap coefficient value of the H register 12 which is one sample delayed from the H register 12, the subtractor 16 performs subtraction to remove the echo signal, and removes the echo signal. Sends a signal.
The tap coefficient is corrected using the difference signal, and the echo signal is deleted while performing the correction operation. In this case, actually, data of N + 1 taps is held in the X register 13, but tap terms are forcibly set to 0 for terms for which sum of products cannot be obtained. In this case, a slight error occurs for a moment, but the difference is extremely small, and it is not a value that has almost no effect if the correction is repeated.

[0023]

As described above, according to the present invention, when one sample period data is shifted due to a jitter generated in a digital line or a slip generated due to an annual delay variation, a pseudo echo significantly differs from an actual echo signal. As a result of solving the disadvantage that the estimation operation in the H register has to be performed and a considerable time is required for the correction to be completed, immediately after the slip occurs, the echo signal is remarkably increased. This has the effect of solving the drawback that wraparound occurs.

[Brief description of the drawings]

FIG. 1 is a block diagram of a line slip compatible echo canceller according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional line-slip-compatible echo canceller. REFERENCE SIGNS LIST 1 echo canceller 2 echo path 3 transmission-side input terminal 4 reception-side output terminal 5 transmission-side output terminal 6 reception-side input terminal 7,8 delay unit 9,10 H register tap delay unit 11 switching circuit 12 H register 13 X register 14 Calculation Circuit 15, 16, 17 Subtractor 18 Level comparator 19 Tap coefficient correction circuit.

Continuation of the front page (56) References JP-A-57-60741 (JP, A) JP-A-64-44636 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04B 3 / 20-3/23 H04B 7/005-7/01 H04M 1/58-1/60 H03H 21/00

Claims (1)

(57) [Claims] 1. An echo canceller for adaptively changing a tap coefficient in accordance with an impulse response of an echo path to cancel an echo signal generated from a signal transmitted from a far-end talker side and canceling the input signal on the transmission side by two. A first delay unit for delaying taps, a tap coefficient value holding register for holding the tap coefficient value of the echo canceller, and a tap coefficient value of the tap coefficient value holding register for two taps when calculating the sum of products of the input signals on the receiving side A second delay device for delaying the first
Three subtractors for subtracting the pseudo echo signal from the two outputs of the delay unit and the input signal on the transmitting side, a level comparator for comparing the levels of the three output results, and a tap for obtaining a sum of products based on the determination result of the level An echo canceller comprising a switching circuit for determining how many tap delays are made in a coefficient value holding register and a product sum with an X register is obtained.