JPH0793596B2 - Echo canceller device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] An echo canceller device for canceling an echo in a communication system in which an echo of a large ground time occurs such as an international telephone communication and a high-efficiency codec introduction line. For the purpose of reducing the amount of calculation such as stabilization processing, the echo path estimation impulse response sequence whose size is adaptively changed is used as a filter coefficient, and the received signal sequence is input and a pseudo echo signal is output. Equipped with an echo generator,
In an echo canceller device for canceling an actual echo component by the pseudo echo signal, a superimposing means for superimposing a constant DC component on the input signal of the pseudo echo generating unit, and a DC component of the output signal of the pseudo echo generating unit. DC blocking means for blocking, constant setting means for setting an addition constant and a multiplication constant based on the magnitude of the DC component of the output signal of the pseudo echo generating section, and filter coefficients of the pseudo echo generating section in a plurality of groups. It is configured to include a processing unit that divides and sequentially performs addition processing of addition constants and multiplication processing of multiplication constants set by the constant setting unit for each group.

[Industrial application field]

The present invention relates to an echo canceller device for canceling an echo in a communication system in which an echo with a large delay time occurs such as in international telephone communication and a high efficiency codec introduction line.

Due to the impedance mismatch in the hybrid circuit that performs 2-wire to 4-wire conversion, a part of the voice signal from the talker wraps around and an echo is sent back to the talker. There are few problems when the delay time of the echo on the short distance line is short, but when the delay time of the long distance line is large, the effect of the echo becomes large and the call is disturbed. . Therefore, it is necessary to suppress or cancel the echo component.

[Conventional technology]

The general telephone and the exchange are connected by two subscriber lines, and the exchange connection processing is performed at the number 4 in the exchange. Therefore, a hybrid circuit for exchanging the four lines on the exchange side and the two lines on the subscriber side is provided on the exchange side. If the impedance matching in this hybrid circuit is perfect, no echo is generated, but the length and configuration of the subscribers connected to the hybrid circuit differ from each other, and temperature changes etc. occur, so impedance matching is not achieved. It will be collapsed, and a sneak signal through the hybrid circuit is generated. This wraparound signal becomes an echo component, and when the delay time due to the line or codec is long, the influence of the echo component becomes large and the speech quality deteriorates. Therefore, an echo canceller device for canceling this echo component. Is provided.

For example, as shown in FIG. 6, a two-line subscriber line 54 is connected to the hybrid circuit 52 of the exchange 51, and the subscriber line 54
The telephone 55 is connected to. When the impedance matching of the hybrid circuit 52 is in an ideal state, a wraparound signal indicated by an arrow, that is, an echo component does not occur, but as described above, it is difficult to maintain ideal impedance matching. Normally, a wraparound signal indicated by an arrow, that is, an echo component is generated. Since this echo component is transmitted to the telephone of the other party (not shown) and deteriorates the call quality, it is canceled by the echo canceller device 53 and only the voice signal from the telephone 55 is transmitted to the telephone of the other party.

The echo canceller device 53 includes terminals RIN, ROUT, SIN, SOUT, a voice signal from the partner telephone is added to the terminal RIN, and a voice signal from the terminal ROUT is transmitted to the telephone 55 via the hybrid circuit 52. The voice signal from the telephone 55 is applied to the terminal SIN via the hybrid circuit 52.
At this time, the echo component via the hybrid circuit 52 is also connected to the terminal.
It will be added to SIN, and based on the audio signal applied to the terminal RIN, a pseudo echo signal with a waveform similar to this echo component will be formed, and the echo component will be canceled by this pseudo echo signal and sent out from the terminal SOUT. To do.

FIG. 7 is a block diagram of a main part of a conventional example of the above-mentioned echo canceller device. 61 is a pseudo echo generation unit, 62 is a received signal storage memory, 63 is an echo path estimation impulse response storage memory, 64 is an adder, and 65 is an adder. Is a coefficient correction unit, and 66 is a coefficient control unit that performs components such as rounding off of coefficients. The function of each unit can be realized by a general-purpose digital signal processor.

The reception input signal from the partner telephone applied to the terminal RIN is sent from the terminal ROUT to a hybrid circuit (not shown) and is also stored in the reception signal storage memory 62. The pseudo echo generating unit 61 has a transversal filter configuration, and the received signal sequence read from the received signal storage memory 62 corresponding to the time of the echo component applied to the terminal SIN becomes the input signal, and the echo path estimation impulse response The echo path estimation impulse response sequence read from the storage memory 63 serves as a filter coefficient, and a pseudo echo signal having a waveform similar to the waveform of the echo component is output, and this pseudo echo signal is output to the terminal SIN at the adder 64. The added echo component will be canceled.

The cancellation residual signal of the echo component from the adder 64 is
An error signal is added to the coefficient correction unit 65, and the coefficient control unit 66
Coefficient control such as rounding processing is performed, and the coefficient corrected corresponding to the error signal is stored in the echo path estimation impulse response storage memory 63.

The received input signal sequence applied to the terminal RIN from the partner telephone is x _j , the echo signal sequence when the transmission input signal applied to the terminal SIN is only the echo component, y _j , and the pseudo echo signal sequence is
_j , and the transmission output signal sequence from the terminal SOUT is e _j ,
This e _j is represented as a difference between the true echo signal and the pseudo echo signal when there is no transmission input voice signal, and can be referred to as an error signal sequence output from the adder 64. For voice signals, communication is performed using a PCM codec, for example, 1
It is sampled at a period of 25 μs and converted into a digital signal, and the subscript j indicates a value at t = j. Each of the above-mentioned signal sequences is e _j = y _j − _j (1) It becomes a relationship. Here, h _i ^(j) is a filter coefficient of the transversal filter for generating pseudo echo, and N is the order of the filter, that is, the number of taps, and is related to the maximum delay time of the echo that can be handled.

The transversal filter that constitutes the pseudo echo generating section 61 performs the calculation of equation (2) to obtain the pseudo echo signal sequence _j . Using the error signal sequence e _j obtained as the difference between the true echo signal sequence y _j and the pseudo echo signal sequence _j , all the filter coefficients h _{i for} each cycle according to the equation (3).
^(j) Modify (i = 0,1,2, ... N-1). Also, α is a positive constant. As described above, the method of adaptively changing the coefficient of the transversal filter according to the equation (3) to sequentially bring the error signal series e _j close to zero is called a learning identification method.

Regarding the amount of calculation that is closely related to the scale of hardware in performing the above-described calculation processing, from the relationship of N × cycle = maximum equalization delay time, the larger the filter order N, the greater the delay time. Although a large echo can be dealt with, a high-performance echo canceller can be configured. However, if the filter order N is increased, the number of product sums in equation (2) and the number of correction processes in equation (3) are increased. Because it will increase
High-speed arithmetic processing is required. However, the denominator of the second term on the left side of the equation (3) is the sum of squares of the received input signal applied to the terminal RIN from t = j−N + 1 to t = j, and t = j
Let I _j be the value at Since it can be processed by two multiplications and two additions regardless of the magnitude of the filter order N, there is no burden in terms of the amount of calculation. Further, if αe _j / I _j = W _j and the coefficient W _j is calculated once every cycle, it can be commonly used for N times of calculation of the equation (3).

Rewriting Eq. (3) using this coefficient W _j gives h _j ^(j) + W _j x _{j-N + 1 + i} = h _j ^{(j + 1)} (4). The coefficient correction unit 65 performs such processing.

The calculation of the equation (4) is performed by using the registers A, B, and D, and A × B
The basic processing flow in the case of using a general-purpose digital signal processor capable of performing × D → D arithmetic
Shown in the figure. In the figure, (1), (2), ... represents a step, first advance load the W _j to B register (1), then load the x _{j-N + 1} in the register (2), then
Load h ₁ ^(j) into the D register (3), and in the next step (4), h ₁ into the D register by the operation of A × B + D → D.
Generate ^{(j + 1)} and load _{xj-N + 2} into the A register. The content of the D register is stored in the memory in the next step (5), h ₂ ^(j) is loaded into the D register in the next step (6), and the operation of A × B + D → D is performed in the next step (7). And x _{j-N + 3} into the A register.

Therefore, as shown in steps (4) and (7), the A register is loaded in parallel with the arithmetic processing, and the calculation of the equation (4) for one filter coefficient has a calculation amount of 3 steps.

However, in reality, the bit size of the A and B registers and the memory in the general-purpose digital signal processor is 16 bits, and the D register in which the multiplication result is generated is 32 bits, so the contents of the D register are stored in the memory. When storing to, the lower 16 bits will be truncated.

This rounding down of the lower 16 bits results in 16
It is considered that it affects only whether or not the 1st bit is 1, and it does not pose a problem so much, but since the truncation processing is performed for each filter coefficient 8000 times per second, the error accumulates and the filter coefficient h _i The values will deviate significantly from what they should be. Since the general-purpose digital signal processor is normally processed in the two's complement format, the value is shifted to the left on the numerical line by the truncation processing. That is,
Positive numbers become smaller and negative numbers become larger in absolute value.
Therefore, if the truncation process is left as it is, the filter coefficient h _i becomes smaller and smaller, reaching the lower limit of -2 or -1 that can be taken in the general-purpose digital signal processor and causing an overflow phenomenon.

Therefore, in the echo canceller device of the conventional example, the processing according to the flowchart shown in FIG. 9 is performed, and (11), (12), ... Show steps. First, W _j
Is loaded into the B register (11), and then x _{j-N + 1 is set} to A
Load into register (12), then from D register upper
A 1 is set at the 17th bit (13), then h ₀ ^(j) is loaded into the A register, and an arithmetic process of A × B + D → D is performed (14). Then load x _{j-N + 2} into the A register and A +
The operation of D → D is performed (15), and then the contents of the D register are stored in the memory (16).

Therefore, by registering 1 to the 17th bit of the D register, W _j ×
The process of adding x _{j-N + i + 1} and further adding h _i ^(j) will be performed, whereby the calculation of h _i ^(j) + W _j · x _{j-N + i + 1} will be performed. Since the carry is carried out by 1 in the 17th bit from the higher order, even if only the upper 16 bits are extracted, the rounding processing is equivalently performed. By such a rounding process, at least 4 steps per filter coefficient. Depending on the type of general-purpose digital signal processor, there are cases in which two steps are required for the number processing to the lower bit of the D register. In this case, if the rounding processing is performed, the operation in the equation (4) is performed. There are 5 steps for each filter coefficient.

[Problems to be Solved by the Invention]

Regarding the modification of the coefficient h _i ^{(j) in} the above-mentioned rounding processing, there is an increase of 1 to 2 steps with respect to the basic processing flow, or there are N coefficient h _i ^(j) (of the transversal filter). Since the number of taps is N), the total number increases by N or 2N steps. The signal repetition period is usually 125
Since it is μs, the processing time for one step is 10
When a high-speed general-purpose digital signal processor of 0 ns is used, the maximum processing calculation amount within a cycle is 1250 steps. For example, when N = 112, N-2N is 112-224. This value corresponds to 9 to 18% of the processable amount, and because of rounding processing, it cannot be processed by one processor, and it often occurs that multiple processors must be provided. This increases the cost of the echo canceller device.

Further, in the echo canceller device of the conventional example, there is a problem that stable operation cannot be maintained when a narrow band signal is input to the terminal RIN. The narrow band signal in this case indicates a single frequency sine wave signal, and if this narrow band signal is input to the terminal RIN and the operation of the echo canceller device is started at t = 0, it is 1 second or less. Within a short time, the echo component attenuates to a small value of -40 dB or less (about -30 dB in the standard) compared to the input signal level, or the error gradually increases, and after a few minutes, the echo component becomes- 20 dB
Grows to a degree.

Therefore, in the rounding processing, a control signal generating function is provided for executing the rounding processing without rounding, and the rounding is performed once every 20 to 40 cycles on average. In this case, the probability is once every 20 to 40 cycles, so that a random number is generated, and when it is a certain value or more, the truncation processing is performed, and at other times, the rounding processing is performed. For such processing, a considerable amount of calculation of about 20 steps is required.

An object of the present invention is to reduce the amount of calculation such as the above-mentioned rounding processing and stabilization processing for narrow band signals.

[Means for Solving the Problems]

The echo canceller device of the present invention is capable of stabilizing the operation and reducing the amount of calculation, and will be described with reference to FIG.

An echo path estimation impulse response sequence whose size is adaptively changed, and a pseudo echo generation unit 1 including a transversal filter that outputs a pseudo echo signal from a received signal sequence are provided, and an actual echo component is generated by the pseudo echo signal. In an echo canceller device that cancels the noise, a superimposing means 2 for superimposing a constant DC component on the input signal of the pseudo echo generating unit 1 having a transversal filter configuration, and a DC component for cutting off the DC component of the output signal of the pseudo echo generating unit 1. Blocking means 3
A constant setting means 4 for setting an addition constant and a multiplication constant based on the magnitude of the DC component of the output signal of the pseudo echo generating section 1, and the filter coefficient of the pseudo echo generating section 1 are divided into a plurality of groups. The processing means 5 is provided for sequentially performing addition processing of addition constants and multiplication processing of multiplication constants set by the constant setting means 4 for each group.

[Action]

By superimposing the DC component on the input signal of the pseudo echo generating section 1 by the superimposing means 2, a DC component proportional to the magnitude of the error of the filter coefficient generated by the truncation processing in the coefficient correction is generated. An addition constant and a multiplication constant are set in the constant setting means 4 in accordance with the magnitude of this DC component. Also, the probability of rounding processing in coefficient correction is 1/2, and on average it is sufficient to add 1/2 of the maximum truncation amount to all filter coefficients per cycle. Specifically, that is, by performing addition processing of addition constants and multiplication processing of multiplication constants for each group, it is possible to reduce the amount of calculation by rounding processing that has been performed on all filter coefficients in each cycle. For narrow band signals, the filter coefficient is multiplied by a multiplication constant set to a value slightly smaller than 1 to prevent the absolute value of the filter coefficient from increasing and maintain the echo attenuation amount to a large value. can do.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention. 11 is a pseudo echo generating section, 12 is a received signal storage memory, 13 is an echo path estimation impulse response storage memory, 14 is an adder, and 15 is a first coefficient. Correction unit, 16 is a second coefficient correction unit, 17 is a high-pass filter, 18 is an adder, 19 is a constant setting unit, 20 is a coefficient processing unit,
Reference numeral 21 is a DC component superimposing unit. Further, RIN is a reception input terminal to which the reception input signal x _j is added, ROUT is a reception output terminal for adding the reception output signal to a hybrid circuit (not shown), and SIN is an echo signal y _j from the hybrid circuit (not shown) and A transmission input terminal to which a transmission input signal is added, SOUT indicates a transmission output terminal that outputs a transmission output signal in which echo components are canceled, and will be hereinafter abbreviated as “terminal”.

Pseudo echo generator 11, received signal storage memory 12, echo path estimation impulse response storage memory 13, and adder 14
And the coefficient correction unit 15 are similar to the configuration of the echo canceller device of the conventional example, and the coefficient correction unit 15 basically performs the process of the equation (4), but performs the rounding process. The structure is not provided, and the function is simplified as compared with the coefficient correction unit 65 (see FIG. 7) in the conventional example. The second
The coefficient correction unit 16 of is composed of a high-pass filter 17, an adder 18, a constant setting unit 19, and a coefficient processing unit 20.
Corresponds to the DC cutoff means 3 in FIG. 1, the adder 18 and the constant setting section 19 correspond to the constant setting means 4, and the coefficient processing section
It corresponds to the processing means 5 including 20 and the coefficient correction unit 15. Further, the DC component superimposing section 21 corresponds to the superimposing means 2.

The constant setting unit 19 sets the addition constant a and the multiplication constant corresponding to the _{DC component} y _DC obtained by the adder 18, and sets the coefficient processing unit.
It will be sent to 20. The echo path estimation impulse response storage memory 13 stores filter coefficients h _{0 to} h _N−1 corresponding to the number of taps N of the pseudo echo generating unit 11.
Further, in the DC component superimposing section 21, the DC component is superimposed by adding a constant f to the input signal x _j , and stored as x _j ′ in the received signal storage memory.

In the present invention, when the error amount due to the coefficient truncation process is detected and the error amount exceeds a certain amount,
The error is canceled by adding a constant to the filter coefficient. Since the error component in this case is not always a fixed amount for each cycle, it is necessary to determine its magnitude, and the error component is detected as the DC component of the output signal of the pseudo echo generation component 11. Is.

Also, in a double talk state where both occur simultaneously during a call, or when only the subscribers on the terminals ROUT and SIN are occurring, a transmission input signal is added to the terminal SIN via a hybrid circuit, Since it is added to the adder 14 together with the echo signal y _j , the coefficient h _i ^(j) moves in the wrong direction when the processing of the equations (1), (2) and (3) is performed.
In order to prevent this, the correction of the coefficient is stopped by setting α = 1, that is, W _j = 0. In this case, the coefficient loaded from the memory can be understood as W _j = 0 in the equation (4). Since h _i ^(j) is stored as it is in the memory as the next coefficient h _i ^{(j + 1)} , no truncation error occurs.

Further, in the present invention, since the first coefficient correction unit 15 does not perform the rounding processing, when the coefficients are corrected, the filter coefficients h _i ^(j) are all on the number line due to the truncation error. Will move to the left. Therefore, assuming that the ideal filter coefficient is h _i ^(j) , the actual filter coefficient H _i ^(j) is H _i ^(j) = h _i ^(j) + d (5). It should be noted that d is generated because the coefficient correction unit 15 does not perform the rounding processing, and is a negative value. Since the difference between rounding and rounding is not uniform depending on each coefficient, the value of d should be different depending on each coefficient, but all coefficients are subjected to coefficient correction processing in each cycle and rounded off. If so, the probability that one that should have 1 added to the least significant bit is truncated is halved, and cumulatively all the coefficients may be set to a constant value d.

Further, the input signal x _j of the pseudo echo generation unit 11 is a voice signal,
Although the direct current component is zero, the direct current component may be superimposed in the process of transmitting the audio signal depending on the communication system. If such a DC component is included, the echo canceling does not sufficiently act, and therefore the input signal x _j , y _j is usually used.
On the other hand, the direct current component is blocked by passing a high-pass filter (not shown). Therefore, it can be considered that the input signal x _j applied to the terminal RIN does not include a DC component, and as described above, in the DC component superimposing unit 21 with respect to this input signal x _j . Add the constant f. This is equivalent to superimposing a DC component having a constant amplitude level f on the input signal x _j . Therefore, equation (2) is Becomes

Since the actual echo is input via a hybrid transformer, etc., it does not include the direct current component, and the sum of the impulse response coefficients becomes zero. Therefore, the third term on the right side of the above equation becomes zero. Become. The output signal of the pseudo echo generating section 11 is the sum of the first term, the second term, and the fourth term of the above equation, but it is
The direct current component y _DC = N · d · f disappears, and the first and second terms
Only terms.

Also, the signal applied to the adder 14 from the high-pass filter 17 has a value of d which is at most close to the least significant bit of the filter coefficient h _i in the steady state after pulling in, when compared with the first and second terms of the above equation. Since it is a value, the second term of the above equation is sufficiently smaller than the first term when viewed as the input of the adder 14, so that the second term can be ignored and only the first term, which is the original echo component, can be ignored. Can be considered.

On the other hand, since the output signal of the adder 18 takes the difference between the input and output signals of the high-pass filter 17, only the _{DC component} y _DC = N · d · f. The direct current component y _DC is proportional to d, which is a shift amount caused by the rounding down process of the coefficient h _i ^(j) . Also constant f
If is a negative value, the DC component y _DC is a positive value with opposite polarity. The output signal _j 'of the pseudo echo generation unit 11, when the pseudo echo signal _j which is added directly to the adder 14, the error signal e _j is, e _j = y _j - _j -y _DC, and the negative of the terminal SOUT DC component is output. Since the value of | d | rapidly increases due to the truncation processing, the error signal e _j reaches the maximum negative level within a few seconds unless the processing in the second coefficient correction unit 16 is performed. Therefore, in the present invention, the output signal _j'of the pseudo echo generator 11 is added to the high-pass filter 17 having a cutoff frequency of several tens Hz to cut off the DC component. The direct current component y _DC can be obtained by the adder 18 as the difference between the input and output signals of the high pass filter 17. This filtering process is executed every cycle.

FIG. 3 is a flow chart of an embodiment of the present invention, in which the output signal _{j'of the} pseudo echo generating section 11 is the second coefficient correcting section 1
It is input to 6 and is input to the high-pass filter 17 to become the pseudo echo signal _j in which the DC component is cut off. Then, y _DC = _j 'by the adder 18 - carries out an operation of _j, to detect the DC component.

Next, it is determined whether or not the current cycle is the first cycle of the large cycles.
That is, the time corresponding to the M cycle is set as a large cycle, and it is determined whether or not it is the first cycle of the large cycle and whether the content J of the counter for counting the cycle is M-1. The function of this counter is provided in the second coefficient correction unit 16, but can be easily realized when configured using a general-purpose digital signal processor. Then, in the first period, the threshold value y _TM , which is a preset zero or a constant close to zero, is compared with the direct current component y _DC .

If y _DC <y _{TH in} the step determination, the constant setting unit 19 sets the addition constant a and the multiplication constant b of a = 0 and b = 1. When y _DC > y _TH , a = k ₁ , b = 1
Set a constant of −k ₂ (k ₁ and k ₂ are positive minute numbers). The above constant setting shows the case where f <0, and f> 0
In case of, the judgment in the step is reversed. In addition, after the step or, the count content J is set to 0 in the step, and the process proceeds to the next step.

In the second to Mth cycles, the constants a and b are not updated, and the process proceeds to step. In this step, the coefficient processing unit 20 performs addition of the constant a and multiplication of the constant b.
Will be done in. That is, Will be processed. Note that i = JL, JL + 1, ...
(J + 1) L-1 and N = ML. That is, the processing is sequentially performed for each of the L groups. Then, the process proceeds to step and the count content J is incremented by +1. The constant a in the expression (7) calculated in the above step
Is added by the processing in the first coefficient correction unit 15, that is,
This is to correct that the coefficient h _i ^(j) has an error in the negative direction due to omission of the rounding processing in the processing of the equation (3).

Further, the multiplication of the constant b, which is slightly smaller than 1, maintains a large echo attenuation amount for a long time even when a narrowband signal is input,
This is to ensure stable operation. According to international standards,
When a 1300 Hz sine wave signal is input to the terminal RIN, the attenuation is 10 dB after 3 minutes from the start of the echo canceller operation.
It is okay to be around. This is because in the case of a sine wave signal input, there are many possible values for the coefficients of the transversal filter, and since the solutions are continuous solutions, certain coefficients vibrate greatly and are positive. To a large value, another coefficient vibrates greatly and tends toward a large negative value, which is a cause of a so-called divergence phenomenon. On the other hand, in the present invention, by multiplying by the constant b smaller than 1, it is possible to prevent the absolute value of the coefficient from increasing, so that the stability can be greatly improved.

The processing of the above formula (7) is performed for N / M = L filter coefficients out of N filter coefficients in total for each cycle, and the coefficient for all coefficients is M cycles, which is a large cycle. It suffices to complete the correction. Therefore, as shown in step, the content J of the counter determines whether the current cycle is the cycle of the large cycle M. For example, N = 112
At this time, M = 28 is set, and 14 is added to each of L = 112/28 = 4 filter coefficients out of 112 filter coefficients in one cycle. Here, the singular decimal number of the 16-bit fixed-point number handled by the general-purpose digital signal processor is 1. Further, the reason for setting a = 14 is that since the processing of the formula (7) for a certain filter coefficient h _i is performed only once in 28 cycles, it is equal to the average value of the errors generated in the coefficient correction unit 15 for 28 cycles. This is because it is optimal to add

As described above, in the present invention, regarding each filter coefficient, for example, the error amount due to the truncation processing for 28 cycles is collectively corrected at one time. Further, not all coefficients are corrected to have the same cycle, but correction is sequentially performed for every group, for example, for four groups. Due to such processing for a part, the filter coefficient of the transversal filter may be incomplete, that is, the waveform of the pseudo echo signal may be different from the waveform of the true echo signal.
Since the order of a <10 ^-3 and 1-b <10 ^{-3 at} the real number level, the deterioration of the echo attenuation amount hardly occurs. For example, in a normal echo canceller device, an echo attenuation amount of about 30 dB is required, but an echo attenuation amount of about 40 dB is obtained as the actual value in the conventional example, and in the present invention, an echo attenuation amount of about 39 dB is obtained. Therefore, the amount of deterioration is slight, and the amount of attenuation is such that a sufficient margin can be obtained even when compared with the required value.

The process of DC component superimposed to the input signal x _j is the input signal x _j
It suffices to add the addition process of the constant f to the end of the high-pass filter process with respect to, and it will be sufficient in two steps. In practice, it is sufficient to subtract the minimum unit of 1.

Further, although the case where the high-pass filter 17 and the adder 18 are used for the DC component detection is shown, in this case, since the primary high-pass filter processing and the subtraction processing may be performed, for example, the following expression is used. Will be things. _{j = 0.975 (j '- j} -1') +0.95 j-1 ... (8) y DC = j '- j ... (9) that is, obtain a DC component y _DC by the two addition and subtraction 3 multiplications be able to. This calculation requires 9 steps. Further, as described above, the determination is not performed every cycle, but is performed only once in M cycles, so there are processes such as stepping or resetting the counter, and 12 steps including the setting of constants a and b. Become. As for the modification of the filter coefficient, the addition of the constant a and the multiplication of the constant b can be processed at the same time.
The number of steps is enough, and even if the overhead of 6 steps is included, 18 steps are possible with 4 coefficients (1 group). Therefore, the total calculation amount is 41 steps.

In the echo canceller device of the conventional example, when N = 112, it takes 112 to 224 steps for coefficient correction for rounding, and 20 steps for securing stability for narrow band signals. In comparison, in the present invention,
Since 41 steps are required, the amount of calculation can be significantly reduced. Further, when the number of taps is increased such that N = 256, in the present invention, it is only necessary to increase the number of processes of the equation (7), so that the difference is further increased.

Further, with respect to an audio signal taken in at a cycle of 125 μs, the echo canceller device according to the present invention and the echo canceller device according to the conventional example are configured by using a digital signal processor of 100 ns per process. Comparing the delay time of the component, that is, how many taps can be processed, according to the present invention, 112 taps, that is, echoes of 14 ms (= 112 × 0.125) can be dealt with. In this case, of the 1250 steps, 112 steps are used for the processing of the transversal filter that constitutes the pseudo echo generator, 336 steps are used for the coefficient correction processing, and other processing such as power calculation, double talk determination, and signal input / output conversion is performed. 78
It became 0 steps. On the other hand, according to the conventional example, it is possible to respond to an echo of 98 or 81 taps, that is, up to about 12 ms or 10 ms. In this case, of the 1250 steps, the steps corresponding to the above-mentioned other processes are 760 steps, and therefore, 1250−760 = 490 steps are divided by 5 to 6 which is the number of steps required for processing per tap. This is the same as the above-mentioned 98 or 81 taps.

Therefore, according to the present invention, it is possible to perform a stable operation even for a narrow band signal, and to cancel an echo having a delay that is 20 to 40% larger than that of the echo canceller device of the conventional example. Can be possible.

FIG. 4 is a flowchart of another embodiment of the present invention,
The output signal _j'of the pseudo echo generator 11 is input, the DC component is detected by the steps of the above-mentioned embodiment, etc., and then it is determined whether the content J of the counter is M-1.
That is, it is determined whether or not it is the first cycle of the large cycle.
In the case of the first cycle, the DC component y _DC is multiplied by αk ₁ to obtain a constant a, the absolute value of αk ₂ is subtracted from 1 to obtain a constant b, and the content J of the counter is set to 0. . 1 of the great cycle
If it is not the second, the constants a and b are not modified and the process proceeds to the step.

Step, is the step in the above-mentioned embodiment,
Is the same as. In this embodiment, by properly selecting the positive constant k ₁ , when the DC component y _DC due to the truncation increases in the negative direction, a increases in the negative direction and the coefficient
h _i is corrected in the positive direction and controlled so that the _{DC component} y _DC approaches zero. When the correction is excessive and the DC component y _DC increases in the positive direction, a also becomes a positive value, and the coefficient h _i is corrected in the negative direction, and the DC component y _DC is controlled so as to approach zero.
Therefore, it is stabilized in the state of the direct current component y _{DC which} is extremely small in absolute value.

Further, by setting the constant b according to b = 1- | k ₂ α | and multiplying this by the coefficient, the coefficient h _i is always corrected to a small value as an absolute value, and stable even for narrowband signals. It will work. Also, the constants a and b are used as a function of α. In the double-talk state, when the coefficient is not corrected, α becomes 0, so that a = 0 and b = 1 are set. This is to prevent the coefficient correction from being performed in the second coefficient correction unit 16 either.

FIG. 5 is a flow chart of still another embodiment of the present invention, and the steps, ... Are the same as the steps ,. In this embodiment, it is determined whether α is 0 in step, and when α = 0, a
= 0, b = 1, and when α ≠ 0, a = k ₁ y _DC , b = 1-k ₂ . Then, the count content J is set to 0 and the step calculation is performed.

The DC component y _DC is detected by the output signal of the pseudo echo generator 11.
It is also possible to add _j ′ to the reduction filter. In this case, the pseudo echo signal added to the adder 14 is obtained by taking the difference between the input and output signals of the low pass filter.
You can ask for _j .

〔The invention's effect〕

As described above, according to the present invention, in the correction of the filter coefficient of the transversal filter that constitutes the pseudo echo generating unit 1, the rounding processing, the constant multiplication processing, and the like are performed on all the filter coefficients for each cycle. You don't have to
When the digital signal processor with the same processing capacity as the conventional example is used, it is possible to cope with echoes with a large delay and when a narrow band signal is input. Since the echo attenuation amount can be maintained large, there is an advantage that the characteristics of the echo canceller device can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIGS. 3, 4 and 5 are flow charts of different embodiments of the present invention, and FIG. FIG. 7 is an explanatory diagram of an echo path, FIG. 7 is a block diagram of a main part of a conventional example, and FIG.
9 and 9 are flowcharts of a conventional example. 1 is a pseudo echo generating unit, 2 is a superimposing unit, 3 is a DC blocking unit, 4 is a constant setting unit, 5 is a processing unit, 11 is a pseudo echo generating unit, 12 is a received signal storage memory, 13 is an echo path estimation impulse response. Storage memory, 14 is an adder, 15 is a first coefficient correction unit, 16 is a second coefficient correction unit, 17 is a high-pass filter,
18 is an adder, 19 is a constant setting unit, 20 is a coefficient processing unit, and 21 is a DC component superimposing unit.

Claims (1)

[Claims] 1. A pseudo echo generating section (1) for inputting a received signal sequence and outputting a pseudo echo signal, wherein an echo path estimation impulse response sequence whose size is adaptively changed is used as a filter coefficient. In an echo canceller device for canceling an actual echo component by an echo signal, a superimposing means (2) for superimposing a constant direct current component on an input signal from a reception input terminal to the pseudo echo generating section (1); DC cut-off means (3) for cutting off the DC component of the output signal of the echo generation unit (1), and an addition constant for the filter coefficient based on the magnitude of the DC component of the output signal of the pseudo echo generation unit (1). And constant setting means (4) for setting a multiplication constant, and the filter coefficient of the pseudo echo generating section (1) is divided into a plurality of groups, and the constant setting means (4) for each group. An echo canceller device comprising: a processing means (5) for sequentially performing addition processing of addition constants and multiplication processing of multiplication constants set in 4) in one sample time.