JP2840041B2 - Electrostatic chuck - Google Patents

Electrostatic chuck

Info

Publication number
JP2840041B2
JP2840041B2 JP3993895A JP3993895A JP2840041B2 JP 2840041 B2 JP2840041 B2 JP 2840041B2 JP 3993895 A JP3993895 A JP 3993895A JP 3993895 A JP3993895 A JP 3993895A JP 2840041 B2 JP2840041 B2 JP 2840041B2
Authority
JP
Japan
Prior art keywords
pedestal
electrode layer
layer
laminate
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3993895A
Other languages
Japanese (ja)
Other versions
JPH0846019A (en
Inventor
シャースティンスキー セミョン
シャモイリアン シャモイル
ビラング マヌーチャー
マク アルフレッド
ダブリュー. タム サイモン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of JPH0846019A publication Critical patent/JPH0846019A/en
Application granted granted Critical
Publication of JP2840041B2 publication Critical patent/JP2840041B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02NELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR
    • H02N13/00Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4582Rigid and flat substrates, e.g. plates or discs
    • C23C16/4583Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
    • C23C16/4586Elements in the interior of the support, e.g. electrodes, heating or cooling devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67098Apparatus for thermal treatment
    • H01L21/67109Apparatus for thermal treatment mainly by convection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H01L21/6833Details of electrostatic chucks
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T279/00Chucks or sockets
    • Y10T279/23Chucks or sockets with magnetic or electrostatic means
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Jigs For Machine Tools (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、一般的には、処理室に
おいて半導体ウェハを固定するために用いられる静電チ
ャックに関し、更に詳細には、ウェハの冷却を高め、こ
の種類のチャックの有効寿命を長くする顕著な改良に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to electrostatic chucks used to secure semiconductor wafers in a processing chamber and, more particularly, to increasing the cooling of a wafer and the effectiveness of such chucks. It is a significant improvement that extends the life.

【0002】[0002]

【従来の技術】静電チャックは、半導体処理室において
チャンバペデスタル上に個々の半導体基板又はウェハを
保持するために用いられる。静電チャックは、典型的に
は、誘電層及び電極を含む。半導体ウェハを誘電層と接
触させて配置し、直流(dc)電圧を電極に印加すると
静電吸引力を発生してウェハをチャックに引きつける。
この種類のチャックは、ウェハを所定の位置に保持する
差圧が不十分であったりウェハの機械的固定が好ましく
ない真空処理環境において特に有用である。静電チャッ
クが広く用いられている1つの処理環境はプラズマエッ
チングプロセスである。
2. Description of the Related Art Electrostatic chucks are used in semiconductor processing chambers to hold individual semiconductor substrates or wafers on a chamber pedestal. Electrostatic chucks typically include a dielectric layer and electrodes. When a semiconductor wafer is placed in contact with a dielectric layer and a direct current (dc) voltage is applied to the electrodes, an electrostatic attraction is generated to attract the wafer to the chuck.
This type of chuck is particularly useful in a vacuum processing environment where the differential pressure holding the wafer in place is insufficient or mechanical fixing of the wafer is undesirable. One processing environment in which electrostatic chucks are widely used is a plasma etching process.

【0003】静電チャックは単一の誘電層と電極だけを
用いて形成されるが、より典型的な構造としては上下誘
電層又はポリイミドのような有機材料間に挟まれた、好
ましくは薄い銅層である電極コアを有する薄い積層部材
を含む。これらの層を一枚の積層シートに組立てかつそ
の積層シートをチャンバペデスタルに装着するために、
ポリイミド接着剤を用いてもよい。
[0003] Electrostatic chucks are formed using only a single dielectric layer and electrodes, but a more typical structure is a thin copper layer, preferably sandwiched between upper and lower dielectric layers or an organic material such as polyimide. It includes a thin laminated member having an electrode core that is a layer. To assemble these layers into one laminated sheet and attach the laminated sheet to the chamber pedestal,
A polyimide adhesive may be used.

【0004】上下ポリイミド層は電極の円周辺縁で融合
して(merge) 、通常銅層を損傷するプラズマを含む銅電
極の処理室への露出を防止する。操作中、銅電極は電圧
源に接続され、陽極として機能する。静電チャックの操
作原理は周知であり、本発明に重要なものではない。ペ
デスタル上に形成された電界によりペデスタルと積層板
に接触して配置された半導体ウェハとの間に相互引力が
生じることを留意することだけで十分である。
The upper and lower polyimide layers merge at the perimeter edge of the electrode to prevent exposure of the copper electrode to the processing chamber, which typically contains a plasma that damages the copper layer. In operation, the copper electrode is connected to a voltage source and functions as an anode. The operating principle of the electrostatic chuck is well known and is not important to the present invention. It is sufficient to note that the electric field formed on the pedestal creates a mutual attractive force between the pedestal and the semiconductor wafer placed in contact with the laminate.

【0005】[0005]

【発明が解決しようとする課題】ウェハが受ける多くの
処理により熱が発生し、熱損傷を防止するためにウェハ
を許容しうる処理温度に冷却する手段を講じなければな
らない。従来技術のほとんどの静電チャックにおいて
は、ペデスタルの中央の開口を通ってウェハの下にヘリ
ウムガスが導入され、次いでペデスタル上の積層板の溝
型を通って分配される。通常は形が円形であるウェハ面
を横切って一様に冷却ガスを分配する努力として種々の
溝型が用いられてきた。この冷却法に伴う欠点は、ウェ
ハの縁付近で一様な冷却を妨げることである。溝がウェ
ハの縁まで続く場合には、特に縁付近に、ガス漏れの割
合が高くかつ冷却作用の低下になる。ほとんどの設計で
は、縁に達する前に溝が終わっている。ある設計では、
放射状の溝が縁付近で第2の溝に隣接し、その第2の溝
は終わりとなる前の短い距離だけ周辺に広がるか又は終
わりとなる前に種々の方向に伸びている分枝溝の形を取
る。しかしながら、これらの設計ではすべて、ウェハの
その周辺縁付近でなお好ましくない過熱がある。
Many of the processes that wafers undergo generate heat, and measures must be taken to cool the wafer to an acceptable processing temperature to prevent thermal damage. In most prior art electrostatic chucks, helium gas is introduced beneath the wafer through a central opening in the pedestal and then distributed through the channel of the laminate on the pedestal. Various groove forms have been used in an effort to distribute the cooling gas uniformly across the wafer surface, which is usually circular. A disadvantage with this cooling method is that it prevents uniform cooling near the edge of the wafer. If the groove extends to the edge of the wafer, especially near the edge, the rate of gas leakage is high and the cooling effect is reduced. In most designs, the groove ends before reaching the edge. In one design,
A radial groove is adjacent to the second groove near the edge, the second groove extending peripherally a short distance before the end, or a branch groove extending in various directions before the end. Take shape. However, all of these designs still have undesirable overheating near its peripheral edge of the wafer.

【0006】従来技術の静電チャックのもう1つの欠点
は、ポリイミドと銅の積層板がチャックペデスタル上に
形成する方法から生じるものである。ポリイミドの第1
層がペデスタルの上に配置され、次いで銅電極がポリイ
ミドの上に配置される。ポリイミド層が銅の外縁の回り
で重なり封着する(provide a seal)ので、銅層がポリイ
ミドの縁まで伸びることができないことは当然のことで
ある。第2ポリイミド層が銅層の上に配置されると、積
層板の全体の厚さは銅層を含む全体の積層板の厚さより
ポリイミドの縁(ポリイミド2層の厚さ)の回りで小さ
くなる。従って、積層板は銅層の外径の外に環状の段差
を有する。この環状の段差は静電チャックの性能につい
て2つの有害な影響がある。第一に、この段差のために
銅層の外径の向こうでウェハと接触しているチャックは
非常に小さな範囲にすぎない。結果として、ウェハの縁
でヘリウム漏れの確率が高くかつウェハの縁領域の望ま
しくない過熱がある。積層構造の環状段差の第2の影響
は、銅層の外縁がポリイミド上層とほぼ同じ厚さを有す
る非常に薄いポリイミド層によってのみ有害チャンバ環
境から絶縁されることである。この層がチャンバ内の処
理プラズマによって腐食されると、チャックを取り替え
なければならない。ポリイミドと他の有機材料は、多く
の処理ガス及びプラズマに対して比較的許容量が低い。
従って、電極の回りに良好な絶縁層を設置することは重
要な問題である。
[0006] Another disadvantage of the prior art electrostatic chucks stems from the method by which polyimide and copper laminates are formed on the chuck pedestal. The first of polyimide
A layer is placed on the pedestal, then a copper electrode is placed on the polyimide. Naturally, the copper layer cannot extend to the polyimide edge because the polyimide layer provides a seal around the outer edge of the copper. When the second polyimide layer is disposed over the copper layer, the overall thickness of the laminate is less around the polyimide edge (thickness of the polyimide two layers) than the overall laminate thickness including the copper layer. . Therefore, the laminate has an annular step outside the outer diameter of the copper layer. This annular step has two detrimental effects on the performance of the electrostatic chuck. First, only a very small area of the chuck is in contact with the wafer beyond the outer diameter of the copper layer due to this step. As a result, there is a high probability of helium leakage at the edge of the wafer and there is undesired overheating of the edge area of the wafer. A second effect of the annular steps of the laminate structure is that the outer edge of the copper layer is insulated from the hazardous chamber environment only by a very thin polyimide layer having about the same thickness as the polyimide top layer. If this layer is eroded by the processing plasma in the chamber, the chuck must be replaced. Polyimides and other organic materials have relatively low tolerance for many process gases and plasmas.
Therefore, placing a good insulating layer around the electrodes is an important issue.

【0007】上記のことから、静電チャックの改良が求
められていることは理解されるであろう。特に必要なこ
とは、ウェハの辺縁付近で冷却を高めかつチャックの有
効寿命を長くする改良されたチャック構造である。本発
明は、下記説明から明らかなようにこの要求を満足させ
るものである。
[0007] From the foregoing, it will be appreciated that there is a need for an improved electrostatic chuck. What is particularly needed is an improved chuck structure that increases cooling near the edge of the wafer and increases the useful life of the chuck. The present invention satisfies this need, as will be apparent from the following description.

【0008】[0008]

【課題を解決するための手段】本発明は、チャックペデ
スタル面を横切る複数の点でチャックを介して冷却ガス
を分配することによりウェハとチャックとの間に、特に
チャックの縁部分に著しく改善された熱移動を与える静
電チャックに関する。更に、本発明のチャックは、チャ
ックペデスタルに取り付けられた積層板の縁までウェハ
に対して平らな面を示し、そのことにより更にウェハの
縁部分の冷却を改善しかつチャックの有効寿命を長くす
る。
SUMMARY OF THE INVENTION The present invention provides a significant improvement between a wafer and a chuck, particularly at the edge of the chuck, by distributing cooling gas through the chuck at multiple points across the chuck pedestal surface. The present invention relates to an electrostatic chuck that provides heat transfer. Further, the chuck of the present invention exhibits a flat surface to the wafer to the edge of the laminate mounted on the chuck pedestal, thereby further improving the cooling of the wafer edge and extending the useful life of the chuck. .

【0009】簡単にしかも一般的に言えば、本発明の静
電チャックは、加工部材を支持するためのペデスタル;
ペデスタルに装着された、銅電極に電圧を印加すると加
工部材が積層板に固定される絶縁銅電極を含む積層板;
及び加工部材を下から冷却するガスを送るためにペデス
タルと積層板を通って上に伸びている複数の穴であっ
て、該穴の多くが加工部材の外周付近に配置されている
もの;を含む。ペデスタルは、また、ペデスタルの下に
形成されかつ全ての穴を横切って広がっている冷却ガス
リザーバ及びリザーバへの冷却ガス供給口を含む。穴
は、上端で小さな直径へと先細になることが好ましい。
[0009] Briefly and generally speaking, the electrostatic chuck of the present invention comprises a pedestal for supporting a workpiece.
A laminated plate including an insulated copper electrode mounted on the pedestal and having a processed member fixed to the laminated plate when a voltage is applied to the copper electrode;
And a plurality of holes extending upwardly through the pedestal and the laminate for delivering gas to cool the workpiece from below, wherein many of the holes are located near the outer periphery of the workpiece. Including. The pedestal also includes a cooling gas reservoir formed beneath the pedestal and extending across all holes and a cooling gas supply to the reservoir. The hole preferably tapers to a small diameter at the upper end.

【0010】更に詳細には、積層板は、第1絶縁層;第
1絶縁層上に形成された銅電極層;及び銅電極上に形成
されかつ銅電極層の縁の回りで第1絶縁層と融合して静
電チャックが取り付けられる処理環境から銅を絶縁する
第2絶縁層を含む。本発明の1態様によれば、第2絶縁
層は積層板の全体の広さにわたって実質的に平らな上面
を示す。そのことにより、銅電極の外縁の向こうで加工
部材と良好な接触が維持される。更に、銅電極が処理プ
ラズマの影響から広く隔てられて静電チャックの有効寿
命を長くする。
[0010] More specifically, the laminate comprises a first insulating layer; a copper electrode layer formed on the first insulating layer; and a first insulating layer formed on the copper electrode and around an edge of the copper electrode layer. And a second insulating layer that insulates the copper from the processing environment in which the electrostatic chuck is mounted. According to one aspect of the invention, the second insulating layer exhibits a substantially flat upper surface over the entire width of the laminate. Thereby, good contact with the workpiece is maintained beyond the outer edge of the copper electrode. Further, the copper electrodes are widely separated from the effects of the processing plasma, extending the useful life of the electrostatic chuck.

【0011】この平らな上面を達成するために、ペデス
タルはその上面に形成された溝を有する。従って、第1
絶縁層はペデスタル上に配置されると溝と適合する。銅
電極が実質的に溝を塞ぎ、実質的に平らで第2絶縁層で
覆われる複合上面を示す。
To achieve this flat top surface, the pedestal has a groove formed in its top surface. Therefore, the first
The insulating layer mates with the groove when placed on the pedestal. FIG. 4 shows a composite top surface in which copper electrodes substantially fill the trenches and are substantially flat and covered with a second insulating layer. FIG.

【0012】本発明の静電チャックは、また、半導体基
板を支持するペデスタル;及びペデスタルに装着された
絶縁銅電極を含む積層板を含み、銅電極に電圧を印加す
ると該基板が積層板に静電的に固定されるように更に特
定して定義される。積層板は、第1誘電層;第1誘電層
上に形成された銅電極層;及び銅電極上に形成されかつ
銅電極層の縁の回りで第1誘電層と融合して静電チャッ
クが取り付けられる処理環境から銅を絶縁する第2誘電
層を含む。第2誘電層は積層板の全体の広さにわたって
実質的に平らな上面を示し、そのことにより、銅電極の
外縁の向こうで基板と良好な接触が維持される。更に、
銅電極が処理プラズマの影響から広く隔てられて静電チ
ャックの有効寿命を長くする。
The electrostatic chuck of the present invention also includes a pedestal for supporting a semiconductor substrate; and a laminated plate including an insulated copper electrode mounted on the pedestal. When a voltage is applied to the copper electrode, the substrate is placed on the laminated plate. It is more specifically defined to be electrically fixed. The laminate comprises a first dielectric layer; a copper electrode layer formed on the first dielectric layer; and an electrostatic chuck formed on the copper electrode and fused with the first dielectric layer around an edge of the copper electrode layer. A second dielectric layer insulates the copper from the attached processing environment. The second dielectric layer exhibits a substantially flat top surface over the entire width of the laminate, thereby maintaining good contact with the substrate beyond the outer edge of the copper electrode. Furthermore,
Copper electrodes are widely separated from the effects of the processing plasma to extend the useful life of the electrostatic chuck.

【0013】新規な方法に関して、本発明は、ペデスタ
ルの上部に電極の厚さと等しい深さを有する浅い溝を形
成し;ペデスタルを横切って第1誘電層を配置し;第1
誘電層の上に電極層を配置し、そのことにより電極層が
浅い溝と一致し;第1誘電層と電極層を横切って第2誘
電層を配置して比較的平らな面を形成する工程を包含す
る。次いで、電極層を比較的長い絶縁路によって処理環
境を効果的に遮断し、平らな面が電極の外縁の外の領域
で基板と良好に接触する。
With respect to the novel method, the present invention forms a shallow groove having a depth equal to the thickness of the electrode at the top of the pedestal; disposing a first dielectric layer across the pedestal;
Disposing an electrode layer over the dielectric layer so that the electrode layer coincides with a shallow groove; disposing a second dielectric layer across the first dielectric layer and the electrode layer to form a relatively flat surface Is included. The electrode layer is then effectively shielded from the processing environment by relatively long insulating paths, so that the flat surface makes good contact with the substrate in areas outside the outer edges of the electrodes.

【0014】上記のことから、本発明が静電チャックの
分野で顕著な進展を示すことは理解されるであろう。特
に、本発明は、縁部分の過熱が実際に取り除かれるとと
もに温度勾配が劇的に低下するチャックを提供するもの
である。更に、チャックの積層部材の構造がその外部領
域の回りでウェハとの接触が良好になりかつチャックの
有効寿命が長くなる。
From the foregoing, it will be appreciated that the present invention represents a significant advance in the field of electrostatic chucks. In particular, the present invention provides a chuck in which the overheating of the edge is actually removed and the temperature gradient is dramatically reduced. Furthermore, the structure of the stack of members of the chuck provides good contact with the wafer around its outer area and prolongs the useful life of the chuck.

【0015】本発明の他の態様及び利点は、図面と共に
用いられた下記の詳細な説明から明らかになるであろ
う。
[0015] Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the drawings.

【0016】[0016]

【実施例】説明のための図面に示されているように、本
発明は静電チャックの改良に関する。図1及び図2に示
されているように、典型的な静電チャックは符号10で
示されるペデスタルを含み、この上に(記載されるべ
き)多層の積層板12が取り付けられる。ペデスタル1
0内の中央開口13は積層板12を通って上に伸び、中
央開口から積層板12を横切って放射状に広がる複数の
溝14と通じている。ペデスタル10は、ねじ16でペ
デスタル台15に固定されているように示されている。
環状の絶縁継ぎ輪(insulating collar) 17はペデスタ
ル上に取り付けられる。ペデスタル10の上部と積層板
12は、積層板の上に配置される半導体ウェハ18の輪
郭と一致するように通常円形である。図4に最もよく示
されているように、積層板12はポリイミド下層20、
銅電極層22及びポリイミド上層24を含む。ポリイミ
ド上層24は、銅層22の縁の回りで下層20と、共に
積層板12の周辺でかつ1つが図4に示されている溝1
4の各々に沿って融合及び封着する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in the accompanying drawings, the present invention relates to an improvement in an electrostatic chuck. As shown in FIGS. 1 and 2, a typical electrostatic chuck includes a pedestal indicated by the numeral 10 on which a multilayer laminate 12 (to be described) is mounted. Pedestal 1
A central opening 13 in 0 extends upwardly through the laminate 12 and communicates with a plurality of grooves 14 extending radially across the laminate 12 from the central opening. The pedestal 10 is shown fixed to the pedestal base 15 with screws 16.
An annular insulating collar 17 is mounted on the pedestal. The top of the pedestal 10 and the laminate 12 are usually circular so as to match the contour of the semiconductor wafer 18 located on the laminate. As best shown in FIG. 4, the laminate 12 comprises a polyimide underlayer 20,
It includes a copper electrode layer 22 and a polyimide upper layer 24. The polyimide upper layer 24 and the lower layer 20 around the edge of the copper layer 22 and the groove 1 shown in FIG.
4. Fuse and seal along each of the four.

【0017】図3(a)及び(b)は、過去に用いられ
ていた別の溝構造を示すものである。図3(a)の構造
においては、放射状の溝14の各々は、積層板12の回
りにその周辺付近まで伸びている弧状あるいは部分環状
溝14' と併合する。図3(b)の構造においては、放
射状溝14の各々は追加の溝分枝14”に隣接し、異な
った方向に積層板の周辺に向かって伸びている。これら
の及び他の構造は、すべて過度の冷却ガスの漏れが生じ
るような縁付近に溝を配置せずにウェハ18の縁付近に
十分な冷却ガスを供給する試みである。これらの構造の
すべてが共通の欠点:ウェハ縁領域の過熱を受ける。す
べての場合において、溝領域には熱移動及び静電固定圧
がほとんどなくウェハ縁での温度勾配が大きい。
FIGS. 3A and 3B show another groove structure used in the past. In the structure of FIG. 3 (a), each of the radial grooves 14 merges with an arcuate or partially annular groove 14 'extending around the laminate 12 to the vicinity of its periphery. In the structure of FIG. 3 (b), each of the radial grooves 14 is adjacent to an additional groove branch 14 "and extends in different directions towards the periphery of the laminate. These and other structures include: All attempts to provide sufficient cooling gas near the edge of the wafer 18 without placing grooves near the edge where excessive cooling gas leakage occurs.All of these structures have a common drawback: wafer edge area. In all cases, there is little heat transfer and static pressure in the groove area and there is a large temperature gradient at the wafer edge.

【0018】従来技術の静電チャックのもう1つの顕著
な欠点は、積層板12とウェハ18の縁領域を詳しく描
いている図7に示されている。積層板12は、まずペデ
スタル10の上にポリイミド下層20を配置し、次にポ
リイミド下層の上に銅電極層22を配置し、最後に最初
の2層20及び22の上にポリイミド上層24を形成す
ることにより作られる。必然的に、この構造は、2つの
ポリイミド層の厚さが2つのポリイミド層と銅層の合計
の厚さより小さいのでポリイミド上層24とウェハ18
との間に環状の隙間が残る。この積層構造は、2つの有
害な影響を有する。第1に、ウェハ18が隙間30の領
域では積層板12で支持されないので、銅層22の外径
の向こうでウェハ対積層板の接触は非常に小さな範囲の
みである。銅層22の外縁の向こうで発生された静電チ
ャック力がない。従って、20トールまでの数トール圧
力で供給された冷却ヘリウムガスはこの小さな範囲を越
えて処理チャンバ内に漏れる。この冷却ガスの漏れによ
り、ガス圧が低下すると共にウェハ縁付近の温度が高く
なる。銅電極22のサイズは、ペデスタル10のサイズ
及びポリイミド層20と24の最少限の重なり(約1.5
mm) に対する要求によって制限される。
Another notable disadvantage of the prior art electrostatic chuck is shown in FIG. 7, which details the edge area of the laminate 12 and wafer 18. Laminate 12 first places polyimide lower layer 20 on pedestal 10, then places copper electrode layer 22 on lower polyimide layer, and finally forms polyimide upper layer 24 on first two layers 20 and 22. It is made by doing. Inevitably, this structure requires that the polyimide top layer 24 and the wafer 18 be formed because the thickness of the two polyimide layers is less than the total thickness of the two polyimide layers and the copper layer.
And an annular gap remains. This laminated structure has two detrimental effects. First, since the wafer 18 is not supported by the laminate 12 in the region of the gap 30, there is only a very small range of wafer-to-laminate contact beyond the outer diameter of the copper layer 22. There is no electrostatic chucking force generated beyond the outer edge of copper layer 22. Thus, cooled helium gas supplied at a few Torr pressure up to 20 Torr leaks into the processing chamber beyond this small range. Due to the leakage of the cooling gas, the gas pressure decreases and the temperature near the wafer edge increases. The size of the copper electrode 22 is the size of the pedestal 10 and the minimum overlap of the polyimide layers 20 and 24 (about 1.5
mm).

【0019】環状の隙間30の第2の有害な影響は、処
理プラズマが隙間に存在するので、積層板によって示さ
れた銅の最少限の絶縁が銅層22の外縁と環状の隙間3
0との間の距離31である。既知のチャックでは、この
距離はポリイミド層の1枚の厚さに近く、約0.025〜
0.050mmである。この小さな絶縁の厚さによりチャッ
クの有効寿命が比較的短くなる。
A second detrimental effect of the annular gap 30 is that the minimal insulation of the copper exhibited by the laminate is limited to the outer edge of the copper layer 22 and the annular gap 3 because the processing plasma is present in the gap.
It is a distance 31 between 0. In known chucks, this distance is close to the thickness of one of the polyimide layers, about 0.025-
It is 0.050 mm. This small insulation thickness results in a relatively short effective service life of the chuck.

【0020】本発明の1つの重要な態様によれば、図8
に示されているように、積層板12は銅層22の外径か
ら十分に伸びている平らな上面を示すようにして形成さ
れる。特に、銅層22’はポリイミド層20’に埋め込
まれ、これらの2層は平らな面を示しその上にポリイミ
ド上層24’が形成される。適切な量で銅層22’を埋
め込む1つの方法は、約0.1〜0.2mmだけ銅電極22’
の直径より大きいように選ばれた直径の端ぐりを機械加
工することにより、まずペデスタル10の上部面に環状
の溝を形成することである。溝の深さは、銅電極22’
の厚さと同じ、即ち、約0.040mmである。次いで、ポ
リイミド下層がペデスタル10の溝を塞ぎ、ポリイミド
下層の上面に対応する溝を残し、その中に銅層22’が
配置される。
According to one important aspect of the present invention, FIG.
As shown, the laminate 12 is formed to exhibit a flat top surface that extends well from the outer diameter of the copper layer 22. In particular, the copper layer 22 'is embedded in the polyimide layer 20', these two layers exhibiting a flat surface on which the polyimide upper layer 24 'is formed. One method of embedding the copper layer 22 'in an appropriate amount is to use the copper electrode 22' by about 0.1-0.2 mm.
First, an annular groove is formed in the upper surface of the pedestal 10 by machining a counterbore of a diameter selected to be larger than the diameter of the pedestal 10. The depth of the groove is the copper electrode 22 '.
Is about 0.040 mm. Then, the polyimide lower layer closes the groove of the pedestal 10, leaving a groove corresponding to the upper surface of the polyimide lower layer, and the copper layer 22 'is disposed therein.

【0021】この構造は、図7として論じられた従来技
術の欠点を克服する。特に、積層板12は銅層22’の
外径から十分に平らな上面を示すので、ウェハ18の外
部領域は積層板との大きな接触面を有しかつ縁の漏れを
減少させる。また、図7の環状の隙間を図8では取り除
き、銅層22’とプラズマとの間の最小限の絶縁の厚さ
を約1.5mm、即ち、30倍以上に増大させる。従って、
チャックの有効寿命が顕著に延長し、その処理性能が改
善される。
This structure overcomes the shortcomings of the prior art discussed as FIG. In particular, since the laminate 12 exhibits a top surface that is sufficiently flat from the outer diameter of the copper layer 22 ', the outer area of the wafer 18 has a large contact surface with the laminate and reduces edge leakage. Also, the annular gap of FIG. 7 has been removed in FIG. 8 to increase the minimum insulation thickness between the copper layer 22 'and the plasma to about 1.5 mm, or more than 30 times. Therefore,
The useful life of the chuck is significantly extended and its processing performance is improved.

【0022】本発明のもう1つの重要な態様は、ウェハ
18の下面に冷却ガスを導入するために複数の開口を使
用することである。これは図5及び6に最もよく示され
ており、ペデスタル34はペデスタルの底を横切って広
がっている冷却材リザーバを備え、ねじ40でペデスタ
ルに固定された円形プレート38によって一部形成され
ている。冷却ガスはリザーバの一端にある単一通路42
を通ってリザーバ36に導入され、Oリング44がリザ
ーバを封着する。複数の穴46はペデスタルを通ってそ
の上面に形成される。対応する位置(図示されていな
い)の穴は、溝が従来技術の構造で形成されたように積
層板にも形成される。(図4参照。)100−200個
ほどの穴があり、その多くは積層板12の縁に近接して
配置される。穴46は直径が小さく、例えば、0.25−
0.50mmであり、上端又は出口端で小さな直径に先細に
なることが好ましい。
Another important aspect of the present invention is the use of multiple openings to introduce cooling gas to the underside of wafer 18. This is best illustrated in FIGS. 5 and 6, where the pedestal 34 includes a coolant reservoir extending across the bottom of the pedestal and is formed in part by a circular plate 38 secured to the pedestal with screws 40. . Cooling gas is provided in a single passage 42 at one end of the reservoir.
Through the reservoir 36 and an O-ring 44 seals the reservoir. A plurality of holes 46 are formed in the upper surface through the pedestal. Holes in corresponding locations (not shown) are also formed in the laminate as grooves were formed in prior art structures. (See FIG. 4.) There are about 100-200 holes, many of which are located close to the edges of laminate 12. The hole 46 has a small diameter, for example, 0.25-
It is preferably 0.50 mm and tapers to a smaller diameter at the upper or outlet end.

【0023】タングステンエッチバック工程における本
発明のプロトタイプテストにより、ウェハの全体の温度
が約10℃だけ低下しかつウェハの辺縁温度が80℃か
ら約60−65℃に低下した。更に、ウェハの中心とそ
の縁との間の温度勾配が15−20℃から6−10℃に
低下した。従来技術の静電チャックにおける過熱に関連
した欠点とは反対に、反復及び許容しうる工程結果が本
発明のチャックを用いて得られた。
The prototype test of the present invention in the tungsten etchback step reduced the overall temperature of the wafer by about 10 ° C and reduced the wafer edge temperature from 80 ° C to about 60-65 ° C. In addition, the temperature gradient between the center of the wafer and its edge was reduced from 15-20C to 6-10C. Contrary to the disadvantages associated with overheating in prior art electrostatic chucks, repetitive and acceptable process results have been obtained with the chuck of the present invention.

【0024】本発明のプロトタイプについての試験結果
から、静電チャックが十分な熱コンダクタンスと十分な
ヘリウム供給を与えてウェハ縁に漏出する場合には従来
技術のチャックにおいて過度と見なされていたウェハ縁
のヘリウムの漏れが工程に有害でないことが明らかであ
る。例えば、従来技術のチャックにおける縁の漏れは約
0.2−1.0sccm(1分当たりの標準立方センチメート
ル)であるが、本発明のチャックにおいては9トール圧
における2−5sccmの漏れの存在は工程に検出できる影
響を示さなかった。ほとんどの漏れは、ウェハ縁付近の
穴からであった。これらの穴を塞ぐと、約10倍、即
ち、0.4−0.6sccm漏れが減少したが、ウェハ縁の過熱
及び選択性の損失が生じた。
Test results on the prototype of the present invention indicate that if the electrostatic chuck provided sufficient thermal conductance and a sufficient helium supply to leak to the wafer edge, the wafer edge would be considered excessive in prior art chucks. It is clear that the leakage of helium is not detrimental to the process. For example, edge leakage in prior art chucks is about
Although 0.2-1.0 sccm (standard cubic centimeters per minute), the presence of a 2-5 sccm leak at 9 torr pressure in the chuck of the present invention had no detectable effect on the process. Most leakage was from holes near the wafer edge. Blocking these holes reduced leakage by a factor of about 10, or 0.4-0.6 sccm, but resulted in overheating of the wafer edge and loss of selectivity.

【0025】[0025]

【発明の効果】本発明は、以上説明したように構成され
ているので、ウェハ全面、特に辺縁にわたって効率よく
冷却し、縁における固定作用及びウェハ接触を改善し、
有効製品寿命を長くすることができる。
According to the present invention, since the present invention is constructed as described above, it is possible to efficiently cool the entire surface of the wafer, particularly over the edge, to improve the fixing action at the edge and the wafer contact,
Effective product life can be extended.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来技術の静電チャックの平面図であり、チャ
ックペデスタル内の中央冷却供給通路から発散する放射
状冷却溝を示す。
FIG. 1 is a plan view of a prior art electrostatic chuck showing radial cooling grooves emanating from a central cooling supply passage in a chuck pedestal.

【図2】実質的に2−2に沿った図1の従来技術の断面
図である。
2 is a cross-sectional view of the prior art of FIG. 1 substantially along 2-2.

【図3】従来技術の静電チャックの平面図であり、2種
類の冷却溝構造(分図(a)、(b))を示す。
FIG. 3 is a plan view of a conventional electrostatic chuck, showing two types of cooling groove structures (split diagrams (a) and (b)).

【図4】従来技術の静電チャックの断片的拡大断面図で
あり、チャックペデスタルの上に形成された積層ポリイ
ミドと銅層の一部を示す。
FIG. 4 is a fragmentary, enlarged cross-sectional view of a prior art electrostatic chuck showing a portion of a laminated polyimide and copper layer formed on a chuck pedestal.

【図5】本発明による静電チャックの平面図であり、チ
ャックペデスタル内に形成された複数の冷却穴を示す。
FIG. 5 is a plan view of an electrostatic chuck according to the present invention, showing a plurality of cooling holes formed in a chuck pedestal.

【図6】実質的に6−6に沿った図5の静電チャックの
断面図である。
FIG. 6 is a cross-sectional view of the electrostatic chuck of FIG. 5 substantially along 6-6.

【図7】図1の実質的に7−7に沿ってポリイミド及び
銅層の積層板がチャックペデスタル上でどのように形成
されているかを示す従来技術の静電チャックの断片的断
面図である。
FIG. 7 is a fragmentary cross-sectional view of a prior art electrostatic chuck showing how a laminate of polyimide and copper layers is formed on a chuck pedestal substantially along line 7-7 of FIG. .

【図8】図7と同様の断片的断面図であるが、本発明に
よる構造を示す。
FIG. 8 is a fragmentary sectional view similar to FIG. 7, but showing a structure according to the invention.

【符号の説明】[Explanation of symbols]

10…ペデスタル、12…積層板、13…中央開口、1
4、14’…溝、16…ねじ、17…絶縁継ぎ輪、18
…半導体ウエハ、20…ポリイミド下層、22…銅電極
層、24…ポリイミド上層、30…隙間、31…距離、
34…ペデスタル、38…円形プレート、40…ねじ、
42…単一通路、44…Oリング、46…穴。
10 pedestal, 12 laminated board, 13 central opening, 1
4, 14 '... groove, 16 ... screw, 17 ... insulating joint ring, 18
... Semiconductor wafer, 20 ... Polyimide lower layer, 22 ... Copper electrode layer, 24 ... Polyimide upper layer, 30 ... Gap, 31 ... Distance,
34 pedestal, 38 circular plate, 40 screw
42 ... single passage, 44 ... O-ring, 46 ... hole.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 シャモイル シャモイリアン アメリカ合衆国, カリフォルニア州 95120, サン ノゼ, ワシュー ド ライヴ 1256 (72)発明者 マヌーチャー ビラング アメリカ合衆国, カリフォルニア州 95036, ロス ガトス, ファブレ リッジ ロード 18836 (72)発明者 アルフレッド マク アメリカ合衆国, カリフォルニア州 94587, ユニオン シティ, フェロ ーズ コート 32722 (72)発明者 サイモン ダブリュー. タム アメリカ合衆国, カリフォルニア州 95035, ミルピタス, オレゴン ウ ェイ 1001 (56)参考文献 特開 平4−253356(JP,A) 特開 平5−121530(JP,A) 特開 平6−244144(JP,A) (58)調査した分野(Int.Cl.6,DB名) H01L 21/68──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shamoyl Chamoyrian United States, California 95120, San Jose, Washoe Drive 1256 (72) Inventor Manuture Billang United States of America, California 95036, Los Gatos, Fabre Ridge Road 18836 (72) ) Inventor Alfred Mac 32722, Union City, Union City, CA 94587, United States 32722 (72) Inventor Simon Double. Tam, United States, 95035, California, Milpitas, Oregon Way 1001 (56) References JP-A-4-253356 (JP, A) JP-A-5-121530 (JP, A) JP-A-6-244144 (JP, A) (58) Field surveyed (Int. Cl. 6 , DB name) H01L 21/68

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 静電チャックであって、 加工部材を支持するための略平坦な上面を有するペデス
タル; 絶縁された電極層を含む積層板であって、ペデスタルに
装着され、上記電極層に電圧を印加すると上記加工部材
が上記積層板に静電的に固定される前記積層板;及び 上記加工部材を下から冷却するガスを送るために上記ペ
デスタルと上記積層板を通って上に伸びている複数の穴
であって、該穴の多くが加工部材の外周付近に配置され
ている前記複数の穴; を備え、 上記ペデスタルが、上記ペデスタルの下に形成されかつ
全ての穴を横切って広がっている冷却ガスリザーバと上
記リザーバへの冷却ガス供給口を含み、且つ、上記ペデ
スタルが、外縁部を除くその上面に形成された凹部を有
し; 上記積層板が上記ペデスタルの上記上面の上記凹部に倣
った状態で、上記ペデスタルの上記上面の実質的全面に
伸びる第1絶縁層; 上記凹部に倣った上記第1絶縁層の部分の中をほぼ埋め
て、上記第1絶縁層上に配置される電極層;及び 上記電極層と、上記電極層に覆われない上記第1絶縁層
の部分とに伸びる第2絶縁層; を含み、 上記第2絶縁層が上記積層板の全面にわたって実質的に
平らな上面を示し、そのことにより上記電極層の外縁を
越えて加工部材と良好な接触が維持され、かつ上記電極
層が処理プラズマの影響から広く隔てられて静電チャッ
クの有効寿命を長くする静電チャック。
A pedestal having a substantially flat upper surface for supporting a processing member, a laminated plate including an insulated electrode layer, wherein the laminated plate is mounted on the pedestal and a voltage is applied to the electrode layer. The work piece is electrostatically secured to the laminate when applied, and extends upward through the pedestal and the laminate to send a gas to cool the work piece from below. A plurality of holes, many of which are located near an outer periphery of a work piece; wherein the pedestal is formed below the pedestal and extends across all holes. Wherein the pedestal includes a cooling gas reservoir and a cooling gas supply port to the reservoir, and wherein the pedestal has a recess formed in an upper surface thereof except an outer edge portion; A first insulating layer extending over substantially the entire upper surface of the pedestal in a state following the recess; and a portion of the first insulating layer following the recess is substantially buried and disposed on the first insulating layer. A second insulating layer extending over the electrode layer and a portion of the first insulating layer that is not covered by the electrode layer; wherein the second insulating layer substantially covers the entire surface of the laminate. A flat top surface, whereby good contact with the workpiece is maintained beyond the outer edge of the electrode layer, and the electrode layer is widely separated from the influence of the processing plasma to prolong the useful life of the electrostatic chuck. Electrostatic chuck.
【請求項2】 半導体基板を支持するための略平坦な上
面を有するペデスタル;及び 絶縁された電極層を含む積層板であって、上記ペデスタ
ル上に形成され、上記電極層に電圧を印加すると上記加
工部材が上記積層板に静電的に固定される前記積層板;
を含む静電チャックであって、上記ペデスタルが、外縁
部を除くその上面に形成された凹部を有し、該積層板が
上記ペデスタルの上記上面の上記凹部に倣った状態で、
上記ペデスタルの上記上面の実質的全面に伸びる第1絶
縁層; 上記凹部に倣った上記第1の絶縁層の部分の中をほぼ埋
めて、上記第1絶縁層上に配置される電極層;及び 上記電極層と、上記電極層に覆われない上記第1絶縁層
の部分とに伸びる第2絶縁層; を含み、 上記第2絶縁層が上記積層板の全面にわたって実質的に
平らな上面を示し、もって、上記電極層の外縁を越えて
上記加工部材と良好な接触が維持され、かつ上記電極層
が処理プラズマ粒子の影響から隔てられて静電チャック
の有効寿命を長くする静電チャック。
2. A pedestal having a substantially flat upper surface for supporting a semiconductor substrate; and a laminated plate including an insulated electrode layer, wherein the laminate is formed on the pedestal, and a voltage is applied to the electrode layer. The laminate in which a processing member is electrostatically fixed to the laminate;
An electrostatic chuck including: wherein the pedestal has a recess formed on an upper surface thereof excluding an outer edge portion, and in a state where the laminate follows the recess on the upper surface of the pedestal,
A first insulating layer extending substantially over the entire upper surface of the pedestal; an electrode layer disposed on the first insulating layer substantially filling a portion of the first insulating layer following the recess; A second insulating layer extending to the electrode layer and a portion of the first insulating layer not covered by the electrode layer; wherein the second insulating layer has a substantially flat upper surface over the entire surface of the laminate. Thus, an electrostatic chuck that maintains good contact with the processing member beyond the outer edge of the electrode layer, and extends the effective life of the electrostatic chuck by separating the electrode layer from the influence of processing plasma particles.
【請求項3】 絶縁された電極層を備えた積層部材とペ
デスタルとを有する静電チャックを製造する方法であっ
て、 上記ペデスタルの、外縁部を除く上部に、上記電極層の
厚さとほぼ等しい深さを有する浅い凹部を形成するステ
ップ; ペデスタルの実質的全面に、上記凹部に倣った状態で第
1誘電層を配置するステップ; 上記第1誘電層上に上記電極層を配置し、もって、上記
電極層が上記第一誘電層の凹部を充填するステップ; 上記第1誘電層と上記電極層との実質的全面に第2誘電
層を配置することにより略平坦な面を形成するステッ
プ; を含む方法。
3. A method for manufacturing an electrostatic chuck having a laminated member having an insulated electrode layer and a pedestal, wherein an upper portion of the pedestal except an outer edge portion has a thickness substantially equal to a thickness of the electrode layer. Forming a shallow recess having a depth; arranging a first dielectric layer on the substantially entire surface of the pedestal following the recess; arranging the electrode layer on the first dielectric layer; Filling the recesses of the first dielectric layer with the electrode layer; forming a substantially flat surface by disposing a second dielectric layer on substantially the entire surface of the first dielectric layer and the electrode layer; Including methods.
JP3993895A 1994-02-28 1995-02-28 Electrostatic chuck Expired - Lifetime JP2840041B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US20311194A 1994-02-28 1994-02-28
US08/203111 1994-02-28

Publications (2)

Publication Number Publication Date
JPH0846019A JPH0846019A (en) 1996-02-16
JP2840041B2 true JP2840041B2 (en) 1998-12-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP3993895A Expired - Lifetime JP2840041B2 (en) 1994-02-28 1995-02-28 Electrostatic chuck

Country Status (5)

Country Link
US (2) US5634266A (en)
EP (1) EP0669644B1 (en)
JP (1) JP2840041B2 (en)
KR (1) KR950034656A (en)
DE (1) DE69500566T2 (en)

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Also Published As

Publication number Publication date
JPH0846019A (en) 1996-02-16
DE69500566D1 (en) 1997-09-25
EP0669644A2 (en) 1995-08-30
US5671117A (en) 1997-09-23
KR950034656A (en) 1995-12-28
EP0669644A3 (en) 1995-12-13
US5634266A (en) 1997-06-03
DE69500566T2 (en) 1998-01-29
EP0669644B1 (en) 1997-08-20

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