JP2837105B2 - Receiver with sigma-delta analog-to-digital conversion for digital signals embedded in television signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for extracting a digital signal embedded in an analog television signal.

[0002]

With appropriate restrictions on the format of digital signals, relatively small signals (for example 3 to 5 IREs) encoding digital information can be mixed into composite video signals and reproduced from those composite video signals. It is possible to prevent adverse effects on the television image. US Patent Application "Processor for NTSCTV Signal with Digital Signal on Quadrature Video Carrier" (1993)
Application dated October 26, 08/141 070) describes a system by which Jim Yang does this,
This is also referred to herein. U.S. Patent Application No. 08
As with the present invention, / 141 070 has Samsung Electronics Co., Ltd. as an assignee, and the assignment has been made based on a predetermined employment contract to assign the invention made within the scope of employment. U.S. Patent Application No. 08/141 070
Describes binary phase shift keying (BPSK) modulation of a suppressed carrier that has the same frequency and quadrature relationship as a video carrier. U.S. Patent Application No. 08/14
In the TV receiver that separates the chrominance signal and the luminance signal without using a comb filter, 1070 sets the band of the BPSK signal to about 2 in order to avoid crosstalk in the chrominance signal.
It proposes to limit to MHz. US Patent Application N
o. 08/141 070 desirably performs processing by passing transmission data through a partial response filter, and performs line comb filtering in a digital signal receiver to separate the PSK subcarrier from the luminance portion of the composite video signal. After that, the data is extracted by the multi-level symbol determination circuit. U.S. Patent Application No. 08/14170 also proposes repeating BPSK frames in opposite phases in successive pairs in successive frames of the NTSC signal. Repeating the data over the frame pair makes the BPSK associated with the composite video signal detected in the NTSC television signal less noticeable in the image generated from the composite video signal and displayed on the screen. The technique of repeating data over a frame pair is the basis of a technique that uses a frame comb filter in a digital signal receiver to separate BPSK from the luminance signal portion of a composite video signal that represents a stationary portion in a continuous television image. ing.

[0003] US Patent Application No. 08/141 070
Assumes that after detection, B.sub.2 uses a flash converter commonly used to digitize the composite video signal.
It states that there are problems when digitizing PSK. When BPSK is detected synchronously, the remainder of the composite video signal of 750 kHz or more accompanies BPSK, but this remainder may be larger than BPSK. If digitization is B
If performed immediately after the synchronous detection of PSK, the remainder of such a large video signal will occupy most of the dynamic range provided by the flash converter for the analog input signal, and the flash has only about 8 bits of resolution. Relatively small BPSK due to transformer quantization noise
The signal resolution will be worse. Twelve-bit flash converters can also be manufactured, but are too expensive for use in general market electronics. US Patent Application 08/14
1070 is to suppress the relative magnitude of the residual of the composite video signal above 750 kHz, which is associated with BPSK.
It has been proposed to process the BPSK signal with an analog line comb filter before digitization. Thereby, the BPSK signal can be decomposed in a larger range of the digital output range of the flash converter to reduce symbol errors.

[0004] US Patent Application “Receiver for Oversampling Analog-to-Digital Conversion of Digital Signals in TV Signals” (filed 08/26/93, 1993)
41071), Thomas Vincent
Bolger points out that the price of flash converters rises sharply with increasing bit resolution, but the price rise for bandwidths above 2 MHz is relatively modest. U.S. Patent Application No. 08/141 07
The 2 MHz limit for BPSK in the system disclosed in US Pat. No. 0 requires a 4 MHz sampling rate for proper sampling at the maximum symbol rate, but this sampling rate is 16 MHz.
8-bit flash converters that can operate at 2x, 32x, or 64x are relatively inexpensive. So Borg
er point out that oversampling conversion methods can be used to achieve better bit resolution in such 8-bit flash converters. 4MHz
Performing oversampling at a rate 16 times the sampling rate of
Even if the detected BPSK is smaller than the coexisting composite video signal occupying most of the dynamic range of the flash converter, the detected BPSK can be digitized without being buried in the quantization noise.

An oversampling converter of the type known as a "sigma-delta" analog-to-digital converter is familiar to designers for obtaining multi-bit resolution using a basic single-bit resolution ADC. Things. Basic multi-bit resolution analog
Sigma-delta analog-to-digital converters for improving the bit resolution of digital converters are known. When the sigma-delta analog-to-digital converter is operated, the digital output signal is fed back to the digital-to-analog converter, and its output is sent to an analog subtractor. Generate an error signal. Quantization noise generated by analog-digital conversion is suppressed by degenerative feedback (suppressed by low-pass digital filtering with increasing frequency). Quantization noise generated during digital-analog conversion is not suppressed. For this reason, DAC
Single bit encoders that overcome the above problem have been favored in sigma-delta analog-to-digital converters. ADCs with a single bit encoder are 1 per second
It is not suitable for digital receivers receiving megabits or more of BPSK. This is because oversampling performed to satisfy the bit resolution requirement requires an impractical sampling rate. U.S. Patent Application No. 08/141 071,
A commonly known sigma using a multi-bit encoder
Due to problems trying to use delta-analog to digital converters, Bolger has pursued oversampling methods other than sigma-delta modulation.

[0006] Pressey Research Ca
swell Ltd. T. C. Leslie and B.S. S
Ingh has written a paper entitled "Improved Sigma-Delta Modulator Architecture" (1990 IEEE "Circuits and Systems 90" Symposium CH 2868-8900000-0372, p.
p. 372-375), by using a sigma-delta procedure that converts only one bit of the basic multi-bit resolution ADC output signal into an analog signal and feeds back the analog signal at each oversampling step. It is stated that the bit resolution of the multi-bit resolution ADC is improved.

[0007]

SUMMARY OF THE INVENTION The present invention solves the problems associated with analog-to-digital conversion that occurs after detecting relatively low power BPSK embedded in NTSC television signals.

[0008]

A BP of a subcarrier orthogonal to a video carrier amplitude-modulated by a composite video signal is provided.
In an embodiment of a digital signal receiver for detecting SK modulation, the BPSK to be detected is separated before the BPSK and the residual composite video signal are separated by a comb filter using a sigma-delta type oversampling analog-to-digital converter. Digitize.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Generally speaking, equalization delays have been omitted from the figures for simplicity and ease of understanding. Those skilled in the art of video signal processor design will recognize the need to provide such delays in order to properly time the pixels and data that experience various delays due to various processing in the various processing paths. Would. Those skilled in the art will understand where such a delay is needed and the length of the delay, but such a delay is not described or discussed below. For logic circuits, those skilled in the art will understand how to provide shimming delays to overcome undesirable "logic race" conditions or to compensate for potential delays in performing logical operations. The details of the logic circuit design for this purpose will not be described below. Furthermore, where analog-to-digital converters (ADCs) are shown and described in the disclosure below, those of ordinary skill in the art will appreciate that it is better to provide an anti-aliasing low-pass filter prior to such converters. , And how to set it up,
It is not described in detail below. Also, where digital-to-analog converters (DACs) are shown and described in the following disclosure, those of ordinary skill in the art should prefer to include a sampling clock rejection low-pass filter after such converters, and You will understand how to do this, but that is not described in detail below.

FIG. 1 shows a television transmitter 1 for transmitting a television signal in which a digital signal is embedded. The signal source 2 supplies one or more analog audio signals to an audio processing circuit 3, and the audio processing circuit 3 supplies a modulated signal to an audio carrier transmitter 4 for modulating the frequency of the audio carrier. The audio processing circuit 3 includes a necessary delay for synchronizing audio and images. In accordance with convention, the audio processing circuit 3 further includes a pre-emphasis network for the analog audio signal and generates stereophonic and secondary audio program subcarriers for inclusion in the modulated signal supplied to the audio carrier transmitter 4. May be provided. Typically, a frequency modulated (FM) audio carrier from a transmitter 4 is provided to a multiplexer 5 and frequency multiplexed with an in-phase VSB AM image carrier and a quadrature VSB BPSK data carrier. Radio broadcast TV transmitter 1
, The multiplexer 5 typically takes the form of an antenna coupling network, and the resulting frequency multiplexed signal is transmitted from a transmitting antenna 6.
The television transmitter used for the transmission station of the cable broadcasting system does not include the transmission antenna 6 used for wireless broadcasting. Multiplexer 5 because the frequency modulated signal sent from a given channel is further frequency modulated with a frequency modulated signal sent from another channel and the resulting signal is supplied to a cable broadcast trunk cable by a linear amplifier. Takes different forms.

In FIG. 1, a signal source 7 supplies an analog composite signal which forms the basis of a modulated signal supplied to a transmitter 8. The transmitter 8 supplies the VSB AM image carrier to the multiplexer 5, where the image carrier is frequency modulated (FM).
Subject to frequency modulation by a voice carrier. It synchronizes the vertical sync pulse, the horizontal sync pulse, and the corresponding signal provided by the color burst station sync signal generator 9 of the analog composite video signal provided by the signal source 7. The control connection 10 between the source 7 of the composite video signal and the station synchronization generator 9 represents the means used for this synchronization. If the signal source 7 is a distant generator for producing a composite video signal, for example, a town studio or another television station networked with a local television station, then the control connection 10 will generate a station synchronization signal. A genlock connection with the container 9 may be used. Signal source 7
If is a local camera, that camera is
May receive synchronization information from the station synchronization generator 9. Such synchronization methods, including synchronization to videotape and telecine devices, are familiar to those skilled in the art. Typically, the time division multiplexer 11 synchronizes synchronization block information including vertical synchronization pulses, horizontal synchronization pulses, equalization pulses, color bursts, and pedestals (often referred to as "porches") with local synchronization block information. Instead, it is used to insert into a composite video signal added as a modulation signal to the image carrier transmitter 8.

The television transmitter 1 shown in FIG. 1 further includes a VSB AM transmitter 12, and a vestigial sideband binary phase shift keying (VSB BPSK) suppressed carrier orthogonal to the VSB AM video carrier of the NTSC composite video signal. Is different from the conventional transmitter in that This VSB
The AM transmitter 12 may include a balanced modulator that is balanced for both the carrier and the BPSK modulated signal, and further receives the in-phase video carrier from the VSB AM transmitter 8 and converts the quadrature video carrier. It is possible to further include a 90 ° phase shift network feeding the balanced modulator. The VSB BPSK signal from the transmitter 12 is supplied to the multiplexer 5, like the VSB AM video carrier amplitude-modulated with the NTSC composite video signal from the transmitter 8, where it is frequency-modulated with a frequency-modulated (FM) audio carrier. You. The signal source 13 includes an error correction encoder 1 for additionally inserting an error correction code into a serial bit stream applied to the frame repeater 15.
4 is supplied with a digital signal in the form of a serial bit. The frame repeater 15 supplies each frame of the data received as its input signal twice as an output signal. The output signal from the frame repeater is provided to a partial response filter 16, which converts the data to a form that remains after line comb filtering performed in a digital signal receiver to suppress the composite video signal. . The digital response from the partial response filter 16 is sent to a digital-to-analog converter (DAC) 17 and converted into an analog keying signal. The DAC 17 supplies the high frequency pre-emphasis and shift shaping filter 18 with a keying symbol that takes a predetermined positive value corresponding to the digital zero and a predetermined negative value corresponding to the digital one. The predetermined negative level of the analog modulation signal has the same absolute value as the predetermined positive level of the analog modulation signal. The filter 18 compensates for a loss in detection efficiency when synchronously detecting VSB BPSK, but the loss is due to single sideband transmission. The response of filter 18 is the keying symbol provided to the balanced modulator of transmitter 12. A balanced modulator receives a quadrature video carrier to be modulated. A transmitter 8 that supplies a VSB AM video carrier subjected to amplitude modulation by the NTSC composite video signal to the multiplexer 5 avoids incidental phase modulation that may interfere with the quadrature VSB BPSK suppressed carrier from the operated transmitter 12. Carefully designed for. P
Since the quadrature VSB AM carrier for SK is suppressed, the phasing of the combined VSB PSK and VSB AM carrier is no different from that of the in-phase VSB AM video carrier. Although the transmitters 8 and 12 are depicted as separate from each other in FIG. 1, in practice the transmitters 8 and 12 can share the same upper sideband filter and final amplification stage.

FIG. 2 shows one form 160 that the partial response filter 16 can take. A digital input signal in the form of a serial bit is applied to the first input of a two-input exclusive-OR (XOR) gate 162 via an input terminal 161, and the output from the exclusive-OR gate is connected to an output terminal 163. Is supplied with the response of the partial response filter 160. A second input of XOR gate 162 receives a delayed response to an output signal applied by multiplexer 165 to a write input connection of digital delay line 164 from a read output connection of digital delay line 164. The digital delay line 164 can be a periodically addressed line storage memory that operates in an overwrite mode after reading and provides a "1H" delay equal to the duration of one horizontal scan line of the television. Multiplexer 1 except when the last row decoded result provided as a control signal to multiplexer 165 is 1, ie, when the last data row of the data frame is indicated to be provided to partial response filter 160.
65 selects the response of the partial response filter 160 appearing at the output terminal 163, and
4 to the write input connection.

When the last row decoding result supplied as a control signal to the multiplexer 165 is 1, that is, when it is indicated that the last data row is supplied to the partial response filter 160, the multiplexer 1
65 adds a modulo-2 data frame count to the write input connection of the digital delay line 164. When the modulo-2 data frame count so added is zero in the last row of the last frame of one pair of frames, the zero row is written to digital delay line 164 and the next one pair of frames is written. During the first row of data through the partial response filter 160 without change. But the multiplexer 165
Is selected and applied to the write input connection of digital delay line 164, if the modulo 2 data frame count is one in the last row of the first pair of data frames, a row of zeros is written to digital delay line 164 and one During the first data row of the last frame of the data frame of the pair, the data is one's complemented by passing through partial response filter 160. This gives 1
The other data rows in the last row of one pair of data frames are one's complement of the corresponding data rows of the first row preceding the pair of data frames.

The digital filtering by the partial response filter 160 suppresses a DC term in an analog signal generated by converting zeros and ones of a digital response appearing at an output terminal 163 into +1 and −1 amplitudes of a keying signal. This is, for example, BPSK
Controls signal generation. The digital filtering in half an odd multiple of the frequency of the horizontal line frequency f _H, showed a peak response, indicates zero response at multiples of the horizontal line frequency f _H. This digital filtering, PSK signal corresponding to data, now have comb frequency spectrum obtained by inverting the comb frequency spectrum of the luminance signal, its spectrum, zero response at odd multiples of half the horizontal line frequency f _H It is shown, indicating the peak of the response at multiples of the horizontal line frequency f _H. Partial response filter 160 shapes the spectrum of the PSK so that it passes through a 2-tap high-pass line comb filter that includes a single 1H delay line and a subtractor. Such a high-pass line comb filter can be placed in a digital signal receiver that suppresses the corrected luminance signal between vertically aligned pixels and transforms it as a jamming signal for PSK. it can.

FIG. 3 shows a partial response filter 1.
6 illustrates another form 166 that can be taken, including a final stage filter portion including the same elements 162 to 165 as the partial response filter 160. Partial response filter 166 further includes a first stage filter portion similar to its final stage filter portion. Input terminal 16
1, the first stage filter portion has a two-input exclusive OR gate 167, and the gate 167 is connected to the input terminal 1
It has a first input connected to 61 and an output connected to the first input of XOR gate 162 instead of being connected to input terminal 161 as in the case of partial response filter 160 of FIG. I have. XOR gate 16
The second input of 7 receives a delayed response to an output signal applied to the write input connection of digital delay line 168 by multiplexer 169 from the read output connection of digital delay line 168. Digital delay line 168
Provides, like the digital delay line 164, a "1H" delay equal to one period of the television horizontal scan line. When the decoding result of the last row supplied as a control signal to the multiplexer 169 is time 1, that is, when the last data row of the data frame is the partial response filter 1
Multiplexer 169 selects and applies the response of XOR gate 167 to the write input connection of digital delay line 168 except as indicated at 66.

When the last row decoding result supplied as a control signal to the multiplexer 169 is 1, that is, when it is indicated that the last data row is supplied to the partial response filter 166, the multiplexer 169
Adds a wired zero to the write input connection of digital delay line 164. This writes a row of zeros to the digital delay line 164 during the last row of each data frame. This zero row is provided to XOR gate 167 during the first row of the next data frame, and the first row of data is
2, the partial response filter 16 of FIG.
As described for 0, 1's complementation is selectively performed.

Compared to the partial response filter 160, the comb response of the partial response filter 166 has a sharper saw-tooth shape, and at the same time, the horizontal scanning line frequency f
A zero response at odd multiples of half of _H, a peak response at multiples of the horizontal line frequency f _H. In a digital signal receiver, a 3-tap high-pass line comb filter can be used to return the PSK signal to a flat frequency spectrum and transform the luminance signal into a PSK jamming signal.

FIG. 4 shows the details of the configuration of the portion of the television transmitter of FIG. 1 used for digital filtering of the digital data from which the phase shift keying signal is generated. The error correction encoder 14 supplies a digital signal to the rate buffer 20 in a serial bit form. Preferably, encoder 14 is of the type that generates modified Reed-Solomon codes, and rate buffer 20 also serves as an interleaver. The operation of the rate buffer 20 as an interleaver is performed by the VSB BPSK data transmitter 12 simultaneously with each horizontal scan line of the composite video signal sent by the VSB AM video transmitter 8 in the first order of column data scanning. Arrange so as to traverse the data line to be finally sent. This is compared to the case of a modified Reed-Solomon code that operates on data mapped to columns along the horizontal scan line rather than data mapped to columns that traverse the horizontal scan line. This is to reduce the number of impulse noises of the composite video signal, which tends to have directional coherence, and the number of jam bits of the modified Reed-Solomon code due to the middle band frequency. in any case,
The rate buffer 20 is a memory that supplies bits to the frame storage memory 21 at regular time intervals and writes only during alternate data frames.
A data frame is defined by a block of 525 rows of symbols and occurs at a scan rate that is a multiple of the data row scan rate. The data row scan rate is the same as the horizontal scan line rate of the analog composite video signal. BPSK
The symbol is a bit, but the symbol to which the modified Reed-Solomon bit is applied is typically 2 ^N- bit data (N is a small positive integer such as 3, 4 or 5). The bit length of each modified Reed-Solomon code is selected to be 525 or less (eg, 256 or 512),
Impulse noise does not disturb the modified Reed-Solomon code more than once along its length.

The relative phasing of the data rows of the composite video signal and the horizontal scan lines is performed such that each data row occurs simultaneously with a respective horizontal scan line of the composite video signal. The data frames occur at the same rate as the frames of the analog composite video signal provided by signal source 7, but for the reasons described later in this specification, nine horizontal scan lines of the composite video signal. It is convenient to delay the data frame from the video signal frame. The frame storage memory 21 is read out after the first data frame has been written and reread out after the second data frame has been written, and a partial response filter is provided between each frame of a continuous set of data frames. Generate an output signal that is provided as an input signal to the X.16. Writing and reading of the rate buffer 20 and the frame storage memory 21 are controlled by a frame storage packing control circuit 22.

The frame counter of the transmitter 1, which counts eight frame cycles to control the insertion of the ghost cancel reference signal into the composite video signal during a fixed vertical blanking interval (VBI) scan line, is used to determine the number of data frames. It includes a modulo 2 data frame counter 23 that controls the timing of the reading of the frame storage memory 21 and the overwriting operation after reading between the respective frames of each successive pair as one stage.
The packing control circuit 22 further includes a data row counter 2
4 and a symbol count signal from the symbol counter 25. The packing control circuit 22 applies the data row count signal as the row address designation and the symbol count signal as the in-row read address designation to the frame storage memory 21. The data row count and the symbol count form a complete addressing AD that the packing control circuit 22 adds to the frame storage memory 21 of FIG. Further, the circuit 22 includes a write enable signal WE for the frame memory 21, a read addressing RAD supplied to the rate buffer 20 in synchronization with a complete addressing AD supplied to the frame storage memory 21 during writing. Then, an address designation WAD for the rate buffer 20 is generated. When digital data is selectively transmitted, the circuit 22 further includes a frame storage memory 21.
For generating a read enable signal.

Specifically, the operation modes are as follows. The data frame count bits are supplied from the frame counter 23 to the packing control circuit 22 and are used to generate a write enable signal for the frame storage memory 21 only when the modulo 2 data frame count bits are zero. Packing control circuit 22
Supplies a read enable signal and a write enable signal that condition the frame store memory 21 to operate in a read-after-overwrite mode when the modulo 2 data frame count bit is zero. When the modulo 2 data frame count bit is 1, the packing control circuit 22 supplies only the read enable signal.

The last row decoder 27 has a data row counter 2
4 provides a control signal to the multiplexer 165 of the partial response filter 16 and also to the multiplexer 169 if used in the filter 16. The last row decoder 27 supplies a zero output signal as the last row decoding result for all values of the data row count other than those indicating the last row of the data frame. The zero output signal is supplied to the multiplexer 165 of the filter 16.
(And multiplexer 169 if used)
) Is adjusted so that the usual partial response filtering by the filter 16 is performed. If the data row count indicates the last row of the data frame, the last row decoder 27
65 (and multiplexer 16 if used)
9) also loads a 1-H delay line 164 (and delay line 168, if used) with the initial state of the filter 16 for the next data frame. The modulo-2 data frame counter 23 supplies the modulo-2 data frame count as a separate input signal to the multiplexer 165, which when the last row decoder 27 provides a 1 to the multiplexer 165 as a control signal. The input connection of the 1-H delay line 164 is selected.

FIG. 4 shows, in addition to the symbol counter 25,
Voltage-controlled oscillator (VCO) 31, zero-crossing detector 32,
A symbol clocking circuit 30 including a 255 count decoder 33 and an automatic frequency phase control (AFPC) detector 34 is shown. Symbol counter 25 includes eight binary count stages. Zero-crossing detector 32 (more precisely, it may be better to call it an average axis crossing detector)
Generates a pulse when the sinusoidal oscillations of oscillator 30 cross their average axis in a predetermined direction. The zero-crossing detector includes a limiter amplifier that generates a square wave corresponding to the variation of the sine wave of the VCO 31, a differentiator that generates a pulse corresponding to the variation of the rectangular wave, and a frame storage packing control circuit for the purpose of timing adjustment. 22 typically includes a clipper that separates pulses of one polarity that feed to 22. Further, these pulses are supplied to a symbol counter 25, counted on each successive line, and generate a symbol count signal supplied to a packing control circuit 22. When the symbol count reaches 255, the 255 count decoder 33 decodes it and generates a pulse. To reset the counter 25 for the next pulse provided by the zero-crossing detector to the counter 25, rather than letting the symbol count simply return to an arithmetic zero since the maximum count is an integer power of two, , 255
Each pulse from the count decoder 33 can be used, which returns the symbol count to an arithmetic zero. The 255-count decoder 33 supplies a pulse to the AFPC detector 34, and outputs the AFP supplied to the VCO 31.
A comparison is made with the horizontal synchronization pulse H for generating the C voltage. This completes a negative feedback loop that adjusts the VCO 31 to a fluctuating frequency of 255 times the horizontal scan line frequency, or 4027972 Hz.

One method of synchronizing the counting operation by the modulo-2 data frame counter 23 and the data row counter 24 with the frame of the analog composite video signal will be considered. In the digital signal receiver for the system described herein, a counter that regenerates the data frame count at the beginning of line 9 of each frame of the analog composite video signal is provided with a counter for the first field of such a frame. It is desirable to synchronize immediately after the trailing edge. In such a case, the counter that generates the data row count in the digital signal receiver is reset to a predetermined count value at the beginning of line 9 of each frame of the analog composite video signal. By synchronizing the counter operations of the modulo-2 data frame counter 23 and the data row counter 24 in the transmitter section shown in FIG. 4, a desired receiver characteristic can be obtained.

The output signal of the 255 count decoder 33 is provided as the first input signal to a two input AND gate 36. The station synchronization generator 9 supplies a vertical synchronization pulse V to a trailing edge detector 36, and the detector 36
Providing a pulse at the end of line 9 of the composite video signal;
In the middle of the composite video signal output signal line 271 the output signal is provided to the AND gate 35 as a second signal.
The response of the AND gate 35 is the line 9 of the composite video signal.
At the end of the data frame. Each of these data frame end pulses is applied as a trigger pulse to the modulo 2 data frame counter 23 to advance the data frame count signal and to add to the data row counter 24 to reset the data row count to a predetermined initial value. Can be In practice, the 255 count decoder 33 may be omitted, and the carry pulse from the last binary count stage of the symbol counter 25 is supplied to the AFPC detector 34 and the AND gate 35 instead of the decoder 33 output signal. May be done.

The transmitting device described above with reference to FIGS.
U.S. Patent Application No. Same as described in 08/141070. The digital signal receiver described below with reference to FIGS. 5-8 is an embodiment of the present invention. FIG.
Shows a digital signal receiver 37 for receiving a digital signal embedded television signal from a means such as an antenna 42 and extracting the embedded digital signal. Tuner 43 selects a television channel to be detected by a first detector, which is typically of the superheterodyne type for converting the selected television signal into a set of intermediate frequency and frequency images. Is a tunable down converter. Intermediate frequency (IF) filter 44
Selects the video intermediate frequency and inputs it to the intermediate frequency (IF) amplifier 45 to reject the image of the frequency. In accordance with current practice, surface acoustic wave (SAW) filters are
A monolithic integrated circuit (I
During C), the video IF amplifier 45 can be used as a multi-stage amplifier without intermediate tuning.
The video IF amplifier 45 supplies the amplified video IF signal to the in-phase synchronous video detector 46 and the quadrature phase synchronous video detector 47. Oscillator 48 oscillating at a nominal frequency of 45.75 MHz supplies the variation to in-phase video detector 46 without phase shift and is provided by quadrature network 49 to quadrature phase-locked video detector 47. 9
Supplied with 0 ° delay phase shift. The oscillator 48 has an automatic frequency and shift control (AFPC) responsive to the output signal of the quadrature phase locked video detector 47. Synchronous video detectors 46 and 47 are connected to video IF amplifier 45
And a portion of the oscillator 48 in the IC. Each of the video detectors 46 and 47 is of a higher carrier type or a true synchronous type. The in-phase corrected composite video signal extracted by the in-phase synchronized video detector 46 is supplied to a horizontal sync separator 50 and a vertical sync separator 51 for extracting horizontal and vertical sync pulses from the in-phase corrected composite video signal, respectively.

The video IF filter 44 is approximately 3.5M
Apart from the fact that it is desirable to have only a bandwidth of 45 Hz and a bandwidth of 45 Hz, the characteristics of the digital signal receiver 37 considered so far are familiar to those skilled in the art of television receiver design. is there. This video IF filter 44 provides color rejection and in-channel sound rejection without having to provide color and in-channel sound rejection after the quadrature video detector 47. (If digital signal receiver 37 is configured with a television receiver, video IF filter 44 may be extended so that subsequent filtering of quadrature video detector 47 provides color and in-channel sound rejection. Good.) The bandwidth of the quadrature video detector 47 needs to be somewhat wider than the symbol rate in order not to weaken the frequencies above the "tail" of the BPSK response. The quadrature-phase video detector 47 detects a keying signal accompanying only a portion of a frequency of 750 kHz or more in the NTSC composite video signal.

In practice, the digital receiver 37 usually includes a ghost suppression circuit, which is not clearly shown separately from other parts in FIG. US Patent Application N filed in
o. It may be of the same type as described in detail in 08/108 311. Each of the in-phase and quadrature-phase video detectors 46 and 47 includes a ghost cancel filter and an equalization filter similar to those used after the sync detector itself and the sync detector itself included in the other video detectors. Have each. The adjustable parameters of the two ghost cancellation filters are:
Adjustments are made in parallel according to the computations performed on the computer, and also the adjustable parameters of the two equalization filters are adjusted in parallel on the basis of further computations performed on the computer. A Ghost Cancel Reference (GCR) signal, which expands in frequency to 4.1 MHz during transmission, and which in a digital signal receiver only expands by about 2.5 MHz due to the limited IF bandwidth, has an in-phase synchronous video detector 4.
6 is extracted from the selected vertical blanking interval (VBI) scan line of the video signal detected. The GCR signal is digitized and provided as an input signal to a computer that calculates tunable parameters of the ghost cancellation filter and the equalization filter. Alternatively, or in addition, the DC or low frequency portion of the quadrature video detector 47 response may be sensed and used as a basis for calculating the adjustable parameters of the ghost cancellation filter.

In the digital signal receiver 37 shown in FIG. 5, the sample count per symbol signal is a sample per symbol which counts the pulses generated by the zero-crossing detector 104 in response to the fluctuation of the sine wave received from the voltage controlled oscillator 105. Generated by the counter 103. The symbol count signal is generated by the symbol counter 52 that counts overflow carry from the sample counter 103 per symbol. Decoder 55 decodes the symbol count reaching 255,
Generates a pulse that resets counters 103 and 52 on the next pulse provided to counter 103 by zero-crossing detector 104, returning both the sample count per symbol and the symbol count to arithmetic zero. The pulses generated by the decoder 55 are separated by a horizontal sync separator and sent to the AFPC 56 for comparison with a horizontal sync pulse that is adjustably delayed by a control delay line 57 for a fraction of a symbol interval. Supplied. The result of the comparison is low-pass filtered in AFPC 56 to generate an automatic frequency and phase control (AFPC) voltage signal to be applied to VCO 105. By these methods, the oscillation frequency of the line-locked VCO 105 is changed to the horizontal scanning line frequency f _H, that is, 64 457545H.
so that 16 × 256 = 4096 times of z
Control. The term "line-locked" used in describing a controlled oscillator means that its oscillation frequency is 1
It shows that a certain ratio is maintained with the scanning line frequency of 5,734.264 Hz. This is typically done by an AFPC circuit that compares the horizontal sync pulse with a value obtained by dividing the oscillation frequency by an appropriate rate.

The keying signal, and the portion of the NTSC composite video signal detected by the quadrature video detector 47 which has a frequency of 750 kHz or more, is supplied to a matched filter 58. The matched filter responds to the keying signal, but only to selected portions of the 750 kHz frequency component of the accompanying composite video signal. Matched filter 58 provides a peak response that matches the roll-off of the de-shaping portion of filter 18 of the transmitter, and extends the PSK bandwidth sufficiently to reduce intersymbol interference. Further, the matched filter 58 has a.
VSB BP in the frequency range of 75 to 1.25 MHz
The SK becomes more single-sideband and provides a peak response to compensate for the roll-off of the detection efficiency of the quadrature-phase video detector 47 due to the fact that it is effectively a single-sideband in the frequency range above 1.25 MHz. You can also. However, since the vestigial sideband filters of the different television transmitters show differences from each other, the peak response to compensate for the detection efficiency roll-off of the quadrature video detector 47 will be adequate in addition to shaping the variation. This is done at each television transmitter 1 by modifying the shift shaping filter 18 to provide a peak response. The additional peaking or pre-emphasis of the binary keying signal in the transmitter 1 increases the BPSK high frequency component of 0.75 MHz or more sent with the luminance signal.

The response from matched filter 58 is applied as an input signal to analog-to-digital converter (ADC) 106. Quadrature video detector 47 is 750 kHz
Hardly extracts composite video signal frequencies less than
The PSK code is performed to have a zero frequency component. 7
When transmitting television images at frequencies above 50 kHz without using much energy, the BPSK portion of the response of the quadrature synchronous video detector 47 indicates an alternation from one polarity to another. Therefore, the ADC 106 has a function of digitizing a positive or negative analog signal. According to the present invention, the ADC 106 is
It is a sigma-delta converter.

More specifically, the ADC 106 includes:
T. C. Leslie and B.S. Singh's paper, "Architecture of Improved Sigma-Delta Modulator" (1990 IEEE Symposium on Circuits and Systems, 90 CH2868-8900000-0372,
Preferably, it is a multi-bit sigma-delta converter with single bit feedback, as described in pp. 372-375). An 8-bit resolution flash converter (sold for a reasonable price) samples the error signal in a second order feedback loop, and single-bit feedback is used to minimize digital-to-analog conversion errors. The second order sigma-delta feedback loop is unconditionally stable. For an oversampling ratio of 16: 1,
The error signal is sampled at a rate 16 times the symbol rate 256 times the horizontal scanning line rate f _H ,
In response to the oscillation of oscillator 105 traversing the zero axis in a predetermined direction, a pulse is output from zero-crossing detector 104 to line 1.
Sampling is performed each time it is received through 07.
The digital output of the flash converter is fed to a FIR low-pass filter in converter 106, whose digital response is 16: 1 subsampled by a subsampler, where pulses are taken from carry overflow of sample counter 103 per symbol. Line 10
Sampling is performed each time it is received on 8. This decimation reduces the storable amount required for the delay portion of the subsequent digital comb filter. Subsampling at the symbol rate, with optimal phasing, suppresses the response to portions of the composite video signal that vary at the symbol rate but are quadrature for sampling at the symbol rate. This is a form of synchronization symbol detection.

The single bit ADC 109 samples at a symbol rate 16 times the symbol rate of 256 times the horizontal scan line rate f _H , corresponding to the pulse provided on line 108 by the zero crossing detector 104, and provides a matched filter. The matched filter 58 responds to the 58 response to provide a sign bit representing the polarity of the 58 response. The sign bit and the sign bit delayed by one sample in the bit latch 110 are supplied as respective inputs to an exclusive OR gate 111. The XOR gate 111 detects the response of the matched filter 58 and supplies the detection result to the pulse phase discriminator 67. The pulse phase discriminator 67 selectively detects that the zero crossings of the response of the matched filter 58 deviate from proper phasing with respect to the zero crossings of the oscillations of the controlled oscillator 105. The shift is detected by the XOR gate 111, and the zero crossing is detected by the zero crossing detector 104. The pulse phase discriminator 67 samples and holds these selectively detected shifts and low-pass filters them, thereby adjusting the delay provided by the control delay line 57 for the horizontal sync pulse H applied to the AFPC 56. To generate a control signal. Pulse phase discriminator 67
Can be performed during the vertical blanking interval where the value of the quadrature video detector 47's response to the composite video signal is expected to be zero. Second
During digitization of the order sigma-delta error signal, the oversampling by the flash converter of the ADC 107 is adjusted to minimize inter-symbol interference.

The technique for adjusting the phasing of a line-locked oscillator is the same as the type developed by Jung-Wan Ko (a colleague of the present inventor). The AFPC loop, which controls the phasing of the oscillating frequency of the control oscillator 105 with respect to the adjustable delayed horizontal sync pulse H provided from the control delay line 57, causes the ADC 106 to "glitch" or noticeably clocking during the phase adjustment. A filter function is provided to avoid showing a reduction in periodicity. Such glitches sometimes occur if fine phase adjustments are made in the ADC 106 clocking itself. The vertical sync separator 51 provides a "lossy" integrated response to the separated vertical sync pulse V to the threshold detector 68, the threshold voltage of which is determined by the vertical sync pulse 5.5 scans. It is selected to exceed the threshold only when integrated over lines and below 6.5 scan lines. The output signal of threshold detector 68, which is 1 only when the input signal exceeds its threshold voltage and otherwise zero, is provided as the first input signal of 2-input AND gate 69. A decoder 55 that produces a 1 (at the end of the horizontal scan line) for the final value of the symbol count for each data row, and otherwise produces a zero, outputs its output signal to a second It is supplied to an AND gate 69 as an input signal. AND gate 69 is responsive to the trailing edge of the vertical pulse occurring at the beginning of the first field of the composite video signal frame and provides a respective data frame end pulse corresponding to each of these edges, but for each of the frames. Does not correspond to the trailing edge of the vertical pulse that occurs between the first and last fields of.

The data frame end pulse in response to the AND gate 69 is supplied as a count input (CI) signal to a modulo 2 data frame counter 70 to advance the regenerated data frame count signal, but the data frame count is It is offset by one scanning line from the data frame count signal. U.S. Patent Application No.
As described in 08/108, 311, to synchronize the data frame count between the television transmitter 1 and the digital data receiver 37, the burst phase alignment and the Bessel chirp on the 19th scan line in a 4 frame cycle are performed. It is best to refer to a ghost cancel reference (GCR) signal that occurs in a given permutation of the phasing. The single binary stage counter 70 that generates a modulo 2 data frame count is often one stage in a multiple binary stage counter that generates a modulo 2 ^N data frame count. N is a positive integer of 2 or more. For more than one binary counter, see Ghost Cancel (
GCR) is used to adjust the timing of signal storage.

Further, the data frame end pulse in response to the AND gate 69 is applied to the data row counter 71 as a reset (R) signal, and its output signal resets the regenerated data row count back to arithmetic zero. . The data row count must then be 524. The data row counter 71 is provided with the horizontal sync separator 5
It is connected so as to count the horizontal synchronization pulse H supplied from 0. The data row count is used to obtain data for a computer that calculates adjustable filter parameters for the equalization and ghost cancellation filters included in video detectors 46 and 47 (shown clearly in FIG. 5). (Not shown) to control the selection of VBI scan lines that contain the GCR signal.

High-pass frame comb filter 72 receives the digital response of ADC 106 as an input signal. The high-pass frame comb filter 72 includes a digital subtractor 73 and a digital frame storage 74 that supplies the signal sample to the output terminal with a delay of one frame scanning corresponding to the signal sample applied to the input terminal.
The digital frame storage 74 is preferably configured as a ram that operates in an overwrite mode after reading. This ram receives the data row count from counter 71 as line addressing (LAD) and the symbol count from counter 52 as symbol addressing (SAD). Subtractor 73 receives a sample of the digitized keying signal for the current frame from ADC 106 as the minuend input signal and a corresponding sample of the digitized keying signal for the previous frame from frame store 74 as the subtrahend input signal. receive. The difference signal from the subtractor 73 is the response of the high-pass frame comb filter 72, from which the residual luminance component indicating the frame-to-frame correlation is removed.

The high pass line comb filter 120 receives this response as an input signal. The high-pass line comb filter 120 is a matching filter for the partial response filter 160 in FIG. 2 used as the partial response filter 16 in the transmitter 1 in FIG.
The high-pass line comb filter 120 suppresses portions of the composite video signal that accompany the detected keying signal but do not change line by line. The specific structure of the filter 120 will be described later in this specification with reference to FIGS.

The portion of the analog signal provided as an input signal to ADC 106 represents the binary code of the keying signal. Therefore, the digital signal supplied to the high-pass frame comb filter 72 as an input signal is also the same. The digital response from the high-pass frame comb filter 72 provided as an input signal to the high-pass line comb filter 120 is still representative of the binary code of the keying signal of the alternating data frames that are valid data frames. In those data frames, a subtractor 73 differentially combines the two data frames whose corresponding digital samples have equal amplitude and opposite polarity. In an intervening data frame, which is an invalid data frame, the digital response of the high-pass frame comb filter 72 supplied as an input signal to the high-pass line comb filter 120 has a ternary nature. Because, in those data frames, the subtractor 73 determines that the corresponding digital samples may have the same amplitude and opposite polarity, or they may have the same amplitude and the same (plus or minus) polarity2. This is because two data frames are combined differentially. During these invalid alternating data frames, the digital response from the high-pass line comb filter 120 has a five-level nature, but symbol decisions based on invalid data frames are irrelevant. During a valid alternating data frame, the digital signal provided as an input signal to the high pass line comb filter 120 represents the binary code of the keying signal, and thus the digital response from the high pass line comb filter 120 is the ternary code of the keying signal. Represents

The symbol decision circuit 75, which receives the digital response of the high-pass line comb filter 120 as an input signal, therefore has a 3
Has comparator ranges. Symbol determination circuit 75 includes an absolute value circuit 751 that generates a modified digital response to the output signal from high pass line comb filter 120. The modified digital response of absolute value circuit 751 represents the binary code of the keying signal and is provided to threshold detector 752.

The threshold detector 752 detects the keying signal 2
This is a symbol determination circuit of a type well known in digital communication technology for performing symbol determination on a hexadecimal code. The threshold detector 752 receives the symbol stream from the absolute value circuit 751 and determines whether the symbol is likely to be zero or one. Threshold detector 752 typically includes a digital comparator adapted to operate as a threshold detector, and determines whether a symbol is likely to be one or zero based on whether a digital threshold has been exceeded. Use the detection results. Preferably, the threshold detector 752 is of a type in which the digital threshold for detecting the threshold is automatically adjusted, preferably according to the strength of the symbol. In such a case, the threshold detector 752 includes associated circuitry for detecting the average peak level and / or the average level of the symbol stream provided by the absolute value circuit 751. There is associated circuitry for calculating a digital value that is provided to the comparator to determine a threshold for threshold detection from each level detected. The detection procedure for determining the symbol determination threshold is preferably selectively performed during the vertical blanking interval. During that interval, the composite video signal contributes little energy to the signal detected by quadrature video detector 47.

The symbol stream from the symbol determination circuit 75 is supplied as an input signal to the rate buffer 77, and the rate buffer cancels the luminance signal portion of the alternate frame in which the keying signal is not canceled but does not change from frame to frame. From the frame only, it is conditioned by the data frame count to accept input samples. Digital samples are provided to the rate buffer at the sample rate, output from the rate buffer at half the symbol rate, and applied to the error correction encoder 78. The encoder 78 receives the result of the decision made by the symbol decision circuit 75 as serial bit digital input data, corrects errors therein, and supplies corrected serial bit digital data. The modified digital serial bit data is output data of the digital signal receiver 37, and the signal source 13
Must correspond to the serial bit digital data shown in FIG.

A digital signal receiver 37 designed for use in a transmitter 1 using a modified Reed-Solomon code that operates on columns of data across horizontal lines, rather than columns of data along horizontal scan lines. In the preferred embodiment, rate buffer 77 operates as a deinterleaver for error correction decoder 78. The write address generator for the rate buffer 77 is not shown in FIG. The read address generator includes a data row counter 71 that supplies a data row count and a symbol counter 52 that supplies a symbol count, and specifies row and column addresses in the ram in the rate buffer 77.

FIG. 6 shows the digital signal receiver 37 of FIG.
2 shows a digital signal receiver 38 designed to be used with the transmitter 1 using the partial response filter 160 shown in FIG. Compared with the digital signal receiver 37, the order of the high-pass frame comb filter 72 and the high-pass line comb filter 120 cascaded with each other in the digital signal receiver 38 is reversed.

FIG. 7 shows the digital signal receiver 37 of FIG.
4 shows a digital signal receiver 39 designed to be used with the transmitter 1 using the partial response filter 166 shown in FIG. In this digital signal receiver 39, another high-pass line comb filter 130 follows the high-pass line comb filter 120. High pass line comb filters 120 and 130
This cascade connection is tapped at 1-H, 2-H delay intervals to produce a filter response (-0.2
5): Equivalent to using a digital delay line to provide an input signal to a weighted weighted network weighted at the ratio of 0.5: (-0.25).

If the partial response filter of the transmitter is a type 166 corresponding to that shown in FIG. 3, the digital signal receiver includes a three-scan high-pass line comb filter of the type shown in FIG. 7 or a corresponding type. If so, the digital response of the high-pass frame comb filter 72 during a valid data frame is essentially five levels rather than ternary in terms of representing a PSK signal. Therefore, in FIG. 7, the symbol determination circuit 75 of FIG. 5 or 6 having three comparator ranges centered on -1, 0 and +1 respectively.
Replaces the symbol decision circuit 76 which has five comparator ranges centered at -2, -1, 0, +1 and +2. The symbol determination circuit 76 includes an absolute value circuit 761, which generates a modified digital response to the output signal of the high-pass frame comb filter 72. The modified digital response of the absolute value circuit 761 does not represent the binary code of the keying signal, but rather the ternary code of the keying signal superimposed on the DC voltage pedestal. Thus, this modified digital response is provided to a dual threshold detector 762.
The dual threshold detector 762 receives the symbol stream from the absolute value circuit 761 and determines whether the symbol is likely to be zero, one, or two. 2 is equated with zero. The dual threshold detector 762 typically includes two digital comparators, each operating as a single threshold detector. One digital threshold is twice that of the other. As a result, a simple logic circuit that specifies the symbol depending on the threshold detection result is obtained. If neither threshold is exceeded,
Logic indicates that the symbol is probably zero. If only a low digital threshold is exceeded, the logic indicates that the symbol is probably one. If both the high and low digital thresholds are exceeded, the logic indicates that the symbol is probably two, which equates to zero. Double threshold detector 7
Desirably, the type 62 is a type in which a digital value supplied to a comparator for determining a threshold value for threshold value detection is automatically adjusted according to the strength of a symbol. In such a case, the dual threshold detector 762 includes associated circuitry for detecting the average level of the symbol stream provided by the absolute value circuit 761 and / or its average peak level. From each detected level there is a circuit that calculates a digital value to be supplied to the digital comparator so that a respective threshold for threshold detection can be established. The detection procedure for determining the symbol determination threshold is preferably selectively performed during the vertical blanking interval. During that interval, the composite video signal contributes little energy to the signal detected by quadrature video detector 47.

FIG. 8 shows the digital signal receiver 39 of FIG.
4 shows a digital signal receiver 40 designed to be used with the transmitter 1 using the partial response filter 166 shown in FIG. In the digital signal receiver 40, the high-pass frame comb filter 7
2 a digital signal receiver 3 placed after the cascade connection of the high-pass line comb filters 120 and 130
Unlike 9 is placed in front. A configuration in which the high-pass frame comb filter 72 is disposed after the high-pass line comb filter 120 but before the high-pass line comb filter 130 is another embodiment of the present invention.

The digital signal receiver 37 of FIGS.
7 and 8 and the symbol decision circuit 76 of the digital signal receivers 39 and 40 of FIGS. 7 and 8 are decoded to perform what data communications technicians call "hard decision" forward error correction. Each "hard" decision is made to provide a binary input signal to the unit 78. Of course, instead, the symbol decision circuits 75 and 76 perform what the data technician calls "soft decision" forward error correction,
It can also be replaced by a circuit that supplies an input signal with multiple levels in a suitable decoder.

FIG. 9 shows in detail one form 121 that the high-pass comb filter 120 can take. An input terminal 122 of the filter 121 is connected to a differential amplifier 123 whose output connection is connected to an output terminal 124 of the filter 121.
To the non-inverting input connection of The inverting input connection of the difference input amplifier 123 receives the delayed response to the output signal from the multiplexer 126 from the output connection of the analog delay line 125. The output signal of the multiplexer 126 is
In addition to the input connection of delay line 125. Analog delay line 125 provides a delay equal to the duration of one horizontal scan line. Such "1-H" delay lines, if analog in nature, are often configured as charge coupled device (CCD) shift registers. The difference input amplifier 123 is included in the charge sensing output stage of the CCD shift register, and is often configured in the form of a monolithic integrated circuit (IC) together with the CCD shift register and the charge injection input circuit. Multiplexer 126 uses field effect transistors acting as transmission gates,
It is convenient to configure them in the same IC.

The multiplexer 126 receives the control signal from the decoder 61. When the data row count from the data row counter 71 reaches the value corresponding to the last row of the data of the data frame, the decoder 61 receives the control signal. Respond and respond with zero to all other values of the data row count. In response to the output signal of the decoder 61 being 1, the multiplexer 126 selects analog 0 as its output response. In response to the output signal of the decoder 61 being zero, the multiplexer 126 selects the detected BPSK signal supplied to the input terminal 122 and selects the 1-H delay line 125
In addition to the input connections.

FIG. 10 shows a high-pass line comb filter 12.
Show in detail another form 127 where 0 can take. This is a variation of the form shown in FIG. 9, but does not include elements 125 and 126. The output connection of the multiplexer 128 connects to the inverting input connection of the difference input amplifier 123 of FIG. Multiplexer 128 receives the control signal from decoder 62, which responds with a 1 when the data row count is reset from data row counter 71 to a value corresponding to the first row of data in the data frame. ,
Respond with zero to all other values of the data row count.
In response to the output signal of decoder 62 being one, multiplexer 128 selects analog zero as its output response. In response to the output signal of the decoder 61 being zero, the multiplexer 128 selects the output signal from the 1-H analog delay line 129, and
To the non-inverting input connection. 1-H analog delay line 12
The output signal at 9 is a delayed response to the signal provided to input terminal 122 of filter 120, the delay being equal to the duration of one horizontal scan line. FIG. 11 shows in detail one form in which the cascading of the high pass line comb filters 120 and 130 can take. The high-pass line comb filter 121 is the same as that of FIG. 9, and the high-pass line comb filter 131 of FIG.
And elements 132-136 similarly connected inside the boundaries of each filter.

FIG. 12 shows a high-pass line comb filter 1.
Figure 3 details another form that the cascade of 20 and 130 can take. High-pass line comb filter 12
7 is the same as that of FIG. 10, and the high-pass line comb filter 137 of FIG. 12 corresponds to the elements 128 and 129 of the high-pass line comb filter 127 and the elements 138 and similarly connected inside the boundary of each filter. 1
Have 39.

FIG. 13 shows a form that the rate buffer 20 shown in FIG. 4 can take when used as an interleaver for the modified Reed-Solomon code supplied from the error correction encoder 14. Data frame pair counter 80 carries out (C) supplied from data frame counter 23 as count input (CI).
I) Receive a signal. Data frame pair counter 80
Is a random access memory 8 for storing two data frames operating as an interleaver for the error correction code.
It controls the alternate write and read operations at 1 and 82. The rams 81 and 82 are written from the address error correction encoder 14 at half the PSK rate during alternate frame pair intervals, and are addressed by columns and symbols per column. Each of the rams 81 and 82 is read into the frame store memory 21 at the PSK rate at each frame pair interval following the frame pair interval at which writing occurs, and address scanning is performed by rows and symbols per row. The "symbol" of the per-row symbol described herein is a PSK symbol or bit, and is a symbol associated with the modified Reed-Solomon code considered from a coding point of view.
Not an ^N- bit symbol.

As a read address designation, the address multiplexer 83 receives the data row count from the data row counter 24 and the symbol per row count from the symbol (symbol per row) counter 25. As a write address designation, the address multiplexer 83
Data row count is received from data row counter 84 and symbol per column count from symbol per column counter 85. The zero-crossing detector supplies a trigger pulse at a PSK rate to the triggered flip-flop 86, which uses the alternating variation of its output signal at half the PSK rate as a count input (CI) to provide a symbol counter per column. It functions as a frequency divider for supplying to the frequency divider 85. Decoder 87 decodes when the symbol per column count reaches a maximum count (525 assuming that the symbol count per column started from zero) and provides a count input (C) to data row counter 84.
I) Supply 1 as a signal. The output signal of the decoder 87 is supplied as a first input signal of a two-input OR circuit 88, which resets the per-column symbol counter 85 in response to a 1 from the decoder 87 ( R) Supply 1 as a signal to reset the symbol count per column to its initial value.

The second input signal to the OR circuit 88 and the reset (R) signal to the data column counter 84 are supplied by the output response from the three-input AND gate 89. When the output response is 1, Reset the per-column symbol count and data column count to their initial values. Only when the data row count indicates that the last row of the data frame has been reached, the decoder 260
A first input of D gate 89 provides a logic one. Otherwise, decoder 260 provides a logical zero as an output signal to AND gate 89. (If the partial response filter 160 is used at the transmitter 1, the decoder 260 may be the decoder 27 of FIG. 4 so that the decoder 27 reaches the last row of the data frame. This is designed to supply a logical 1 only when the data row count indicates that the data row count has been performed.)
The three input signals of ND gate 88 are applied as the other two. Only when the selected one of the RAMs (RAMs) 81 and 82 reaches the last symbol of the last data row in the odd frame immediately before the even frame to be read into the frame storage memory 21 for each data row, and The output response is 1.

When the modulo 2 data frame pair count from the data frame pair counter 80 becomes 1, the address multiplexer 83 selects the read address designation for the ram 81 and the write address designation for the ram 82. If the modulo 2 data frame pair count from the data frame pair counter 80 is 1, the RAM 81 is stored in the frame storage memory 21 for each data row.
If the one's complement of the count is zero, the error correction encoder 14 can write to the RAM 82 for each data string.

If the modulo 2 data frame pair count from data frame pair counter 80 is zero,
The address multiplexer 83 can select the read address designation to the ram 82 and can select the write address designation to the ram 81. If the modulo 2 data frame pair count from the data frame pair counter 80 is zero, the ram 82 can be read into the frame storage memory 21 for each data row, and if the one's complement of the count is one, the ram 82 81 can be written from the error correction encoder 14 for each data string.

FIG. 14 shows a possible form when the rate buffer 77 shown in FIGS. 5-8 is used as a deinterleaver for the modified Reed-Solomon code supplied from the symbol decision circuit 75 or 76. Data frame pair counter 90 receives a carry-out (CO) signal supplied from data frame counter 70 as a count input (CI) signal. The data frame pair counter 90 controls alternate writing and reading of the two data frame storage random access memories 91 and 92 which operate as a deinterleaver for the error correction code. Rams 91 and 92
Is written only during alternate even frames,
The data written to 1 and 92 are supplied from the symbol determination circuit 75 or 76 at the PSK rate, and the address scanning is performed row by row and symbol by row. The "symbol" of the symbol per line here is
PSK symbol or bit, not the 2 ^N bit symbol associated with the modified Reed-Solomon code considered from an encoding point of view. Each of the rams 91 and 92 is read out to the frame store memory 21 at half the PSK rate during alternate frame pair intervals, and address scanning is performed column by column and symbol by column.

As a write address designation, the address multiplexer 93 counts the data row count from the data row counter 71 and the symbol (symbol per row) counter 5.
Receive the symbol row count from 2. As a read address designation, the address multiplexer 93 receives the data row count from the data column counter 94 and the symbol per column count from the symbol per column counter 95. Zero-crossing detector 104 generates PSK
It supplies to the triggered flip-flop 96 at a rate.
Flip-flop 96 uses the alternation of its output signal at half the PSK rate as the count input (CI)
It functions as a frequency divider for supplying to the per-column symbol counter 95. Decoder 97 decodes when the per-column symbol count reaches a maximum count (525 assuming that the per-column symbol count starts from zero), and provides a count input (C) to data row counter 94.
I) Supply 1 as a signal. The output signal of the decoder 97 is provided as a first input signal of a two-input OR circuit 98, which resets the per-column symbol counter 95 in response to a 1 from the decoder 97 ( R) Supply 1 as a signal to reset the symbol count per column to its initial value.

The second input signal to the OR circuit 98 and the reset (R) signal to the data string counter 94 are supplied by the output response from the three-input AND gate 99. When the output response is 1, Reset the per-column symbol count and data column count to their initial values. Only when the data row count indicates that the last row of the data frame has been reached, the decoder 61
A first input of gate 99 provides a logic one. Otherwise, decoder 61 supplies a logical zero as an output signal to AND gate 99. The output signal of the data row last symbol decoder 55 and the modulo 2 data frame count from the data frame counter 70 are applied as the other two of the three input signals of the AND gate 98.
Only when an even frame in which writing is performed for each data row from the symbol determination circuit 75 or 76 comes to a selected one of the rams 91 and 92 and when the last symbol of the last data row is reached in an odd frame, an AND gate is provided. 98
Output response is 1.

When the modulo 2 data frame pair count from the data frame pair counter 90 becomes 1, the address multiplexer 93 selects the address designation for the ram 91 and the write address designation for the ram 92. If the data frame pair count from the data frame pair counter 90 is 1, the ram 91 can be read out to the error correction decoder 78 for each data string. Two-input AND gate 101 selects 1 as the write enable (WE) signal to ram 92 in response to the data frame count from counters 70 and 90 and the one's complement of the data frame pair becoming zero. Supply. With the WE signal, the ram 92 can be written from the symbol determination circuit 75 or 76 for each data row.

If the modulo 2 data frame pair count from data frame pair counter 90 is zero,
The address multiplexer 93 can select the read address designation to the ram 92 and can select the write address designation to the ram 91. If the data frame pair count from the data frame pair counter 90 is zero, the ram 92 is sent to the error correction decoder 78 for each data stream.
Can be read out. 2-input AND gate 10
2 means that the 1's complement of the data frame count becomes zero and the data frame pair count from the counter 90 becomes 1
In response to this, 1 is selectively supplied to the ram 91 as a write enable (WE) signal. This WE
The signal determines the symbol determination circuit 75
Alternatively, writing can be performed for each data row from 76.

The rate buffering performed in the digital signal receivers 37-40 is intended to fill gaps generated when frames of non-effective signals generated when the paired frames are subjected to frame comb filtering are alternately discarded. Although it can be done after frame comb filtering, it must be before the symbol decision circuit. However, rate buffering is preferably performed after the symbol is determined, since then the frame storage memory only needs to be one bit instead of many bits. Before error correction decoding, it is desirable to perform rate buffering simultaneously with deinterleaving. This is because there is no need to provide a separate frame storage memory for rate buffering. If rate buffering is performed separately from deinterleaving, a read-only port supplied by a shift register (with serial stages that can be loaded in parallel one row at a time from the ram portion accessed via the read / write port) , The rate buffering can be performed using only one frame storage memory.

FIG. 15 shows a general single loop sigma described by Leslie and Singh.
1 shows a delta converter 200. This converter can be used in any of the digital signal receivers of FIGS. The sigma-delta converter 200 is configured using a flash converter 201 having an 8-bit resolution as a basic converter. Most significant bit (ie, sign bit) of the digital output signal of flash converter 201
This bit is applied to a bit latch 203 as a digital feedback signal. The contents of bit latch 203 are converted to a positive or negative analog voltage level by digital-to-analog converter 204 to generate an analog feedback signal. The analog subtractor 205 subtracts this analog feedback signal from the input signal supplied to the input terminal 206 of the sigma-delta converter 200 and sampled and input to the subtractor 205 by a sampling switch (or sampler) 207. The difference output signal from the subtractor 205 is an analog error signal. The analog adder 208 adds its own sum output signal (delayed by the sample time by the sample and hold circuit 209) to the analog error signal,
A sum output signal is generated from the analog adder 208. The sum output signal from the analog adder 208 is a one-time integration of the analog error signal with respect to time, and this integrated response is digitized by the flash converter 201. Digital-analog converter 204, analog subtractor 20
5. It is advantageous if the sampler 207, the analog adder 208 and the sample and hold circuit 209 are configured in a capacitor switching circuit.

The errors generated by the use of single bit feedback are compensated in a manner as proposed by Leslie and Singh. Wired taking 202 of the most significant bit (ie, sign bit) of the digital output signal of flash converter 201
Involves a wired zero extension 213 through the lower bit positions to generate an 8-bit reduced number for a digital subtractor 214 that receives the complete 8-bit digital output signal of the flash converter 201 as the minuend input signal. The difference output signal from the subtractor 214 is delayed by a sample time in an 8-bit latch parallel battery 215, applied to a digital adder 218, and generates a 9-bit sum signal supplied to a low-pass storage filter 219. The response of the accumulation filter 219 is
The signal is subsampled at a symbol rate by 20 and input to an output terminal 221 of the sigma-delta converter 200.

FIG. 16 shows a generalized double-loop sigma-delta converter 300 described by Leslie and Singh. This converter can be used in any of the digital signal receivers shown in FIGS. 5 to 8, and includes an 8-bit resolution flash converter 301 as a basic converter. Flash converter 301
Is provided with a wired taking 302 of the most significant bit (i.e., sign bit) of the digital output signal, which is applied to a bit latch 303 as a digital feedback signal. Bit latch 303
Is converted to a positive or negative analog voltage level by a digital-to-analog converter 304 to generate an analog feedback signal. Analog subtractor 305
Is supplied to an input terminal 306 of the sigma-delta converter 300 and is supplied to a sampling switch (or sampler) 3.
07, the analog feedback signal is subtracted from the input signal sampled and input to the subtractor 305.
The difference output signal from the subtractor 305 is an analog error signal. The analog adder 308 adds its own sum output signal (delayed by the sample time by the sample and hold circuit 309) to the analog error signal, and generates a sum output signal from the analog adder 308.
The sum output signal from the analog adder 308 is a one-time integration of the analog error signal with respect to time, and this one-time integration response is supplied as a subtracted signal to an analog subtractor 310 that receives an analog feedback signal as a subtracted signal. The analog adder 311 adds its own sum output signal (delayed by the sample time by the sample and hold circuit 312) to the integrated analog error signal, and generates a sum output signal from the analog adder 311. The sum output signal from the analog adder 311 is twice integrated with respect to time of the analog error signal, and the twice integrated response is digitized by the flash converter 301. The digital-to-analog converter 304, analog subtractors 305 and 310, sampler 307, analog adders 308 and 311, and sample and hold circuits 309 and 312 are advantageously configured in a capacitor switching circuit.

The errors generated by the use of single bit feedback are compensated in a manner as proposed by Leslie and Singh. Wired taking 302 of the most significant bit (ie, sign bit) of the digital output signal of flash converter 301
Involves a wired zero extension 313 through the lower bit positions to generate an 8-bit reduced number for the digital subtractor 314 which receives the full 8-bit digital output signal of the flash converter 301 as the minuend input signal. The difference output signal from the subtractor 314 is delayed by the sample time in the 8-bit latch parallel battery 315, and further delayed by the sample time in the 8-bit latch parallel battery 316. The digital output signal of the flash converter 301, the contents of the 8-bit latch parallel battery 315 (doubled by the wired single bit position shift 317), and the contents of the 8-bit latch parallel battery 316 are converted by the digital adder 318. Generate a 10-bit sum signal that is added to each other and supplied to the low-pass accumulation filter 319. The response of storage filter 319 is subsampled at the symbol rate by subsampler 320 and input to output terminal 321 of sigma-delta converter 300.

Having described the preferred embodiment of the present invention, which is presently preferred by the inventor, those skilled in the art of communication system, transmitter and receiver design will appreciate, based on the above disclosure, the present invention. Many alternative embodiments could be designed. This must be kept in mind when interpreting the claims that accompany the specification.

[Brief description of the drawings]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a television transmitter for transmitting a television signal in which a digital signal is embedded as described in 08/141 070. FIG.

FIG. 2 shows US patent application no. FIG. 2 is a schematic diagram of a partial response filter that can be used in the transmitter of FIG. 1 as described in 08/141 070.

FIG. 3 shows US patent application no. FIG. 2 is a schematic diagram of another partial response filter that can be used in the transmitter of FIG. 1 as described in 08/141 070.

4 is a schematic diagram illustrating in detail a portion of the television transmitter of FIG. 1 that digitally filters digital data from which a phase-shift keying signal that modulates a suppressed quadrature video carrier is digitally filtered.

FIG. 5 is a schematic diagram of a digital signal receiver according to an embodiment of the present invention, which receives a television signal in which a digital signal is embedded and extracts the embedded digital signal.

FIG. 6 is a schematic diagram of a digital signal receiver according to an embodiment of the present invention, which receives a television signal in which a digital signal is embedded and extracts the embedded digital signal.

FIG. 7 is a schematic diagram of a digital signal receiver according to an embodiment of the present invention, which receives a television signal in which a digital signal is embedded and extracts the embedded digital signal.

FIG. 8 is a schematic diagram of a digital signal receiver according to an embodiment of the present invention, which receives a television signal in which a digital signal is embedded and extracts the embedded digital signal.

FIG. 9 shows in detail one form that can be taken by a high-pass comb filter used in the digital signal receiver of the present invention.

FIG. 10 is a diagram illustrating in detail another form that the high-pass comb filter used in the digital signal receiver of the present invention can take.

FIG. 11 is a diagram illustrating in detail one possible form of a cascade connection of high-pass comb filters used in the digital signal receiver of the present invention.

FIG. 12 is a diagram showing in detail one possible form of a cascade connection of high-pass comb filters used in the digital signal receiver of the present invention.

FIG. 13 shows US patent application no. FIG. 8 is a schematic diagram of a rate buffer that can be used in the portion of the television transmitter of FIG. 1 shown in FIG. 4 and operates as an interleaver, as described in 08/141 070.

FIG. 14 is a schematic diagram of a rate buffer that can be used in any of the digital signal receivers of FIGS. 5-8 and operates as a deinterleaver.

FIG. 15 is a schematic diagram of a single loop sigma-delta converter that can be used in any of the digital signal receivers of FIGS. 5-8 in accordance with the present invention.

FIG. 16 is a schematic diagram of a dual-loop sigma-delta converter that can be used in any of the digital signal receivers of FIGS. 5-8 in accordance with the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Television transmitter 2 Signal source 3 Audio processing circuit 4 Audio carrier transmitter 5 Multiplexer 6 Transmission antenna 7 Signal source 8 Transmitter 9 Station synchronization generator 10 Control connection 11 Time division multiplexer 12 VSB AM transmitter 13 Signal source 14 Error correction Encoder 15 frame repeater 16 partial response filter 17 DAC 18 deviation shaping filter 20 rate buffer 21 frame storage memory 22 frame storage packing control circuit 23 modulo 2 data frame counter 24 data row counter 25 symbol counter 30 symbol clocking circuit 31 voltage Controlled oscillator (VCO) 32 Zero crossing detector 33 255 count decoder 34 Automatic frequency phase control (AFPC) detector 35 AND gate 36 2-input A D gate 37 Digital signal receiver 38 Digital signal receiver 39 Digital signal receiver 40 Digital signal receiver 42 Antenna 43 Tutor 44 Video intermediate frequency (IF) filter 45 Intermediate frequency (IF) amplifier 46 In-phase synchronous video detector 47 Quadrature Synchronous Video Detector 48 Oscillator 49 Shift Network 50 Horizontal Sync Separator 51 Vertical Sync Separator 52 Symbol Counter 55 Decoder 56 AFPC 57 Control Delay Line 58 Matching Filter 61 Reconstructor 67 Pulse Phase Discriminator 68 Threshold Detection Device 69 2-input AND gate 70 modulo 2 data frame counter 71 data row counter 72 high-pass frame comb filter 73 digital subtractor 74 frame storage 75 symbol decision circuit 76 symbol decision circuit 77 rate buffer 78 Error correction encoder 80 Data frame pair counter 81 Data frame storage random access memory 82 Data frame storage random access memory 83 Address multiplexer 84 Data row counter 85 Symbol counter per column 86 Triggered flip-flop 87 Decoder 88 Two-input OR Circuit 89 3-input AND gate 90 Data frame pair counter 91 Data frame storage random access memory 92 Data frame storage random access memory 93 Address multiplexer 94 Data column counter 95 Symbol counter per column 96 Triggered flip-flop 97 Decoder 98 2-input OR Circuit 99 3-input AND gate 101 2-input AND gate 103 Symbol counter per sample 10 4 Zero Crossing Detector 105 Voltage Controlled Oscillator 106 ADC 107 Line 108 Line 109 Single Bit ADC 110 Bit Latch 111 Exclusive OR Gate 120 High Pass Line Comb Filter 123 Differential Input Amplifier 124 Output Terminal 125 Analog Delay Line 126 Multiplexer 127 High Pass Line Comb filter 128 multiplexer 129 1-H analog delay line 130 high-pass line comb filter 131 high-pass line comb filter 137 high-pass line comb filter 160 partial response filter 161 input terminal 162 2-input exclusive-OR (XOR) gate 163 output terminal 164 digital delay Line 165 multiplexer 166 partial response filter 167 two-input exclusive OR gate 168 Digital delay line 169 multiplexer 200 single loop sigma-delta converter 201 flash converter 202 wired taking 203 bit latch 204 DAC 205 analog subtractor 206 input terminal 207 sampling switch 208 analog adder 209 sample and hold circuit 213 wired zero extension 214 digital Subtractor 215 Parallel battery 218 Digital adder 219 Low pass storage filter 271 Line 300 Double loop sigma-delta converter 301 Flash converter 302 Wire taking 303 Bit latch 304 DAC 305 Analog subtractor 306 Input terminal 307 Sampling switch 308 Analog adder 309 Sample and hold circuit 310 Subtractor 311 Analog adder 313 Wired zero extension 314 Digital subtractor 315 Parallel battery 316 Parallel battery 317 Wired single bit position shift 318 Digital adder 319 Low-pass accumulation filter 320 Subsampler 321 Output terminal 761 Absolute value circuit 762 Double threshold Threshold detector

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Allen Leroy Limberg New Jersey USA 08551 Hart Lane Lingers 22 (56) References JP-A-5-207401 (JP, A) (58) Fields studied (Int. . ⁶ , DB name) H04N 7/08

Claims (50)

(57) [Claims] In a transmission combined with a video carrier whose amplitude is modulated according to a composite video signal, digital symbols are serialized in a binary phase shift keying modulation sideband of a suppressed carrier in quadrature with said video carrier. a digital signal receiver for use with a system for transmitting: not a necessary detection response in response to a transmission combined the
Providing an analog detection response comprising a desired detection response and detecting binary phase shift keying of said suppressed carrier, thereby comprising said unwanted detector comprising a residue of a composite video signal detected from an amplitude modulated video carrier. A detection device for generating the desired detector response with a response; and a sigma-delta analog for digitizing the analog detection response to provide a digitized detection response.
Wherein the more becomes possible with digital comb filter rather generates the lie Yi to the required detection response response from said digitized detection response receiving the unwanted detection <br/> out response; digital converter and Digital signal receiver. 2. The digital signal receiver according to claim 1, wherein said digital comb filter is a high-pass digital frame comb filter. 3. The sigma-delta analog-to-digital converter comprises: a subtracted input connection for receiving the analog detection response, a reduced input connection for receiving an analog feedback signal, and a difference between the detection response and the analog feedback signal. An analog subtractor having an output connection for providing an analog error signal proportional to: an means for integrating the analog error signal at least once in time; and after integrating the analog error signal at least once in time. A flash converter for converting digital samples of a plurality of bits into digital samples; a digital-analog converter for receiving the most significant bit of each of the digital samples as a digital feedback signal and converting it to the analog feedback signal; Signal Means for correcting the digital samples to compensate for being a single bit, thereby generating a corrected digital sample; and a predetermined sub-sampling period for generating a sample of the digitized detection response. 3. A digital signal receiver as claimed in claim 2, further comprising means for performing a weighted accumulation of the corrected digital samples over a period of time. 4. The digital signal receiver according to claim 1, wherein said digital comb filter is a high-pass digital line comb filter. 5. A sigma-delta analog-to-digital converter comprising: a minuend input connection for receiving the analog detection response; a subtraction input connection for receiving an analog feedback signal; An analog subtractor having an output connection for providing an analog error signal proportional to the difference between; and means for integrating the analog error signal at least once in time; And a digital-to-analog converter that receives the most significant bit of each of the digital samples as a digital feedback signal and converts it to the analog feedback signal. The digital feed; Means for correcting the digital samples to compensate for the back signal being a single bit, thereby generating corrected digital samples; and a predetermined sub-sampling to generate a digitized detection response. 5. The digital signal receiver according to claim 4, further comprising means for performing a weighted accumulation of said corrected digital samples over a period of time. 6. The digital signal receiver according to claim 1, wherein said digital comb filter is a high-pass digital frame comb filter followed by a high-pass digital line comb filter. 7. A sigma-delta analog-to-digital converter comprising: a subtracted input connection for receiving the analog detection response, a reduced input connection for receiving an analog feedback signal, and a difference between the detection response and the analog feedback signal. An analog subtractor having an output connection for providing an analog error signal proportional to the analog error signal; means for temporally integrating the analog error signal at least once; and integrating the analog error signal at least once in time. And a digital-to-analog converter that receives the most significant bit of each of the digital samples as a digital feedback signal and converts it to the analog feedback signal; and Digital feedback Means for correcting said digital samples to compensate for the fact that the signal is a single bit, thereby generating corrected digital samples;
7. The digital signal receiver according to claim 6, further comprising means for performing a weighted accumulation of said corrected digital samples over a predetermined sub-sampling period to generate a digitized detection response. 8. The apparatus according to claim 6, further comprising a symbol decision circuit for receiving a response from said high-pass digital line comb filter and for determining the identity of each digital symbol to generate a bit serial digital signal response. A digital signal receiver as described. 9. The digital signal receiver according to claim 1, wherein the digital comb filter is a high-pass digital line comb filter followed by a high-pass digital frame comb filter. 10. The sigma-delta analog-to-digital converter comprises: a minuend input connection for receiving the analog detection response;
An analog subtractor having a subtraction input connection for receiving an analog feedback signal and an output connection for providing an analog error signal proportional to a difference between the detection response and the analog feedback signal; Means for integrating at least once in time ; a flash converter for converting the analog error signal into a digital sample with a multi-bit resolution after integrating for at least one response time; A digital-to-analog converter for receiving the upper bits as a digital feedback signal and converting it to the analog feedback signal; and correcting the digital samples to compensate for the digital feedback signal to be a single bit; correction Means for generating a digitized detection response; means for performing a weighted accumulation of the corrected digital samples over a predetermined sub-sampling period to generate a digitized detection response. The digital signal receiver according to claim 9. 11. The apparatus according to claim 9, further comprising a symbol decision circuit for receiving a response from said high-pass digital frame comb filter and for determining the identity of each digital symbol to generate a bit serial digital signal response. A digital signal receiver as described. 12. In a transmission combined with a video carrier whose amplitude is modulated according to a composite video signal, the digital signal is serialized in a binary phase shift keying modulation sideband of a suppressed carrier in quadrature with said video carrier. A digital signal receiver for use with a transmitting system, comprising: providing an analog detection response in response to the combined transmission, detecting binary phase shift keying of the suppressed carrier, and thereby modulating amplitude. A detection device for generating a required detector response with an unwanted detector response comprising the remainder of the composite video signal detected from the video carrier; and a sigma for converting the analog detection response into a digitized detection response. A delta analog-to-digital converter; receiving the digitized detection signal response; A cascade connection of an bypass digital line comb filter and a high-pass digital frame comb filter connected to provide a combined comb filter response provided from a cascade having a plurality of levels of response to digital symbols; A digital signal receiver for determining the identity of each digital symbol to generate a bit digital serial response in response to the comb filter response. 13. The high-pass digital frame comb filters precede the digital line comb filters in their cascade connection: an input connection of the high-pass digital frame comb filter that receives the digitized detection response; An output connection of the high-pass digital frame comb filter that supplies a frame comb filter response as its input signal to the high-pass digital line comb filter;
A one-frame digital delay line for delaying the digitized detection response received at the input connection of the high-pass digital frame comb filter at a time interval equal to a period of frame scanning of the composite video signal; the first one-frame digital delay A first input connection for receiving a delayed response from the line, a second input connection connected with substantially no delay from an input connection of the high-pass digital frame comb filter, and a first and second input connection. 2. A digital subtractor having an output connection for providing a differential response to a signal to an output connection of said digital frame comb filter.
2. The digital signal receiver according to 2. 14. The digital signal receiver according to claim 13, wherein said one frame delay line is a random access memory operating in an overwrite mode after writing. 15. The high-pass digital line comb filter comprising: an input connection of the high-pass digital line comb filter that receives the high-pass digital line comb filter response; and a high-pass digital line comb filter that provides the combined comb filter response. An output connection; a 1-H digital delay line for delaying the high-pass digital frame comb filter response received at an input connection of the high-pass digital line comb filter at a time interval equal to a horizontal scan line period of the composite video signal; A first input connection for receiving a delayed response from a first 1-H digital delay line, a second input connection connected with substantially no delay from an input connection of the high-pass digital line comb filter, and In the first and second input connections 14. A digital signal receiver as claimed in claim 13, further comprising a second digital subtractor having an output connection for providing a differential response to said signal to an output connection of said high-pass digital line comb filter. 16. The symbol decision circuit comprising: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for providing a modified response; An input connection for receiving the modified response and an output connection for supplying a bit of the digital signal, each bit being the first response of the modified response.
16. The digital signal receiver of claim 15 further comprising a threshold detector in a first state above a threshold level and a modified response in a second state not above the first threshold level. vessel. 17. The high-pass digital line comb filter, the input connection of the high-pass digital line comb filter receiving the high-pass digital frame comb filter response; and the high-pass digital line comb filter providing the combined comb filter response. An output connection; a first 1-H delaying the high-pass digital frame comb filter response received at the input connection of the high-pass digital line comb filter at a time interval equal to a horizontal scan line period of the composite video signal.
A first input connection for receiving a delayed response from the first 1-H digital delay line; and a second input line connected with substantially no delay from the input connection of the high-pass digital line comb filter. Input connection and the first
A second digital subtractor having an output connection for providing a differential response to the signal at the second input connection; and a second digital subtracter for delaying the differential response of the second digital subtractor at a time interval equal to period 1-H. Two 1-H digital delay lines; a first input connection for receiving a delayed response from the second 1-H digital delay line; and a second input connected with substantially no delay from the input connection. Connection, first and second
14. A digital signal receiver according to claim 13, further comprising a third digital subtractor having an output connection for providing a differential response to the signal at the input connection of the digital line comb to the output connection of the digital line comb filter. 18. The symbol decision circuit comprising: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for providing a modified response; An input connection for receiving the modified response and an output connection for supplying a bit of the digital signal, each bit having a second value above which the modified response exceeds a first threshold level but is higher than the first threshold level. In a first state, wherein the modified response does not exceed the first threshold level or exceeds both the first and second threshold levels. The digital signal receiver according to claim 17, further comprising a double threshold detector. 19. The high-pass digital frame comb filters are subsequent to the digital line comb filters in their cascade connection: an input connection of the high-pass digital frame comb filter receiving the high-pass digital line comb response; An output connection of the high-pass digital frame comb filter for providing a filtered comb filter response; and the high-pass digital line comb filter received at the input connection of the high-pass digital frame comb filter at a time interval equal to the period of frame scanning of the composite video signal. A one-frame digital delay line to delay the response from
A first input connection receiving a delayed response from the first one-frame digital delay line, a second input connection connected with substantially no delay from an input connection of the high-pass digital frame comb filter, 13. A digital signal as claimed in claim 12, comprising a first digital subtractor having an output connection for providing a differential response to the signal at the first and second input connections to an output connection of the digital frame comb filter. Receiver. 20. The digital signal receiver according to claim 19, wherein said one frame delay line is a random access memory operating in an overwrite mode after writing. 21. The high-pass digital line comb filter comprising: an input connection of the high-pass digital line comb filter that receives the digitized detector response; and a high-pass digital line comb filter to an input connection of the high-pass digital frame comb filter. filter output connection and; 1 for delaying the composite video signal wherein the highpass digital line input connection required detector response with unwanted detector response that receive in the comb filter at equal time intervals during the horizontal scanning lines of A first input connection for receiving a delayed response from the first 1-H digital delay line; and a substantially no delay from the input connection of the high-pass digital line comb filter. A second input connection and a signal at the first and second input connections. Digital signal receiver according to claim 19, wherein the the more the second digital subtractor having an output connection for supplying a differential response to the output connection of said highpass digital line-comb filter for. 22. The symbol decision circuit comprising: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for providing a modified response; An input connection for receiving the modified response and an output connection for supplying a bit of the digital signal, each bit being the first response of the modified response.
22. The digital signal reception of claim 21 further comprising a threshold detector in a first state exceeding a first threshold level and the modified response in a second state not exceeding the first threshold level. vessel. 23. The high-pass digital line comb filter: an input connection of the high-pass digital line comb filter receiving the subsampler response; an output connection of the high-pass digital line comb filter to an input connection of the high-pass digital frame comb filter. A first 1- delaying a required output response with an unwanted detector response received at the input connection of the high-pass digital line comb filter at a time interval equal to the horizontal scan line period 1-H of the composite video signal; An H digital delay line; a first input connection receiving a delayed response from the first 1-H digital delay line; and a second input connection connected with substantially no delay from the input connection of the high-pass digital line comb filter. 2 and the signals at the first and second input connections. A second digital subtractor having an output connection for providing a differential response to the second digital subtractor; a second 1-H digital delay line for delaying the differential response of said second digital subtractor for a time interval equal to period 1-H. A first input connection for receiving a delayed response from the second 1-H digital delay line, and a second input connection with substantially no delay from the output connection of the second digital subtractor.
And a third digital subtractor having an output connection for providing a differential response to signals at the first and second input connections to an output connection of the digital line comb filter. Item 14. A digital signal receiver according to Item 13. 24. The symbol decision circuit comprising: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for providing a modified response; An input connection for receiving the modified response and an output connection for supplying a bit of the digital signal, each bit having a second value above which the modified response exceeds a first threshold level but is higher than the first threshold level. In a first state, wherein the modified response does not exceed the first threshold level or exceeds both the first and second threshold levels. The digital signal receiver according to claim 23, further comprising a double threshold detector. 25. A digital signal receiver for use in a system for transmitting a binary phase shift keying modulation sideband of a suppressed carrier in quadrature with a video carrier whose amplitude is modulated according to a composite video signal. a is: an intermediate frequency signal response amplitude modulation video carrier and the tuner to provide the non-Sensing No. that is become more selective as binary phase polarized moved keyed suppressed carrier; wherein the filtering and amplification components were amplified An intermediate frequency amplifier for the intermediate frequency signal response, providing an intermediate frequency amplifier response; and generating an in-phase and quadrature-phase intermediate frequency video carrier at the intermediate frequency and an average phase controlled by the frequency and phase error signals. A controlled oscillator circuit for receiving the amplified intermediate frequency amplifier response, and receiving and supplying the amplified intermediate frequency amplifier response. An in-phase video detector for synchronously detecting a composite video signal therefrom in response to the carrier; and receiving the amplified intermediate frequency amplifier response and responding to the supplied quadrature intermediate frequency video carrier in response to the supplied frequency and phase. A quadrature video detector for synchronously detecting a binary phase shift keying signal with the quadrature video detector response from the quadrature video detector from a portion of the composite video signal including an error signal; A horizontal sync separator for separating a horizontal sync pulse from the composite video signal detected by the in-phase video detector; and generating clocking oscillation at a frequency and a phase controlled by the separated horizontal sync pulse. 2 above
A second controlled oscillator circuit, which is a multiple of the symbol rate for the binary phase shift keying signal; an input connection for receiving the quadrature phase detection signal; and a digitized response of the binary phase shift keying signal. Providing a quadrature video detector response as a sampled response to the clocking oscillation at a symbol rate for the sigma-delta analog-to-digital converter; and a symbol for the binary phase shift keying signal. Receiving a digitized quadrature detector response supplied at a rate, wherein a digital comb filter response in which the response to the accompanying portion of the composite video signal is suppressed is converted to the binary phase shift keying signal. Providing a digital comb filter; receiving the digital comb filter response and receiving the binary phase shift key; Digital signal receiver, characterized in that the more a symbol decision circuit for determining the symbols to be transmitted by the ring signal. 26. The sigma-delta analog-to-digital converter comprises: a first input connection for receiving the analog detector response, a second input connection for receiving an analog feedback signal, and the detector A differential output amplifier having an output connection for providing an analog error signal proportional to the difference between the response and the analog feedback signal; and converting the analog error signal to a sample of a digital error signal at a multi-bit resolution. A flash converter; receiving the most significant bit of the digital error signal as a digital feedback signal;
A digital-to-analog converter that converts it to the analog feedback signal; and a weighted accumulation of the corrected digital error signal samples over a predetermined sub-sampling period to generate samples of the digitized detector response. 26. The digital signal receiver according to claim 25, further comprising means for performing: 27. The digital signal receiver according to claim 25, wherein the digital comb filter has a cascade connection of a high-pass digital frame comb filter followed by a high-pass digital line comb filter. 28. The high-pass digital frame comb filter comprising: an input connection of the high-pass digital frame comb filter that receives samples of the digitized response to the quadrature video detector samples at the symbol rate; An output connection of the high-pass digital frame comb filter that supplies a frame comb filter response as its input signal to the high-pass digital line comb filter; A one-frame digital delay line for delaying the subsampler response received at an input connection; a first input connection for receiving a delayed response from the first one-frame digital delay line; A second input connection connected without substantial delay from the input connection of the frame comb filter;
The digital digital subtractor of claim 27, further comprising a first digital subtractor having an output connection for providing a differential response to the signal at the first and second input connections to an output connection of the digital frame comb filter. Signal receiver. 29. The high-pass digital line comb filter comprising: an input connection of the high-pass digital line comb filter that receives the high-pass digital line comb filter response; and an input connection of the high-pass digital line comb filter that provides the combined comb filter response. An output connection; a 1-H delay line for delaying the high-pass digital frame comb filter response received at an input connection of the high-pass digital line comb filter at a time interval equal to a horizontal scan line period of the composite video signal; A first input connection for receiving a delayed response from the 1-H digital delay line, a second input connection connected with substantially no delay from the input connection of the high-pass digital line comb filter, and a first input connection. And the signal at the second input connection 29. A digital signal receiver according to claim 28, further comprising a second digital subtractor having an output connection for providing a differential response to the output connection of said high-pass digital line comb filter. 30. The symbol decision circuit comprising: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for providing a modified response; An input connection for receiving the modified response and an output connection for supplying a bit of the digital signal, each bit being the first response of the modified response.
30. The digital signal reception of claim 29, further comprising a threshold detector in a first state above a threshold level and a modified detector in a second state where the modified response does not exceed the first threshold level. vessel. 31. An output signal bit provided from an output connection of said symbol determination circuit is provided at a symbol rate: a vertical sync separator for separating a vertical sync pulse from a composite video signal detected by said in-phase video detector. ;
A data frame counter for counting the separated vertical sync pulses that occur when the symbols per row are not within the intermediate row range, thereby generating a data frame count; and an input for receiving bits from an output connection of the symbol decision circuit. Having a connection, receiving said bits only when said data frame count modulo 2 has a predetermined one of two values, and supplying said symbol decision circuit output signal bits in a predetermined order at a half symbol rate 30. The digital signal receiver according to claim 29, further comprising a rate buffer having an output connection for receiving the signal. 32. The rate buffer operates as a deinterleaver to supply the symbol decision circuit output signal bits at a half symbol rate to an error correction decoder in the order of each data stream. 32. The digital signal receiver according to item 31, 33. Each of said separate clocks for counting said symbol clocking oscillations, thereby generating a symbol count per row, and resetting said symbol count to a predetermined base count value for said symbol count. A per-row symbol counter responsive to the set horizontal sync pulse;
Counting each time the per-row symbol counter is reset, thereby generating a data row count and resetting each of the separations to reset the data row count to a predetermined base count value for the data row count. A data row counter responsive to the applied vertical sync pulse; and at individual times by bits from the output connection of the sibol determination circuit only when the data frame count modulo 2 has the predetermined one of two values. At least one random access memory included in the rate buffer that is written and receives the data row count and the symbol count per row as write addresses together during the individual times. 32. The digital signal receiver according to claim 31. 34. The high-pass digital line comb filter comprising: an input connection of the high-pass digital line comb filter that receives the high-pass digital line comb filter response; and an input connection of the high-pass digital line comb filter that provides the combined comb filter response. An output connection; delaying the high-pass digital frame comb filter response received at the input connection of the high-pass digital line comb filter at a time interval equal to a period of a horizontal scan line of the composite video signal;
A first input connection for receiving a delayed response from the first 1-H digital delay line; and a second input connection connected with substantially no delay from the input connection of the high-pass digital line comb filter. A second digital subtractor having two input connections and an output connection providing a differential response to the signal at the first and second input connections of said second subtractor; a time interval equal to period 1-H. A second 1-H digital delay line for delaying the differential response of the second subtractor at a first input connection for receiving a delayed response from the first 1-H digital delay line; A second input connection connected with substantially no delay from an input connection of the digital line comb filter, and a differential response to signals at the first and second input connections, the differential response of the high-pass digital filter. Digital signal receiver according to claim 28, wherein the the more the third digital subtractor and an output connected to supply to the emission comb filter. 35. The symbol decision circuit comprising: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for providing a modified response; An input connection for receiving the modified response and an output connection for supplying a bit of the digital signal, each bit having a second value above which the modified response exceeds a first threshold level but is higher than the first threshold level. In a first state, wherein the modified response does not exceed the first threshold level or exceeds both the first and second threshold levels. 35. The digital signal receiver according to claim 34, further comprising a double threshold detector. 36. An output signal bit provided from an output connection of said symbol determination circuit is provided at a symbol rate: a vertical sync separator for separating a vertical sync pulse from a composite video signal detected by said in-phase video detector. ;
A data frame counter for counting the separated vertical sync pulses that occur when the symbols per row are not within the intermediate row range, thereby generating a data frame count; and an input for receiving bits from an output connection of the symbol decision circuit. Having a connection, receiving said bits only when said data frame count modulo 2 has a predetermined one of two values, and supplying said symbol decision circuit output signal bits in a predetermined order at a half symbol rate 35. The digital signal receiver according to claim 34, further comprising a rate buffer having an output connection for receiving. 37. The rate buffer operates as a deinterleaver to supply the symbol decision circuit output signal bits at a half symbol rate to an error correction decoder in the order of each data stream. A digital signal receiver according to claim 36. 38. Each of said separated clocks for counting said symbol clocking oscillations, thereby generating a symbol count per row, and resetting said symbol count to a predetermined base count value for said symbol count. A per-row symbol counter responsive to the set horizontal sync pulse;
Counting each time the per-row symbol counter is reset, thereby generating a data row count and resetting each of the separations to reset the data row count to a predetermined base count value for the data row count. A data row counter responsive to the applied vertical sync pulse; and at individual times by bits from the output connection of the sibol determination circuit only when the data frame count modulo 2 has the predetermined one of two values. At least one random access memory included in the rate buffer that is written and receives the data row count and the symbol count per row as write addresses together during the individual times. 37. The digital signal receiver according to claim 36. 39. The digital signal receiver according to claim 25, wherein the digital comb filter has a cascade connection of a high-pass digital line comb filter followed by a high-pass digital frame comb filter. 40. The high-pass digital frame comb filter includes: an input connection of the high-pass digital frame comb filter that receives the high-pass digital line comb response; an output of the high-pass digital frame comb filter that provides the combined comb filter response. A one-frame digital delay line for delaying a response from the high-pass digital line comb filter received at an input connection of the high-pass digital frame comb filter at a time interval equal to a period of frame scanning of the composite video signal; A first input connection for receiving a delayed response from one frame digital delay line, a second input connection connected with substantially no delay from the input connection of the high-pass digital frame comb filter, and a first and a second connection. Enter 2 40. The digital signal receiver of claim 39, further comprising a first digital subtractor having an output connection for providing a differential response to a signal at the force connection to an output connection of the digital frame comb filter. 41. The high-pass digital line comb filter comprising: an input connection of the high-pass digital line comb filter that receives the digitized detector response to the quadrature video detector samples at the symbol rate; unnecessary received at the composite video signal input connections at equal time intervals during the horizontal scanning lines before KIHA bypass digital line comb filter; the highpass digital line-comb filter output connection and to the input connection of the digital frame comb filter A 1-H digital delay for delaying a required detector response with a detector response; a first input connection for receiving a delayed response from the first 1-H digital delay line; and the high-pass digital line comb filter. Connected from the input connection without substantial delay. A second digital subtractor having a second input connection and an output connection for providing a differential response to signals at the first and second input connections to an output connection of the high-pass digital line comb filter. 41. The digital signal receiver according to claim 40. 42. The symbol determination circuit comprising: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for providing a modified response; An input connection for receiving the modified response and an output connection for supplying a bit of the digital signal, each bit being the first response of the modified response.
42. The digital signal reception of claim 41, further comprising a threshold detector in a first state above a threshold level and a modified state of the threshold response in a second state not above the first threshold level. vessel. 43. An output signal bit provided from an output connection of said symbol determination circuit is provided at a symbol rate: a vertical sync separator for separating a vertical sync pulse from a composite video signal detected by said in-phase video detector. ;
A data frame counter for counting the separated vertical sync pulses that occur when the symbols per row are not within the intermediate row range, thereby generating a data frame count; and an input for receiving bits from an output connection of the symbol decision circuit. Having a connection, receiving said bits only when said data frame count modulo 2 has a predetermined one of two values, and providing said symbol decision circuit output signal bits in a predetermined order at a half symbol rate 42. The digital signal receiver according to claim 41, further comprising a rate buffer having an output connection therefor. 44. The rate buffer operates as a deinterleaver to supply the symbol decision circuit output signal bits at a half symbol rate to an error correction decoder in the order of each data stream. 44. The digital signal receiver according to claim 43. 45. Each of said isolated clocks for counting said symbol clocking oscillations, thereby generating a symbol count per row, and resetting said symbol count to a predetermined base count value for said symbol count. A per-row symbol counter responsive to the set horizontal sync pulse;
Counting each time the per-row symbol counter is reset, thereby generating a data row count and resetting each of the separations to reset the data row count to a predetermined base count value for the data row count. A data row counter responsive to the applied vertical sync pulse; and at individual times by bits from the output connection of the cibol determination circuit only when the data frame count modulo 2 has the predetermined one of two values. At least one random access memory included in the rate buffer that is written and receives the data row count and the symbol count per row together as a write address during the individual times. 44. The digital signal receiver according to claim 43. 46. The high-pass digital line comb filter: an input connection of the high-pass digital line comb filter that receives at the symbol rate samples of the digitized response to the quadrature video detector samples; An output connection of the high-pass digital line comb filter to an input connection of the digital frame comb filter; no need to receive at the input connection of the high-pass digital line comb filter at a time interval equal to the horizontal scanning line period 1-H of the composite video signal. A first 1-H digital delay line for delaying a required detector response with an accurate detector response; and a first receiving a delayed response from said first 1-H digital delay line. Substantially from the input connection and the input connection of the high-pass digital line comb filter. A second digital subtractor having a second input connection connected without significant delay and an output connection providing a differential response to the signal at the first and second input connections; equal to period 1-H A second 1-H digital delay line for delaying the differential response of the second digital subtractor at a time interval; a first input connection for receiving a delayed response from the second 1-H digital delay line; , A second digital subtractor connected from the output connection of the second digital subtractor without substantial delay.
And a third digital subtractor having an output connection for providing a differential response to signals at the first and second input connections to an output connection of the digital line comb filter. Item 41. The digital signal receiver according to Item 40. 47. The symbol decision circuit comprising: an absolute value circuit having an input connection receiving the combined comb filter response and an output connection providing a modified response; An input connection for receiving the modified response and an output connection for supplying a bit of the digital signal, each bit having a second value above which the modified response exceeds a first threshold level but is higher than the first threshold level. In a first state, wherein the modified response does not exceed the first threshold level or exceeds both the first and second threshold levels. 47. The digital signal receiver according to claim 46, comprising a double threshold detector. 48. An output signal bit provided from an output connection of said symbol determination circuit is provided at a symbol rate: a vertical sync separator for separating a vertical sync pulse from a composite video signal detected by said in-phase video detector. ;
A data frame counter for counting the separated vertical sync pulses that occur when the symbols per row are not within the intermediate row range, thereby generating a data frame count; and an input for receiving bits from an output connection of the symbol decision circuit. Having a connection, receiving said bits only when said data frame count modulo 2 has a predetermined one of two values, and providing said symbol decision circuit output signal bits in a predetermined order at a half symbol rate 47. The digital signal receiver of claim 46, further comprising a rate buffer having an output connection therefor. 49. The rate buffer operates as a deinterleaver to supply the symbol decision circuit output signal bits at a half symbol rate to an error correction decoder in the order of each data stream. 49. A digital signal receiver according to item 48. 50. Each of the isolated clocks for counting the symbol clocking oscillations, thereby generating a symbol count per row, and resetting the symbol count to a predetermined base count for the symbol count. A per-row symbol counter responsive to the set horizontal sync pulse;
Counting each time the per-row symbol counter is reset, thereby generating a data row count and resetting each of the separations to reset the data row count to a predetermined base count value for the data row count. A data row counter responsive to the applied vertical sync pulse; and at individual times by bits from the output connection of the cibol determination circuit only when the data frame count modulo 2 has the predetermined one of two values. At least one random access memory included in the rate buffer that is written and receives the data row count and the symbol count per row together as a write address during the individual times. 49. The digital signal receiver according to claim 48.