KR0173693B1 - Receiver performing oversampling analog/digital conversion for digital signal inside tv signal - Google Patents

Abstract

Disclosed is a digital signal receiver for detecting a BPSK modulation of a suppressed carrier at right angles to an image modulated by a composite image signal. The detected BPSK is dedigitized using an 'oversampling' analog-to-digital converter before digital comb filtering to separate the BPSK from the residual composite picture signal. This is done to get an increased number of bit resolutions from relatively inexpensive flash converters.

Description

Receiver Oversampling Analog-to-Digital Conversion for Digital Signals in Television Signals

1 is an overall schematic diagram of a television transmitter for transmitting a television signal with a digital signal hidden therein, as described by both Jian.

2 and 3 are schematic diagrams of a part-response filter, either of which can be used in the television transmitter of FIG. 1, as described by both Jian.

4 is a schematic diagram detailing a portion of the television transmitter of FIG. 1 used to digitally filter digital data generating a phase-shift key signal that modulates a suppressed, quadrature-phase image carrier.

5 to 8 are schematic diagrams of respective digital signal receivers embodying the present invention for receiving a television signal with a digital signal hidden therein and extracting a hidden digital signal.

9 to 10 are schematic diagrams detailing one of the various forms that line-conb filtering in either the digital or signal receiver of either FIG. 5 or 6 may take.

11 through 12 are schematic diagrams showing in detail one of the various forms that line-com filtering in either the digital signal receiver of FIG. 7 or FIG. 8 may take.

FIG. 13 is a schematic diagram of a rate buffer operated as an interleaver, which may be used for a portion of the television transmitter of FIG. 1 shown in FIG. 4, as described by both Jian.

FIG. 14 is a schematic diagram of a rate buffer operated as a deinterleaver, which may be used in the digital-signal receivers of FIGS. 5-8, as in the digital signal receiver described by both jian.

The present invention relates to a receiver for recovering a digital signal hidden in an analog television signal.

Relatively small (e.g., 3 to 5 IRE) signals that encrypt digital information can be mixed with the composite picture signal without seldom appearing on the television screen resulting from the composite picture signal if appropriate restrictions on the digital signal format are observed. Yang Jian, US patent application Ser. No. 08 / 141,070, which is hereby incorporated by reference, discloses a system for doing this in an apparatus for processing an NTS television signal having a digital signal on a quadrature-phase image carrier. It describes. The inventions described in its patent application by both Jian, such as the inventions described herein, are assigned to Samsung Electronics in accordance with an existing employee agreement for the transfer of inventions made within the scope of employment. Both papers describe dual phase-shift-key (BPSK) modulation of a suppressed carrier at the same frequency and perpendicular to the image carrier. Both Jian advocates BPSK signals that are limited to a bandwidth of about 2 MHz to avoid crosstalk to the chroma in a TV receiver that separates luma and chroma without relying on comb filtering. Both papers show that it is better to pass the data transmitted through a partial-response filter to increase the correlation at corresponding points along successive horizontal scan lines in the composite image signal, which is equivalent to the PSK subcarriers. There is a foundation for using line-comb filtering in digital signal receivers to separate the light emitting portions of composite image signals. Yang Jian also insists on repeating the anti-phase of the BPSK's frames in consecutive frame pairs of NTSC television signals. The repetition of such data in the frame pair makes the composite picture signal detected from the NTSC television signal less visible in the picture generated from the composite picture signal for BPSK to view on the screen. Such repetition of data occurring in a frame pair also provides the basis for using frame-comb filtering in a digital signal receiver to separate the BPSK and the light emitting portion of the composite picture signal representing the static portion of a continuous television picture. do.

Both papers describe problems that occur in digital signal receivers when BPSK is digitized after detection, assuming that a flash converter, which is typically used to digitize composite image signals, is used. Residues of composite image signals of 750 Hz or more are accompanied by BPSK when BPSK is detected simultaneously, which can sometimes be relatively large compared to BPSK. If the digitalization takes place immediately after synchronous detection of the BPSK and the quantization noise of a flash converter with only a resolution of about 8 bits, the relatively small BPSK signal is inadequately decomposed, this large composite picture signal residue can cause the flash converter to It will occupy a large part of the area. Flash converters with around 12 bits can be made, but they are too expensive for use in high-volume electronics. Both Jian insist on using line-comb filtering of the BPSK signal before digitization, in order to reduce the relative size of the composite picture signal residue above 750 kHz with BPSK. The BPSK signal can then be resolved over a larger portion of the digital output range of the flash converter to reduce symbol errors.

Flash converters increase in price very rapidly as their bit resolution increases, but the price increase for bandwidth increases beyond the limit of 2 MHz for which both Jian claims the BPSK bandwidth is relatively moderate. The 2 MHz limitation on the BPSK bandwidth requires a 4 MHz sample rate in order for the maximum symbol rate to be sampled properly, and an 8-bit flash converter that can operate at 16, 32, or even 64 times the sample rate. They are reasonably priced. Thus, the inventor points out that the oversampling conversion method can be used to obtain an increased effective bit resolution from such an 8-bit flash converter. By oversampling at 16 times the 4 MHz sample rate, an effective resolution of about 12-bits can be obtained, so that even if the detected BPSK is relatively small compared to the composite picture signal occupying most of the same area of the flash converter, The detected BPSK can be digitized without being lost.

The present invention is embodied in a digital signal receiver for detecting BPSK modulation of a suppressed carrier orthogonal to an amplified-modulated image carrier by a composite image signal, wherein the detected BPSK is used to comb-filter BPSK from a residual composite image signal. Before it is digitalized. Preferably, the digitalization of the detected BPSK consists of an oversampling analog-digital changer.

Typically, equalization delays have been removed from the drawings to simplify the drawings and make them easier to understand. One of ordinary skill in the art of image signal processor design appropriately to time-align pixels or data that are affected by different delays on these different pathways due to different processes performed in different pathways. Will understand the need for such a delay. Those skilled in the art will understand where such delays are needed and how long each delay should be, so such delays will not be described below. In logic circuits, one of ordinary skill in the art knows how to provide the shimming delay required to overcome undesirable logic race conditions or compensate for potential delays in performing logic operations. As will be appreciated, a detailed description of the logic circuit design regarding providing seaming delay will not be discussed below. Furthermore, where analog-to-digital converters (ADCs) are shown or described herein, it would be desirable for one of ordinary skill in the art to precede such converters with an anti-aliasing low pass filter. We will not discuss further such as this can be understood as well as how it can be implemented. In addition, where a digital-to-analog converter (DAC) is shown or described herein, it is desirable for a person of ordinary skill in the art to add such a converter after a sample clock reject lowpass filter and how As we can see if it can be implemented, we will not discuss that further below.

FIG. 1 shows a television transmitter 1 for transmitting a television signal with a digital signal hidden therein. Source 2 supplies one or more analog audio signals to audio processing circuit 3. The audio processing circuit 3 supplies a modulated signal to an audio carrier transmitter 4 to modulate the frequency of the audio carrier. The audio processing circuit 3 includes the delay required to synchronize voice and picture. By convention, audio processing circuit 3 also includes a pre-emphasis network for analog audio signals and includes stereo and secondary audio programs (SAP) for inclusion in the modulated signal supplied to audio carrier transmitter 4. ) May include an apparatus for generating a subcarrier. Frequency modulated (FM) audio carriers are typically supplied from transmitter 4 to multiplexer 5 for frequency-multiplex transmission with in-phase VSB AM picture carriers and quadrature-phase VSB BPSK data carriers. In a television transmitter 1 for wireless broadcasting, the multiplexer 5 usually takes the form of an antenna combining circuit and the resulting frequency multiplexed signal is broadcast from the transmitting antenna 6. The television transmitter for the head end of the cable broadcast system would not have a transmit antenna 6 used for radio broadcasting. The multiplexer 5 has a different form, in which the frequency multiplexed signal from the channel under consideration is further frequency multiplexed with the signals multiplexed from the other channel, and the resulting signal is transmitted by a linear amplifier to the cable broadcasting system. Is applied with the trunk cable.

In FIG. 1, source 7 supplies an analog composite picture signal, which is the basis of the supplied modulated signal, to transmitter 8, and transmitter 8 supplies a VSB AM picture carrier to multiplexer 5, where a frequency modulated (FM) speech carrier and frequency -Allow multiple transmissions. The color burst of the vertical sync pulse, horizontal sync pulse and analog composite picture signal from source 7 is synchronized with the corresponding signal supplied by the station sync signal generator 9. The control connection 10 between the source 7 of the composite picture signal and the station synchronization generator 9 represents the means used for such synchronization. If source 7 is a remote generator of a composite video signal, such as a downtown studio or another television station networked with a local television station, the control connection 10 may be a genlock connection to station synchronization generator 9. If source 7 is a local camera, the local camera will receive synchronization information from station sync generator 9 via the control connection 10. Other synchronous designs, including those for video tape recorders and television movie apparatuses, are familiar to those of ordinary skill in the art. Typically, time-division multiplexer 11 converts sync block information, including vertical sync pulses, horizontal sync pulses, equalization pulses, color bursts and pedestals (commonly referred to as porches) into original sync block information. Is used to insert into the composite image signal applied as a modulation signal to the image carrier transmitter 8.

The television transmitter 1 of FIG. 1 is currently present in that another VSB AM transmitter 12 generates a binary phase-shift-key (VSB BPSK) suppressed carrier that is in phase with the VSC AM picture carrier for the residual sideband, NTSC composite picture signal. It is different from the transmitters used. This another VSB AM transmitter 12 may include a balanced balanced modulator for both carrier and BPSK modulated signals, receiving in-phase picture carriers from VSB AM transmitter 8 and feeding quadrature-phase picture carriers to the balance modulator. It may further comprise a 90 ° -phase-shift network. VSB BPSK signals received from transmitter 12, such as VSB AM picture carriers amplified-modulated by NTSC composite picture signals received from transmitter 8, are fed to multiplexer 5, where also frequency-modulated (FM) speech Frequency-multiplexed with carrier Source 13 supplies a digital signal in serial-bit form to error-correcting coder 14 for inserting an additional bit of error correction code in the form of serial-bit applied to frame iterator 15. Frame repeater 15 supplies each frame of data received as an input signal that is twice the output signal. The output signal from frame repeater 15 is fed to partial response filter 16, which inserts a correlation into the data at the corresponding points of the continuous horizontal scanning line. The digital response from the partial-response filter 16 is fed to a digital-to-analog converter (DAC) 17 for conversion to an analog key signal. The DAC 17 supplies a high frequency pre-emphasis and transition-shaping filter 18 with a keying signal that is a predetermined positive value corresponding to digital zero and a predetermined negative value corresponding to digital one. The predetermined sound level of the analog modulated signal has an absolute value equal to the predetermined positive level of the analog modulated signal. Filter 18 compensates for the loss in detection efficiency when simultaneously detecting VSB BPSK, due to the transmission being virtually single sideband. The response of filter 18 is the keying signal supplied to the balance modulator in transmitter 12, which also receives the quadrature image carrier being modulated. Transmitter 8, which supplies VSB AM picture carriers amplified-modulated by NTSC composite picture signals to multiplexer 5, to avoid incidental phase modulation that can interfere with quadrature-phase VSB BPSK suppressed carriers from transmitter 12. Carefully designed and operated. Since the quadrature-phase VSB AM carrier relative to the PSK is suppressed, the phase of the signal in which the VSB PSK and VSB AM are combined is not noticeably different from the phase of the in-phase VSB AM picture carrier. Although FIG. 1 shows transmitters 8 and 12 separated from one another, in practice the same upper sideband filter and final amplifier stages may be shared by transmitters 8 and 12.

2 illustrates one form 160 that partial response filter 16 may take. The serial-bit digital input signal is applied to the first input of the 2-input exclusive OR gate via input terminal 161, and the output of the 2-input XOR gate is connected to output terminal 163 and partially-responded therein. Supply the response of filter 160. The second input of the XOR gate 162 receives a delay response to the output signal from the multiplexer 165 applied to the write input connection of the digital delay line 164 from the read output connection of the digital delay line 164. Digital delay line 164, which can be implemented as a cyclic address line storage memory operated in a read-write repeat mode, provides a 1-H delay equal to the period of one television horizontal scan line. The multiplexer 165 is connected to the write input connection of the digital delay line 164 except when the last row decoding result supplied as a control signal to the multiplexer 165 is 1, which indicates that the last data row of the data frame is being fed to the partial-response filter 160. Select the response of the partial-response filter 160 at output terminal 163 to apply it to.

When the last row decoding result supplied as a control signal to the multiplexer 165 is 1, which indicates that the last data row of the data frame is being supplied to the partial-response filter 160, the multiplexer 165 sets the modulo-2 data frame count to a digital delay line. Applies to 164 write input connections. When the modulo-2 data frame count so applied is zero during the last row of the last frame of a pair of frames, a series of zeros are written to the digital delay line 164 to allow the data for the first data row of the next pair of frames. Passes through the partial-response filter 160 without change. However, when the modulo-2 data frame count selected by the multiplexer 165 to apply to the write input connection of the digital delay line 164 is 1 during the last row of the first frame of the pair of data frames, a series of ones are digital delay lines. Written in 164, during the first data row of the last frame in the pair of data frames, the data passes through the partial-response filter 160 to be one's complement. This causes the next data row of the last frame in the data frame pair to be one's complement of the corresponding data row of the first frame preceding the data frame pair.

The digital filtering provided by the partial-response filter 160 is performed on the analog signal generated by converting the digital response 0s and 1s at the output terminal 163 with +1 and -1 amplification of the keying signal, which is a signal for controlling the generation of BPSK signals. Suppresses the DC term. This digital filtering shows the peak of the response at multiples of the hole at 1/2 horizontal-scan-line frequency f _H and the response is zero at multiples of horizontal-scan-line frequency f _H. This digital filtering allows the PSK signal for the data to have a comb-like frequency spectrum that complements the frequency spectrum of the comb-like emission signal. The luminescent signal shows a response of zero at an odd multiple of 1/2 the horizontal-scan-line frequency f _H and a peak of the response at a multiple of the horizontal-scan-line frequency f _H. Partial-response filter 160 will share the spectrum of the PSK, passing through a 2-tap highpass line-comb filter with a single 1H delay line and subtractor. Such a highpass line-comb filter may be placed in a digital signal receiver to suppress a light emitting signal having a favorable correlation between vertically arranged pixels and reduce it to a jamming signal for the PSK.

3 shows another form 166 that part-response filter 16 may take, which includes a final filtering comprising the same elements 162-165 as part-response filter 160. The partial-response filter 166 further includes an initial filtering unit similar to its final filtering unit. This first filtering part has a two-input exclusive OR gate 167, where the first input of the gate 167 is connected to the input terminal 161, and the output of the gate 167 is input terminal 161 as in the partial-response filter 160 of FIG. Rather, it is connected to the first input of the XOR gate 162. The second input of the XOR gate 167 receives a delay response to the output signal from the multiplexer 169 applied from the read output connection of the digital delay line 168 to the write input connection of the digital delay line 168. Digital delay line 168 provides 1H equal to the period of one television horizontal scan line, such as digital delay line 164. The multiplexer 169 is write input of the digital delay line 168 except when the last row decoding result supplied as a control signal to the multiplexer 169 is 1, indicating that the last data row of the data frame is being fed to the partial-response filter 166. Select the response of XOR gate 167 to apply to the connection.

When the last row decoding result supplied as a control signal to multiplexer 169 is 1, indicating that the last data row is being fed to partial-response filter 166, multiplexer 169 connects wired 0 to the write input connection of digital delay line 164. To apply. This writes a series of zeros to the digital delay line 164 during the first row of each data frame. This series of zeros is fed to the XOR gate 167 during the first row of the next data frame such that the first row of data is replaced by an XOR gate 167 for selective complementation as described for the partial-response filter 160 of FIG. It is passed to the XOR gate 162.

The partial-response filter 166 has a sharper-toothbrush shaped comb response than the partial-response filter 160 but also exhibits a zero response at odd multiples of the 1/2 horizontal-scan-line frequency f _H and a horizontal-scan- The peak of the reaction is shown at multiples of the line frequency f _H. In a digital signal receiver, a three-tap highpass line-comb filter can be used to recover the PSK signal to the planar frequency spectrum and reduce the luminescent signal, which is a jamming signal for the PSK.

4 illustrates in more detail the structure of a portion of FIG. 1 TV Transmitter 1 used to digitally filter the digital data from which the phase-shift keying signal is generated. The error-correcting coder 14 supplies a digital signal in serial-bit form to the rate buffer 20. Preferably, the coder 14 is a type that generates modified Reed-Solomon codes and the rate buffer 20 plays a dual role as an interleaver. The interleaver operation of rate buffer 20 is used to scan data into a column across a row of data finally transmitted by VSB BPSK data transmitter 12 simultaneously with each horizontal scan line of the composite picture signal transmitted by VSB AM picture transmitter 8. Place the original order. The impulse noise and mid-band frequencies of a composite picture signal that tend to combine in the horizontal direction are transformed to operate on the data mapped to the row along the horizontal scan line rather than on the data mapped to the column across the horizontal scan line. The above operation is performed to lessen the bits of the modified Reed-Solomon code than in the case of the Reed-Solomon code. In any case, the rate buffer 20 is a memory that supplies the regularly adjusted bits on the base to the frame-storage memory 21 for writing during the replacement data frame. Data frames are defined as blocks of 525 rows of symbols that occur at a symbol rate that is a multiple of the data row scan rate, which is equal to the horizontal scan line rate for the analog composite image signal. The BPSK symbols are bits, but these symbols to which modified Reed-Solomon codes are applied are typically 2 _N -bit data, where N is a small positive integer such as 3, 4 or 5. The bit length that each modified Reed-Solomon code extends is chosen to be less than 525 (e.g., 256 or 512), so that the impulse noise more than once confuses one of the modified Reed-Solomon codes along its longitudinal axis. do.

The relative phase of the data row and the horizontal scan line of the composite image signal is such that each data row coincides with each horizontal scan line of the composite image signal in time. The data frames appear at the same rate as the frames of the analog composite image signals supplied by source 7, but for reasons further disclosed herein it is desirable that the data frames delay the image signal frames by nine horizontal scan lines of the composite image signal. It is convenient. In order to generate an output signal provided as an input signal to the partial-response filter 16 during each frame of the successive pairs of data frames, the frame-storage memory 21 reads and writes the first data frame and re-writes the second data frame. Before writing, re-read after writing. Writing and reading of the rate buffer 20 and the frame-storage memory 21 are controlled by the frame-storage packing-control circuit 22.

The frame counter in Transmitter 1, used to count eight frame cycles for controlling the insertion of the ghost-erase reference signal into the composite picture signal during the selected vertical-blank erasure period (VBI) scan line, is a step in it. And a module-2 data frame counter 23 used to time read and write-write repeat operations of the frame-storage memory 21 during each frame of each successive pair of data frames. The packing-control circuit 22 also receives a data row count signal from the data row counter 24 and a symbol count signal from the symbol counter 25, and receives the received data row count signal and the symbol count signal, respectively, in row addressing and row-in-row. Read addressing is applied to the frame-storage memory 21. The data row count and the symbol count together constitute a completion addressing AD, and the packing-control circuit 22 applies the completion addressing AD to the frame-storage memory 21 of FIG. The circuit 22 also reads the writeable signal WE for the frame-storage memory 21 and the read-addressing RAD supplied to the rate buffer 20 simultaneously with the completion addressing AD supplied to the frame-storage memory 21 during the writing of the frame-storage memory. And write addressing WAD for rate buffer 20. When digital data is selectively transmitted, the circuit 22 also generates a readable signal RE for the frame-storage memory 21.

More detailed operation modes are as follows. The data frame count bits are fed from the frame counter 23 to the packing-control circuit 22 where they are used to generate a writable signal for the frame-storage memory 21 only if the modulo-2 data frame count bits are zero. . The packing-control circuit 22 supplies the readable and writable signals to cause the frame-storage memory 21 to operate in a post-read write mode when the module-2 data count bit is zero. When the module-2 data frame count bit is 1, the packing-control circuit 22 supplies only a readable signal.

The final row decoder 27 receives the data row count signal from the data row counter 24 and generates control signals for the multiplexer 165 in the partial-response filter 16 and the multiplexer 169 (if used in the filter 16 above). The last row decoder 27 supplies a zero output signal as a result of the last row decoding in response to all values of the data row count except for indicating the last row in the data frame, which zero output signal is a multiplexer in the filter 16. 165 (also 169 if multiplexer 169 is used) causes normal partial-response filtering by filter 16 above. To adjust the load of 1-H delay line 164 (also 1-H delay line if used) to match the initial state of the filter 16 for the next data frame, the last row decoder 27 displays data representing the last row in the data frame. In response to the row count, a 1 response is supplied to multiplexer 165 in filter 16 (also 169 if multiplexer 169 is used). The modulo-2 data frame counter 23 supplies the modulator-2 data frame count to the multiplexer 165 as a replacement input signal so that when the last row decoder 27 supplies 1 to the multiplexer as a control signal, a 1-H delay line. Allows selection of 164 write input connections.

4 shows a symbol clocking circuit 30 including a voltage-controlled oscillator (VCO) 31, a zero-crossing detector 32, a 255-count decoder 33 and an automatic frequency and phase control (AFPC) detector 34 in addition to the symbol counter 25. It is shown. The symbol counter 25 includes eight binary count stages. The zero-crossing detector 32, more suitably referred to as the mean-axis-crossing detector, generates a pulse whenever the sine oscillation of oscillator 30 crosses its mean axis in a predetermined direction. The zero-crossing detector 32 is typically a limiter amplifier for generating square waves for a sinusoidal oscillation of VCO 31, a differential circuit for generating pulses in response to the transition of these square waves, and a frame-stored packing-control circuit for timing purposes. And constitutes a clipper for separating one pole pulses supplied to 22. These pulses are also supplied to the symbol counter 25 for counting on each successive line, to generate a symbol count supplied to the packing-control circuit 22. do. The 255-count decoder 33 decodes the symbol count up to 255 to generate a pulse. Rather than simply making the symbol count value arithmetic zero because the maximum count value is a power of two, each pulse from the 255-count decoder 33 is fed to the counter 25 by the zero-crossing detector 32 on the next pulse. Can be used to reset counter 25, returning the symbol count to arithmetic zero. The 255-count decoder 33 supplies a pulse to the AFPC detector 34 to compare with the horizontal sync sink H to develop the AFPC voltage supplied to VCO 31. This completes the negative feedback loop, which adjusts the frequency of the VCO 31 oscillation to be 255 times the horizontal scan line frequency, or 4 027 972 Hz.

We will look at one method of synchronizing counts by a module-2 data frame counter 23 and a data row counter 24 having frames of an analog composite picture signal. In the digital signal receiver for the system described herein, a counter that reproduces the data frame count for the first time in line 9 of each frame of the analog composite picture signal, immediately after the falling edge of the vertical sync pulse in the initial field of each frame. It is desirable to synchronize them. In such a case, the counter which generates a data row count at the digital signal receiver is reset to a predetermined count value at the beginning of line 9 of each frame of the analog composite image signal. Synchronizing the counts with the Modulo-2 data frame counter 23 and the data row counter 24 in transmitter 1 shown in FIG. 4 is suitable for the desired receiver implementation.

The output signal of the 255-count decoder 33 is supplied to the two-input AND gate 36 as the first input signal. The station sink generator 9 supplies a vertical sync pulse V to the falling edge detector 35, the detector 36 providing a pulse at the end of line 9 of the composite image signal and at the midpoint of line 271 of the composite image signal, the detector 36 The output signal of is supplied to the AND gate 35 as a second input signal. The response of the AND gate 35 constitutes a data-frame-end pulse at the end of line 9 of the composite picture signal. Each of these data-frame-end pulses is applied as a delay pulse to the Modulo-2 data frame counter 23 to advance the data frame count signal, and also to reset its data row count to a predetermined initial value. Applied to counter 24. Indeed, the 255-count decoder 33 may be absent, and carry pulses from the last binary count stage of the symbol counter 25 may be supplied to the AFPC detector 34 and the AND gate 35 instead of the output signal of the decoder 33.

The transmission apparatus described above in connection with FIGS. 1 to 4 is as described by both Jian. The following digital signal receivers in FIGS. 5 to 8 embody the present invention.

5 shows a digital-signal receiver 37 for receiving a television signal with a digital signal hidden therein from a means such as an antenna 42 and extracting the hidden digital signal. Tuner 43 selects a television channel detected by a first detector therein, the first detector being of a superheterodyne type for converting the selected television signal into one set of intermediate frequencies and one image set of frequencies. Is a tunable downconverter. An image intermediate frequency (IF) filter 44 selects an image intermediate frequency for application as an input signal to the intermediate frequency amplifier 45, but does not select the frequency of the image set. As a general practice, surface acoustic wave (SAW) filters can be used to construct an image intermediate frequency amplifier 45 in the image intermediate frequency filter 44 and in a single integrated circuit (IC), which is a multi-stage amplifier without inter-step tuning. The picture intermediate frequency amplifier 45 supplies an amplified picture intermediate frequency signal to the in-phase synchronous image detector 46 and the quadrature-phase synchronous image detector 47. The oscillator 48 oscillating at the standard frequency 45.75 MHz supplies the oscillation to the in-phase synchronous image detector 46 without phase shift, and to the quadrature-phase synchronous image detector 47 with a 90 degree delay phase shift by the shift network 49. The oscillator 48 has automatic frequency and phase control (AFPC) responsive to the output signal of the quadrature-phase synchronous image detector 47. The synchronous image detectors 46 and 47 are usually included in an integrated circuit together with the image intermediate frequency amplifier 45 and the oscillator 48. Each of the picture detectors 46 and 47 may be an exalted carrier type, or may be a true sync type. The in-phase modified composite image signal recovered by the in-phase synchronized image detector 46 is supplied to a horizontal sync separator 50 and a vertical sync separator 51, wherein the sync separators 50 and 51 are horizontal and vertical sync pulses from the in-phase modified composite image signal, respectively. To recover.

Although the picture intermediate frequency filter 44 is preferably made only about 3.5 MHz wide and centered on 45.25 MHz, the aspects of the digital-signal receiver 37 discussed so far are generally for those of ordinary skill in the field of TV receiver design. Familiar This picture intermediate frequency filter 44 provides chroma rejection and in-channel rejection without the need for filtering chroma rejection and in-channel rejection after the quadrature-phase image detector 47. If configured with a receiver, the picture intermediate frequency filter 44 will be widened with the chroma rejection and in-channel speech rejection provided by filtering after the quadrature-phase picture detector 47.) The bandwidth must be somewhat wider than the symbol rate in order not to reduce the higher frequency at the tail of the BPSK response. The quadrature-phase image detector 47 detects a keying signal involving only those portions of the NTSC composite image signal at frequencies above 750 kHz.

In fact, digital receiver 37 typically includes a ghost suppression circuit, which is described in detail in US patent application Ser. No. 08 / 108,311, filed August 20, 1993, although not explicitly shown in FIG. Can be seen by type. Each of the in-phase and quadrature phase image detectors 46 and 47 includes their ghost detector and respective ghost cancellation and equalization filters similar to those used following the synchronous detector included in another image detector. The adjustable parameters of the two ghost-erase filters are adjusted horizontally in response to a computation made in the computer, and the adjustable parameters of the two equalization filters are also adjusted horizontally in response to another computation made in the computer. Ghost-erasing reference (GCR) signals that extend frequencies up to 4.1 MHz when transmitted but only up to 2.5 MHz in digital signal receivers due to limited intermediate frequency bandwidth are selected verticals of the image signals detected by the in-phase synchronous image detector 46. Extraction from the blanking period (VBI) scan line. The GCR signals are digitized and supplied as input signals to a computer for calculating the adjustable parameters of the ghost-erase and equalization filters. Alternatively or additionally, direct current or low-frequency elements of the response of the quadrature-phase image detector 47 can be detected and used as a basis for calculating the adjustable parameters of the ghost-erasing filters.

In the digital-signal receiver 37 of FIG. 5, the sample / symbol count signal is generated by a sample / symbol counter 103 which counts pulses generated by the zero-crossing detector 104 in response to a sine oscillation received from the voltage-controlled oscillator 105. FIG. Is generated. The symbol count signal is generated by a symbol counter 52 that counts excess carriers from the sample / symbol counter 103. Decoder 55 decodes the symbol count up to 255 to generate both a sample / symbol count and a symbol count to generate a pulse that resets the counters 103 and 52 on the next pulse supplied to the counter 103 by a zero-crossing detector 104. Return to arithmetic zero The pulse generated by the decoder 55 is supplied to the AFPC detector 56 for comparison with the horizontal sync pulse H separated by the horizontal sync separator 50 and delayed to be adjustable to subdivide the symbol period by the control delay line 57. The comparison results are lowpass filtered in the AFPC detector 56 to generate an automatic frequency and phase control (AFPC) voltage signal for application to the VCO 105. These devices control the frequency of the oscillation supplied from the line-closed VCO 105 to be 4 096 times the horizontal scan line frequency f _H , or 64 447 545 kHz. The term line-closed, as used in connection with a controlled oscillator, is maintained at a nominal ratio for the frequency of the oscillation to the 15,734,264 kHz scan line frequency, which is usually achieved by an AFPC circuit that compares the frequency of the oscillation separated by a horizontal sync pulse by a suitable factor. It means done.

The keying signal and accompanying portions of the NTSC composite image signal at a frequency of 750 kHz or higher detected by the quadrature-phase image detector 47 are supplied to the matching filter 58, wherein the matching filter 58 is a frequency element of 750 kHz or more of the composite image signal. Respond to the keying signal, which is the selected portion of them. The matched filter 58 provides a peaking response that matches the roll-off of the transition-shape of the filter 18 in the transmitter to extend the PSK bandwidth sufficient to reduce intersymbol interference. The matched filter 58 is also substantially single sideband over the frequency range between 0.75 and 1.25 MHz and is substantially single sideband beyond the frequency range above 1.25 MHz, due to the VSB BPSK of the quadrature-phase image detector 47. The peaking response is further provided to compensate for the roll-off of the detection efficiency. However, since the residual sideband filters of the other TV transmitters show variations between each other, the peaking response to compensate for the roll-off of the detection efficiency of the quadrature-phase image detector 47 provides an appropriate peaking response in addition to the standard transition. In order to achieve this, the transition shaping filter 18 will probably be better at each TV transmitter 1. However, this additional peaking or pre-emphasis of the binary keying signal in transmitter 1 will increase the high frequency content of the BPSK to be greater than 0.75 MHz delivered with the luminescent signal.

The response from the matched filter 58 is applied as an input signal to an analog-to-digital converter (ADC) 106, for example a flash converter with 8-bit resolution. The quadrature-phase image detector 47 does not substantially recover a composite image signal frequency of 750 kHz or less, and BPSK coding has no zero-frequency content. While transmitting TV images without much energy at frequencies above 750 kHz, the BPSK portion of the response of the quadrature-phase synchronous image detector 47 will alternate from one pole to another. Placing one of the decision thresholds for quantizing the input signal on the ADC 106 at zero analog input level transmits the TV picture without any energy at frequencies above 750 kHz, even though the bit-resolution of the ADC 106 is slightly lower than 8 bits. This ensures that the BPSK portion of the response of the quadrature-phase synchronous image detector 47 will cause a change in the digital response of the ADC 106. Due to the non-responsiveness of the detector 47 to the low-frequency device of the sync pulse, the dynamic area of the composite image signal residue is reduced to less than 140 IRE units, which must be within the analog area capable output of the ADC 106 at the analog input port. And detector 47 reacts to the same area. If the ADC 106 has an 8-bit resolution and the amplitude of the BPSK is in units of about 3 IRE, five to six decision thresholds will be crossed by the BPSK. This is more than enough quantization noise so that TV images with some energy at frequencies above 750 kHz will not be able to place the BPSK portion of the response of the quadrature-phase locked image detector 47 between adjacent decision thresholds. However, if the symbol decision circuit has to make symbol decisions for the ternary keying signal, as shown in the case of digital signal receivers 37 and 38 in FIGS. 5 and 6, approximately sixteen decision thresholds are low. Should be crossed by the BPSK to ensure symbolic errors. If the symbol decision circuit has to make symbol decisions for the five-level keying signal, as shown in the case of the digital signal receivers 39 and 40 in FIGS. 7 and 8, 32 decision thresholds result in low symbol error. Should be crossed by the BPSK to ensure.

Thus, in a preferred embodiment of the present invention, ADC 106 is operated as an oversampling analog-to-digital converter to sample the response from matched filter 58 whenever a zero-crossing point is detected by zero-crossing detector 104. Thus, ADC 106 samples a symbol rate of 256 times horizontal refresh rate f _H 16 times, so that an additional 4-bit resolution can be obtained from 8-bit ADC 106 through oversampling. The digital response of the ADC 106 is fed to the finite-impulse-response (FIR) digital lowpass filter 107 as an input signal. The filter 107 is a multi-tap digital delay line in which signals from its successive taps are symmetrically weighted according to the sin x / x function prior to generating a lowpass filter response. The lowpass filter response from the filter 107 is fed to a 16-time subsampler or decimator 108 which provides a 12-bit analog-to-digital conversion response at a BPSK symbol rate of 256 times horizontal refresh rate f _H. Decimation by the 16-fold subsampler 108 reduces the storage capacity required in the delay portion of subsequent digital-comb filtering. Sampling from oversampler 108 at a symbol rate with an optimal phase is a form of synchronous symbol detection that exhibits a change in symbol rate but suppresses the response to elements of the composite image signal that are in phase with the sampling. .

Wired taking the sign bit of the ADC 106's digitized response signal. The sign bit delayed by one sample in the sign bit and bit latch 110 is supplied to the exclusive OR gate 111 as its respective input. The XOR gate 111 detects zero-crossing of the digitized response from the ADC 106 and supplies the detection result to the pulse phase discriminator 67. The pulse phase discriminator 67 detects zero-crossing of the ADC 106 response detected by the XOR gate 111 from an appropriate phase relationship with respect to the zero-crossing point of the oscillation signal of the control oscillator 105 detected by the zero-crossing detector 104. Selectively detect the departure point. The pulse phase discriminator 67 lowpass filters this sampled detected starting point to generate a control signal for adjusting the delay that the control delay line 57 provides to the horizontal sync pulse H applied to the AFPC detector 56. do. This selective detection by the pulse phase discriminator 67 can be made during the vertical blanking period when the value of the response of the quadrature-phase image detector 47 for the composite image signal is expected to be zero. During digitization, the phase for the sample at the symbol rate of the ADC 106 input signal is thus adjusted to minimize intersymbol interference.

The devices for adjusting the phase of a line-locked oscillator are of a type developed by Ko Jung, a colleague of the present inventor. The AFPC loop, which controls the frequency and phase of the oscillation signal of the control oscillator 105 with respect to the adjustable delayed horizontal sync pulse H, supplied from the control delay line 57, has an abrupt glitch of the period during which the ADC 65 clocking is adjusted. Or provide filtering to prevent significant shortening. Such drastic changes sometimes occur when proper phase adjustment is attempted at the ADC 65 clocking itself.

Vertical sync separator 51 supplies an integrated response with loss for a separate vertical sync pulse V to threshold detector 68 whose threshold voltage is greater than 5 and 1/2 scan lines, 6 and 1 / It is selected to be exceeded only when integrated below two scan lines. The output signal of threshold detector 68, which is 1 only when the input signal exceeds the threshold voltage and 0 otherwise, is supplied as a first input signal to the 2-input AND gate 69 (at the end of the horizontal scan line). The decoder 55, which generates one for the final value of the symbol count in each data row, or zero otherwise, supplies its output signal to its AND gate 69 as its second input signal. 1 from the output of the AND gate 69 provides a respective data-frame-end pulse for each of these falling sections, in response to the falling sections of the vertical pulses occurring at the beginning of the initial field of the composite image signal frame. It does not respond to falling periods of vertical pulses that occur between the initial and final fields of each frame.

To advance the regenerated data frame count signal subtracted by one scan line from the data frame count signal at the transmitter, the data-frame-end pulse at the response of the AND gate 69 is a modulo-2 data frame counter. 70 is supplied as a count input (CI) signal. As shown in US patent application Ser. No. 08 / 108,311, the best method of arrangement for synchronizing data frame counts in TV transmitter 1 and digital data receiver 37 is the burst phase and vessel in the 19th scan line of a four-frame period. Reference is made to a ghost cancellation reference (GCR) signal that occurs at a given permutation of Bessel chirp phases. The single-binary-stage counter 70 that generates the Modulo-2 data frame count is often one stage in the multi-binary-stage counter that generates the Modulo-2N (N is a positive integer of at least 2) data frame count. The multi-binary-end counter is used to determine the cumulative time of the ghost cancellation reference (GCR) signal.

The data-frame-end pulse in the response of the AND gate 69 is also applied as a reset signal to the data row counter 71 to reset the data row count recovered to its output signal to arithmetic zero, where the output signal is 524. Should be The data row counter 71 is connected to count the horizontal sync pulses H supplied from the horizontal sync separator 50. The data row count is in a circuit for acquiring data for a computer that calculates adjustable filtering parameters for the equalization and ghost-erase filters included in image detectors 46 and 47 (not explicitly shown in FIG. 5). It is used to control the selection of the VBI scan-line containing the GCR signal.

The highpass frame-comb filter 72 receives the digital response of the subsampler 108 as an input signal. The highpass frame-comb filter 72 includes a digital frame-storing 74 and a digital subtractor 73 responsive to the signal sample for later supplying the signal sample applied to the input stage to the output stage for a later one frame scan period as appropriate. The digital frame storage 74 conveniently consists of RAM operated in a read-write repeat mode. This RAM receives data row counts from the counter 71 with line addressing (LAD) and symbol counters from the counter 52 with symbol addressing (SAD). The subtractor 73 receives a sample of the digitized keying signal for the current frame from the subsampler 108 as the subtracted input signal, and receives the corresponding sample of the digitized keying signal for the preceding frame from the frame storage 74 as the subtracted input signal. do. The difference signal from the subtractor 73 is the response of the highpass frame-comb filter 72, from which the residual light emitting element exhibiting frame-to-frame correlation is removed.

Highpass line-comb filter 120 receives this response as its input signal. The highpass line-comb filter 120 is a matched filter for the second-degree partial-response filter 160 used in the partial-response filter 16 in the first degree transmitter 1. The high pass line-comb filter 120 suppresses elements of the composite picture signal that accompany the detected keying signal but do not exhibit line-to-line variation. The detailed structure of the filter 120 will be further described herein in connection with FIGS. 9 and 10.

The analog signal supplied in part to the highpass line-comb filter 59 as an input signal describes the binary encoding of the keying signal while some output signals from the highpass line-comb filter 59 describe the ternary encoding of the keying signal, The output signal is digitized by the ADC 65 to supply an input signal to the highpass frame-comb filter 72. Since the valid data frames combine two data frames with corresponding digital samples with the same amplification and opposite poles, the digitized signal supplied as the output signal from the highpass frame-comb filter 72 is the replacement data which is the valid data frame. Describes the ternary encoding of the keying signal in a frame. In an intervening replacement data frame that is an invalid data frame, the digitized signal supplied to the output signal from the highpass frame-comb filter 72 is in fact five-level, but symbol determination based on the invalid data frame is not important.

The analog signal supplied as part of the ADC 106 as an input signal describes the binary encoding of the keying signal and, therefore, the digital signal supplied to the highpass frame-comb filter 72 as the input signal also describes the binary encoding of the keying signal. The digital response from the highpass frame-comb filter 72 supplied as an input signal to the highpass line-comb filter 120 describes the binary encoding of the keying signal in the replacement dataframe, which is a valid dataframe, in which the subtractor 73 differentially combines two data frames with corresponding digital samples of equal amplification and opposite polarity. In an invalid data frame, the subtractor 73 sometimes differentials two data frames with corresponding digital samples that have the same amplification and opposite poles, but at different times the same amplification and poles (this same pole may be positive or negative). In this replacement data frame, which is an invalid data frame, the digital response from the highpass line-comb filter 72 supplied as an input signal to the highpass frame-comb filter 120 is actually ternary. During this invalid replacement data frame, the digital response from the highpass line-comb filter 120 is in fact five-level, but symbol determination based on the invalid data frame is not important. During the effective replacement data frame, the digital signal supplied as an input signal to the highpass line-comb filter 120 describes a binary encoding of a keying signal, and therefore the digital response from the highpass line-comb filter 120 is keyed. Describes the ternary encoding of a signal.

Thus, the symbol decision circuit 75, which receives the digital response of the highpass line-comb filter 120 as an input signal, has three comparator regions centered at -1, 0 and +1, respectively. The symbol decision circuit 75 includes an absolute value circuit 751 that generates a rectified digital response to the output signal from the high pass line-comb filter 120. The rectified digital response from the absolute value circuit 751 describes the binary encoding of the keying signal and is supplied to a threshold detector 752.

The threshold detector 752 is a form of symbol determination circuitry well known in the field of digital communications for making symbol decisions regarding binary coding of keying signals. The threshold detector 752 receives a symbol flow from the absolute value circuit 751 and determines whether this symbol is zero or one. The threshold detector 752 typically includes a digital comparator arranged to operate as a threshold detector, the threshold determination result being used to control the determination as to whether the symbol is one or zero depending on whether the threshold digital value is exceeded or not exceeded. Used. The threshold detector 752 is preferably in a form such that the threshold digital value for threshold determination is automatically adjusted according to the strength of the symbol. In such a case, the threshold detector 752 is combined with circuitry for detecting the average peak level of the symbol flow supplied by the absolute value circuit 751 or its average level, or both. There is a combined circuit for counting the digital value supplied to the comparator from each detected level to determine the threshold for threshold detection. The detection procedure for determining the symbol determination threshold is optionally performed during the vertical blanking period, preferably when the composite picture signal provides little energy to the signal detected by the quadrature-phase picture detector 47.

The symbol flow from the symbol determination circuit 75 is supplied as an input signal to the rate buffer 77, which is caused by the data frame count so that the keying signal is not erased and no frame-to-frame change occurs. Is to receive input samples only from those replacement frames where. Digital samples are fed to rate buffer 77 at symbol rate and come out at rate 1/2 symbol from rate buffer 77 for application to error-correction decoder 78. The decoder 78 receives the result of the determination by the symbol decision circuit 75 as serial-bit digital input data and corrects an error in the data to provide corrected serial-bit digital data, which is corrected digital-bit data. Output data of signal receiver 37, corresponding to serial-bit digital data shown as source 13 in FIG. 1 for supply to television transmitter 1. FIG.

In a preferred embodiment of a digital signal receiver 37 designed for use with transmitter 1 that uses a modified Reed-Solomon code that operates on a column of data across a horizontal scan line rather than on a row of data along a horizontal scan line. Buffer 77 acts as a deinterleaver for error-correction decoder 78. The write address generator for the rate buffer 77 is not shown in FIG. The read address generator includes a data row counter 71 for supplying a data row count and a symbol counter 52 for supplying a symbol count, where each count is supplied to row addressing and column addressing, respectively, in RAM (s) in the rate buffer 77. .

FIG. 6 shows a digital signal receiver 38 which is a variation of the digital signal receiver 37 of FIG. 5 and is also designed for use with transmitter 1 using the partial-response filter 160 shown in FIG. Compared to the digital signal receiver 37, in the digital signal receiver 38, the cascading order of the highpass frame-comb filter 72 and the highpass line-comb filter 120 is reversed.

FIG. 7 illustrates a digital signal receiver 39 which is a variation of the digital signal receiver 37 of FIG. 5 and designed for use with transmitter 1 using the partial-response filter 166 shown in FIG. In this digital signal receiver 39, the highpass line-comb filter 120 is followed by another highpass line-comb filter 130. This cascade of highpass line-com filters 120 and 130 corresponds to using a digital delay line followed by 0, 1-H and 2-H delay periods to feed the input signal to the weighted addition network. In order to develop the filter response at (0.25): 0.5: (-0.25) the weight is added.

When the partial-response filter in the transmitter is of the same kind or equivalent to 165 shown in FIG. 3, and the digital signal receiver is a three-scan high-band as or equivalent to that shown in FIG. When including a pass line-comb filter, the digital response of the highpass line-comb filter 72 during the valid data frame is essentially five-level rather than ternary in describing the PSK signal. Thus, the symbol decision circuit 75 of FIG. 5 or 6 having three comparator regions centered at -1, 0 and +1, respectively, is centered at -2, -1, 0, +1 and +2 in FIG. Is replaced by a symbol decision circuit 76 having five comparator regions. The symbol decision circuit 76 includes an absolute value circuit 761 that generates a rectified digital response to the output signal from the high pass frame-comb filter 72. The rectified digital response of the absolute value circuit 761 describes the ternary encoding of the keying signal superimposed on the direct-voltage pedestal rather than describing the binary encoding of the keying signal, so that the rectified digital response is Supplied to a double-threshold detector 762. The double-threshold detector 762 receives a symbol flow from an absolute value circuit 761 to determine whether the symbol is zero, one, or two, where two equals zero. The dual-threshold detector 762 is typically arranged to operate as a single-threshold detector, respectively, with two digital comparators and one equalizer dependent on the result of the threshold detection, with one comparator adapted to operate at twice the critical digital value of the other comparator. It includes some simple logic circuits to determine. If no threshold digital value is exceeded, the logic circuitry indicates that the symbol is zero. If only the low threshold digital value is exceeded, the logic circuitry indicates that the symbol is one. If both the low and high critical digital values are exceeded, the logic circuit indicates that the symbol is two, which is equal to zero. The double-threshold detector 762 is preferably arranged such that the digital value supplied to the comparators for determining the threshold for threshold detection is automatically adjusted according to the strength of the symbol. In such a case, the double-threshold detector 762 is coupled with circuitry for detecting the average level of the symbol flow supplied by the absolute value circuit 761 or its average peak level, or both. There is a circuit for determining each threshold for threshold detection by counting the digital value supplied to the digital comparators from each detected level. The detection procedure for determining the symbol determination threshold is optionally performed during the vertical erase period, preferably when the composite picture signal provides little energy to the signal detected by the quadrature-phase picture detector 47.

FIG. 8 is a variation of the digital signal receiver 39 of FIG. 7 and also shows a digital signal receiver 40 designed for use with transmitter 1 using the partial-response filter 166 shown in FIG. In this digital signal receiver 40, the highpass frame-comb filter 72 is located behind rather than in front of cascaded highpass line-comb filters 120 and 130 as in the digital signal receiver 39. Although the highpass frame-comb filter 72 follows the highpass line-comb filter 120, the arrangement preceding the highpass line-comb filter 130 is another embodiment of the present invention.

Symbol decision circuits 75 in digital signal receivers 37 and 38 in FIGS. 5 and 6 and symbol decision circuits 76 in digital signal receivers 39 and 40 in FIGS. 7 and 8 respectively. To implement what is called a hard decision, a hard decision is made to supply a binary input signal to the decoder 78. The symbol decision circuits 75 and 76 may instead be replaced by circuitry that feeds the input signal with multiple levels to the appropriate decoder, in order to fulfill what the data communication technicians call a soft-decision of forward error correction. .

FIG. 9 details one form 121 that a highpass line-comb filter 120 can take. An input terminal 122 for the filter 121 is connected to a non-inverting input connection of a differential-input amplifier 123 having an output connection connected to the output terminal 124 of the filter 121. The inverting input connection of the differential-input amplifier 123 receives a delay response to the output signal from the multiplexer 126 from the output connection of the analog delay line 125, and the output signal of the multiplexer 126 is applied to the input connection of the delay line 125. do. The analog delay line 125 provides a delay equal to the duration of one horizontal scan line. If such a 1-H delay line is in fact analog, the delay line is usually configured as a charge-coupled-device (CCD) shift register, and the differential-input amplifier 123 is coupled with a CCD shift register and its charge-injected input circuit. It is configured in a single integrated circuit and is included in the charge-sense output stage of the CCD shift register. The multiplexer 126 is conveniently configured within the same IC using a field-effect transmitter operated as a transmission gate.

The multiplexer 126 receives a control signal from decoder 61, which responds with a 1 to a data row count from the data row counter 71 that reaches a value associated with the last row of data in a data frame. Answer 0 for all other values of the row count. In response to the decoder 61 output signal 1, multiplexer 126 selects analog zero for its output response. In response to 0, the output signal of the decoder 61, the multiplexer 126 selects the detected BPSK signal supplied to the input terminal 122 to apply to the input connection of the 1-H delay line 125.

FIG. 10 illustrates in detail another form 127 that the highpass line-comb filter 120 may take, which is alternative to the form shown in FIG. 9 and does not include components 125 and 126. The output connection of multiplexer 128 is connected to the inverting input connection of differential-input amplifier 123 in FIG. The multiplexer 128 receives a control signal from decoder 62, and the decoder 62 responds with a 1 to a data row count from data row counter 71 that is reset to a value associated with the last row of data in one data frame, Answer 0 for all other values of the data row count. In response to 1 being the output signal of decoder 61, multiplexer 128 selects analog zero for that output response. In response to 0, the output signal of the decoder 61, the multiplexer 128 selects the output signal from the 1-H analog delay line 129 to apply to the non-inverting input connection of the differential-input amplifier 123. The output signal from the 1-H analog delay line 129 is a delay response to the signal supplied to the input terminal 122 of the filter 120, the delay being equal to the duration of one horizontal scan line.

11 shows in detail one form that the cascaded connections of the highpass line-comb filters 120 and 130 can take. Highpass line-comb filter 121 is the same as in FIG. The highpass line-comb filter 131 in FIG. 11 has components 132 to 136 corresponding to components 122 to 126 of the highpass line-comb filter 121 and are similarly connected within the range of each filter.

12 illustrates in detail the different forms that the cascaded connections of the highpass line-comb filters 120 and 130 can take. Highpass line-comb filter 127 is the same as in FIG. The highpass line-comb filter 137 in FIG. 12 has components 138 and 139 corresponding to components 128 to 129 of the highpass line-comb filter 127 and are similarly connected within the range of each filter.

FIG. 13 illustrates one form that rate buffer 20 shown in FIG. 4 can take when used as an interleaver for modified Reed-Solomon coding supplied from error-correcting coder 14. The data frame pair counter 80 receives the carry-out (CO) signal supplied from the data frame counter 23 as its count input (CI) signal. The data frame pair counter 80 controls alternate writes and reads of two data frame-stored random access memories 81 and 82 that operate as interleavers for error-correcting encoding. The RAMs 81 and 82 are written from the error-correcting coder 14 at a 1/2 PSK rate for alternate frame pair periods, and address scanning is done by columns and by symbols along the columns. Each of the RAMs 81 and 82 is read into the frame-storage memory 21 at the PSK ratio for each frame pair period following the frame pair period in which it is written, and address scanning is done by rows and by symbols along the rows. The symbols according to the lines mentioned here are PSK symbols or bits, rather than 2N-bit symbols associated with the modified Reed-Solomon code in terms of sign.

The address multiplexer 83 receives the data row count from the data row counter 24 and the symbol / row count from the symbol (eg, symbol along the row) counter 25 by read addressing. The address multiplexer 83 receives the data column count from the data column counter 84 and the symbol / column count from the symbol counter 85 along the column by write addressing. Zero-crossing detector 32 provides a triggering pulse at triggered flip-flop 86 at a PSK rate, which flips over an alternate transition of its output signal at a PSK rate at symbol counter 85 along the column. It serves as a frequency separator for supplying as input (CI). Decoder 87 decodes the symbol / column count up to the maximum count (assuming the symbol count according to the column starts at 0) and provides 1 to the data column counter 84 as a count input (CI) signal. The output signal of the decoder 87 is supplied as a first input signal to a two-input OR gate 88, and the OR gate 88 resets the symbol / column count to its initial value in response to one from the decoder 87. 1 is provided as a reset (R) signal to the symbol counter 85 according to FIG.

The second input signal supplied to the OR gate 88 and the reset (R) signal supplied to the data column counter 84 are provided by the output response from the three-input AND gate 89 and when the output response is one. This response resets both the symbol / column count and the data column count to their respective initial values. Decoder 260 supplies a logic one to the first input of the AND gate 89 when the data row count indicates that the last row of the data frame has arrived. Otherwise, the decoder 260 supplies a logic 0 as its output signal to the AND gate 89. (Partial-response filter 160 is used for transmitter 1 so that the data row count indicates that the last row of the data frame has arrived. If decoder 27 is designed to supply logic 1, then decoder 260 may be decoder 27 of FIG. 4.) Output signal from last symbol of data row decoder 33 and module from data frame counter 23. Two data frame counts are applied to the AND gate 89 as the remaining two of the three input signals of gate 89. The output response of the AND gate 89 is that the last symbol of the last row of data reaches an odd frame, just before reaching an even frame when any one of RAM 81 and 82 is read out into the frame-storage memory 21 for each row of data. If only 1.

If the Modulo-2 data frame pair count from the data frame pair counter 80 is 1, this causes the address multiplexer 83 to select read addressing and send it to RAM 81 and the write addressing to RAM 82. The modulo-2 data frame pair count 1 from the data frame pair counter 80 allows RAM 81 to be read into the frame-storage memory 21 per row of data, and 0, the complement of count 1, means that the RAM 82 is per data column. Allow error-correction coder 14 to write.

If the modulo-2 data frame pair count from the data frame pair counter 80 is zero, this causes the address multiplexer 83 to select read addressing and send it to RAM 82 and the write addressing to RAM 81. A modulo-2 data frame pair count from data frame pair counter 80 allows the RAM 82 to be read into the frame-storage memory 21 row by line of data, and complement 1 of count 0 indicates that RAM 81 is error per data column. -Allow the entry from correction coder 14.

FIG. 14 shows one form that may be taken when the rate buffer 77 shown in FIGS. 5-8 is intended to be used as a deinterleaver for modified Reed-Solomon coding supplied from the symbol decision circuit 75 or 76. FIG. . The data frame pair counter 90 receives a carry-out (CO) signal supplied from the data frame counter 70 as its count input (CI) signal. The data frame pair counter 90 controls alternate writing and reading of two data frame-stored random access memories 91 and 92 operated as deinterleaver for error-correcting encoding. The RAMs 91 and 92 are written only during alternate even frames in which data for writing the RAMs 91 and 92 is supplied from the symbol decision circuit 75 or 76 at a PSK rate, and address scanning is performed by rows and by symbols along the rows. Is done. The symbols according to the lines mentioned here are PSK symbols or bits rather than 2 ^N -bit symbols associated with the modified Reed-Solomon code from the point of view of the sign. Each of the RAMs 81 and 82 is read into the frame-storage memory 21 at a half PSK rate during the replacement frame pair period, and address scanning is performed by a column and by symbols along the column.

The address multiplexer 93 receives, by write addressing, a data row count from the data row counter 71 and a symbol / row count from the symbol (e.g., symbol along the row) counter 52. The address multiplexer 93 receives the data column count from the data column counter 94 and the symbol / column count from the symbol counter 95 according to the column by read addressing. The zero-crossing detector 104 provides a triggering pulse at the PSK rate for the triggered flip-flop 96, which flips the alternate transition of the output signal at a 1/2 PSK rate to the count counter 95 along the column. Function as a frequency separator for feeding as CI). Decoder 97 decodes the symbol / column count up to the maximum count (assuming the symbol count according to the column starts at 0), and provides 1 to the data column counter 94 as a count input (CI). The output signal of the decoder 97 is supplied as a first input signal to the 2-input OR gate 98, which resets 1 to the symbol counter 95 according to the column for resetting the symbol / column count to its initial value. R) responds to 1 from decoder 97 to provide as a signal.

The second input signal supplied to the OR gate 98 and the reset (R) signal supplied to the data column counter 94 are provided by an output response from a three-input AND gate 99 and when the output response is one This response resets both the symbol / column count and the data column count to their respective initial values. The decoder 61 supplies logic 1 to the first input of the AND gate 99 when the data row count indicates that the last row of the data frame has been reached. Otherwise, the decoder 61 supplies logic 0 as an output signal to the AND gate 99. The output signal from the last-symbol of data row decoder 55 and the Modulo-2 data frame count from data frame counter 70 are applied to the AND gate 98 as the remaining two of the three input signals of gate 98. . The output response of the AND gate 98 is the last symbol of the last data row in the odd frame, just before the even frame is reached when a selected one of the RAMs 91 and 92 is written from the symbol decision circuit 75 or 76 per data row. Only 1 when reached.

If the data frame pair count is from Modulo-2 data frame pair count from 90, this causes the address multiplexer 93 to select read addressing to RAM 91 and write addressing to RAM 92. The Modulo-2 data frame pair count 1 from the data frame pair counter 90 allows the RAM 91 to be read by the error-correction decoder 78 per data column. The two-input AND gate 101 selectively supplies one to the RAM 92 as a writable (WE) signal in response to one's complement of the data frame count and zero, the data frame count from the counters 70 and 90. This writable signal allows the RAM 92 to be written from the symbol decision circuit 75 or 76 by data rows.

If the Modulo-2 data frame pair count from data frame pair counter 90 is 1, this causes address multiplexer 93 to select read addressing to RAM 92 and write addressing to RAM 91. The modulo-2 data frame pair count 0 from the data frame pair counter 90 allows the RAM 92 to be read out to the error-correction decoder 78 per data column. The 2-input AND gate 102 selectively supplies 1 to the RAM 91 as a writable (WE) signal in response to the complement 0 of 1 of the data frame count and the data frame count 1 from the counter 90. This writable signal allows the RAM 91 to be written from the symbol decision circuit 75 or 76 by data rows.

The rate buffering at the digital signal receivers 37 to 40 to fill the remaining gap when the replacement frames of the non-effective signal resulting from the frame-comb filtering of the paired frames are eliminated is performed after the frame-comb filtering and before the symbol decision circuit. Can happen. Rate buffering is preferably done after symbol determination, but after that, the frame-storage memory only needs to be a 1-bit sequence rather than a multiple bit sequence. Rate buffering with deinterleaving before error-correction decoding is desirable because it eliminates the need to separate frame-storage memory and rate buffering. If rate buffering is done separately from deinterleaving, this is a dual-ported RAM with read-only ports supplied by the shift register and the serial stages of the register once from the portion of RAM accessed through the read / write port. Rate buffering can be done with only one frame-storage memory if it can be loaded horizontally, row by row.

The data transmission structure described herein provides a single suitably wide band data transmission channel. A variety of different services can be provided through this single data transmission channel using various forms of time-division-multiple structures. For example, data may be transmitted in packets, and each successive packet is provided with header information to indicate the nature of the provided data service and the origin of the data service. Television broadcasting devices and cable broadcasting devices can be a source of various data services. Packet headings that identify the origin in a two-way data transmission scheme may be used to select a suitable data return channel, such as a dedicated channel in a telephone line or a cable broadcasting system.

While embodiments of the invention have been described by the inventors, those of ordinary skill in the art of designing communication systems, transmitters, and receivers are able to design many alternative embodiments of the invention by knowing the above disclosure. Will be. This fact should be kept in mind when interpreting the scope of the claims according to the present specification.

Claims (50)

Digitally used as a system for serial transmission of digital symbols in a binary phase shift keying modulation sideband of a suppressed carrier having a quadrature phase difference of the image carrier in a combined transmission with an image carrier whose amplitude is modulated in accordance with a composite image signal. A signal receiver comprising: detecting a binary phase shift keying of a suppressed carrier in response to the combined transmission to detect a binary phase shift keying of the suppressed carrier to be detected from an amplitude modulated image carrier A detection device for generating the desired detector response involving the undesirable detector response consisting of residual components of the composite image signal; An analog to digital converter for digitizing the detector response; And a digital comb filter for receiving said digitalized detector response to generate a response that depends primarily on said desired detector response rather than said undesirable detector response. The digital receiver of claim 1, wherein the digital comb filter is a high pass digital frame-comb filter. 3. The digital receiver of claim 2, wherein the analog to digital converter is in the form of oversampling. 4. The digital receiver of claim 1 wherein the digital comb filter is a high pass digital line-com filter. 5. The digital receiver of claim 4, wherein the analog-to-digital converter is in the form of 'oversampling'. The digital receiver as claimed in claim 1, wherein the digital comb filter is a highpass digital frame-comb filter in which the highpass digital line-comb filter is cascaded. 7. The digital receiver of claim 6, wherein the analog-to-digital converter is in the form of 'oversampling'. 7. The apparatus of claim 6, further comprising a symbol determination circuit that receives a response from the high pass digital line-com filter and determines a coincidence state of each digital symbol to generate a bit-serial digital signal response. receiving set. 2. The digital receiver of claim 1, wherein the digital comb filter is a highpass digital line-comb filter in which the highpass digital frame-comb filter is cascaded. 10. The digital receiver of claim 9 wherein the analog-to-digital converter is in the form of 'oversampling'. 10. The apparatus of claim 9, further comprising a symbol determination circuit that receives a response from the high pass digital line-com filter and determines a coincidence state of each digital symbol to generate a bit-serial digital signal response. receiving set. Digital signals used in systems such as systems for transmitting digital symbols in series in a binary phase shift keying modulation sideband of a suppressed carrier in a quadrature phase of the image carrier in a combined transmission with an image carrier whose amplitude is modulated in accordance with a composite image signal. In a receiver, an undesirable detector consisting of residual components of a composite image signal detected from an amplitude modulated image carrier by detecting binary phase shift keying of the suppressed carrier to supply a detector response in response to the combined transmission. A detection device for generating a desired detector response accompanying the response; An analog-to-digital converter that 'oversamples' the detector response and digitizes the resulting sample to generate a response of an 'oversampled' and digitized detector having a predetermined number of bit resolutions for each of the samples of the digitized result. ; A digital region pass filter for receiving the 'oversampled' and digitized detector response and generating a digital low pass filter response; Decimate the digital low pass filter response to generate a subsampler response, which is a relatively sparse sampled and digitalized detector response, where each sample of the subsampler response has a greater number of bits than the predetermined number of bit resolutions. Has a resolution and the subsampler response is a relatively sparse sampled and digitized detector response resulting from the desired detector response and a relatively sparse sampled and digitalized undesirable detector resulting from the desired detector response. A subsampler containing the response; In the combined comb response having multiple response levels for each digital symbol therein representing the relatively coarse sampled and digitally detected desired detector response, the subsampler response is received and the undesirably relatively coarse sampled. A cascade of highpass digital line-com filters and highpass digital frame-comb filters connected to select a digitalized detector response; And a symbol determination circuit for determining a coincidence state of each digital symbol in response to the combined comb filter response to generate a bit-serial digital signal response. 13. The input of the highpass digital frame-comb filter of claim 12, wherein the highpass digital frame-comb filter precedes the highpass digital line-comb filter in the cascaded connection and receives the subsampler response. Connection; An output connection of the high pass digital frame-comb filter for supplying the high pass digital frame-comb filter response as an input signal to the digital line-com filter; A 1-frame digital delay line for delaying the subsampler response received at the input connection of the high pass digital frame-comb filter by a time interval corresponding to the duration of frame scanning of the composite image signal; A first input connection for receiving a delayed response from the 1-frame digital delay line, a second input connection connected without substantial delay from the input connection of the high pass digital frame-comb filter, and the first and second input connections. And a first digital subtractor having an output connection for supplying a differential response to a signal at a second input connection to an output connection of the high pass digital frame-comb filter. 15. The digital receiver of claim 13 wherein the 1-frame delay line is random access memory (RAM) operated in a read-then-write-over mode. 14. The apparatus of claim 13, wherein the high pass digital line-com filter comprises: an input connection of the high pass digital line-com filter to receive the high pass digital frame-comb filter response; An output connection of the high pass digital line-comb filter to supply the combined comb filter response; A 1-H digital delay line for delaying the high pass digital frame-comb filter response received at the input connection of the high pass digital line-comb filter by a time interval corresponding to the duration of the horizontal scan line of the composite image signal; A first input connection for receiving a delayed response from the 1-H digital delay line, a second input connection connected without a substantial delay from the input connection of the high pass digital line-comb filter, and the first and second input connections. And a second digital subtractor having an output connection for supplying a differential response to a signal at a second input connection to an output connection of said high pass digital line-comb filter. 16. The apparatus of claim 15, wherein the symbol determination circuit comprises: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for supplying a rectifying response; An input connection for receiving the rectified response from an output connection of the absolute value circuit and in a first state when the rectified response exceeds a threshold level and in a second state when the rectified response does not exceed a threshold level. And a threshold detector having an output connection for feeding bits of the digital signal. 14. The apparatus of claim 13, wherein the high pass digital line-com filter comprises: an input connection of the high pass digital line-com filter to receive the high pass digital frame-comb filter response; An output connection of the high pass digital line-comb filter to supply the combined comb filter response; A first 1-H digital delay for delaying the high pass digital frame-comb filter response received at the input connection of the high pass digital line-comb filter by a time interval corresponding to the duration of the horizontal scan line of the composite image signal. Crypts; A first input connection for receiving a delayed response from the first 1-H delay line, a second input connection connected without a substantial delay from the input connection of the high pass digital line-comb filter, and the first and second input connections. A second digital subtractor having an output connection for supplying a differential response to the signal at the second input connection; A second 1-H digital delay line for delaying the differential response of the second digital subtractor by a time interval corresponding to duration 1-H; A first input connection for receiving a delayed response from the second 1-H digital delay line, a second input connection connected without a substantial delay from an output connection of the second digital subtractor, and the first and second connections; And a third digital subtractor having an output connection 3 for supplying a differential response to a signal at an input connection to the output connection of said high pass digital line-comb filter. 18. The apparatus of claim 17, wherein the symbol determination circuit comprises: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for supplying a rectifying response; An input connection for receiving the rectified response from an output connection of the absolute value circuit, and in a first state when the rectified response exceeds a first threshold level and does not exceed a second threshold level higher than the first threshold level. And a double-threshold detector having an output connection for supplying a bit of a digital signal in a second state when the rectified response does not exceed the first threshold level or exceeds the first and second threshold levels. Digital signal receiver characterized in that. 13. The highpass digital frame-comb filter of claim 12, wherein the highpass digital frame-comb filter is followed by the highpass digital line-comb filter in a cascaded connection and receives the response from the highpass digital line-comb filter. Input connection of a comb filter; An output connection of the high pass digital frame-comb filter to supply the combined comb filter response; 1-frame digital for delaying the response from the highpass digital line-comb filter received at the input connection of the highpass digital frame-comb filter by a time interval corresponding to the duration of frame scanning of the composite image signal. Delay lines; A first input connection for receiving a delayed response from the 1-frame digital delay line, a second input connection connected without substantial delay from the input connection of the high pass digital frame-comb filter, and the first and second input connections. And a first digital subtractor having an output connection for supplying a differential response to a signal at a second input connection to an output connection of the high pass digital frame-comb filter. 20. The digital receiver of claim 19 wherein the 1-frame delay line is a random access memory (RAM) operated in a read-write repeat mode. 20. The apparatus of claim 19, wherein the high pass digital line-com filter comprises: an input connection of the high pass digital line-com filter to receive the subsampler response; An output connection of the high pass digital line-comb filter to an input connection of the high pass digital frame-comb filter; A first 1-H for delaying a desired detector response involving an undesirable detector response received at the input connection of the high pass digital line-comb filter by a time interval corresponding to the duration of the horizontal scan line of the composite image signal. Digital delay line; A first input connection for receiving a delayed response from the 1-H digital delay line, a second input connection connected without a substantial delay from the input connection of the high pass digital line-comb filter, and the first and second input connections. And a second digital subtractor having an output connection for supplying a differential response to a signal at a second input connection to an output connection of said high pass digital line-comb filter. 22. The apparatus of claim 21, wherein the symbol determination circuit comprises: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for supplying a rectifying response; An input connection for receiving the rectified response from an output connection of the absolute value circuit and in a first state when the rectified response exceeds a threshold level and in a second state when the rectified response does not exceed a threshold level. And a threshold detector having an output connection for feeding bits of the digital signal. 20. The apparatus of claim 19, wherein the high pass digital line-com filter comprises: an input connection of the high pass digital line-com filter to receive the subsampler response; An output connection of the high pass digital line-comb filter to an input connection of the high pass digital frame-comb filter; 1 for delaying the desired detector response involving the undesirable detector response received at the input connection of the high pass digital line-comb filter by a time interval corresponding to the duration 1-H of the horizontal scan line of the composite image signal. -H digital delay line; A first input connection for receiving a delayed response from the first 1-H digital delay line, a second input connection connected without a substantial delay from the input connection of the high pass digital line-comb filter, and the first input connection; And a second digital subtractor having an output connection for supplying a differential response to the signal at the second input connection; A second 1-H digital delay line for delaying the differential response of the second digital subtractor by a time interval corresponding to duration 1-H; A first input connection for receiving a delayed response from the second 1-H digital delay line, a second input connection connected without a substantial delay from an output connection of the second digital subtractor, and the first and second connections; And a third digital subtractor having an output connection for supplying a differential response to a signal at a two input connection to an output connection of said high pass digital line-comb filter. 24. The apparatus of claim 23, wherein the symbol determination circuit comprises: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for supplying a rectifying response; An input connection for receiving the rectified response from an output connection of the absolute value circuit, and in a first state when the rectified response exceeds a first threshold level and does not exceed a second threshold level higher than the first threshold level. And a double-threshold detector having an output connection for supplying a bit of a digital signal in a second state when the rectified response does not exceed the first threshold level or exceeds the first and second threshold levels. Digital signal receiver characterized in that. A digital receiver for use with a system for transmitting digital information in a binary phase shift keying modulation sideband of an oppressed carrier at an orthogonal phase with an image carrier whose amplitude is modulated in accordance with a composite image signal, comprising: an amplitude modulated image carrier; A tuner for supplying an intermediate frequency signal response to a selected high frequency signal consisting of a binary phase shift keyed suppressed carrier; An intermediate frequency amplifier for said intermediate frequency signal response having a filtering element and an amplifying element and for supplying an amplified intermediate frequency amplifier response; A first controlled oscillation circuit for generating an in-phase intermediate frequency image carrier and a quadrature phase intermediate frequency image carrier at an intermediate frequency and an average phase controlled by the frequency and phase error signal; An in-phase image detector for receiving the amplified intermediate frequency amplifier response and synchronously detecting a composite image signal according to a supplied in-phase intermediate frequency image carrier; Receiving the amplified intermediate frequency amplifier response and receiving a binary phase shift keying signal accompanying an area of the composite image signal including the frequency and phase error signal in a quadrature phase image detector response from the quadrature phase image detector; A quadrature phase image detector for detecting synchronously according to the quadrature intermediate frequency image carrier supplied; A horizontal synchronizing separator for separating horizontal synchronizing pulses from the composite image signal by the in-phase image detector; A second controlled oscillator for generating a clock oscillation at a frequency and a phase controlled by said separated horizontal sync pulse and a multiple of a symbol rate for said binary phase shift keying signal; An analog-to-digital converter having an input connection for receiving the quadrature phase image detector response and an output connection for supplying a digitalized response to a sample of the quadrature phase image detector response sampled in response to the clock oscillation; A digitalized right angle at the symbol rate for the binary phase shift keying signal in response to a digitalized response to a sample of the analog input signal sampled in response to the clock oscillation from an output connection of the analog-to-digital converter. Means for supplying a phase image detector response; Receive the digitalized quadrature phase image detector response supplied at the symbol rate for the binary phase shift keying signal, supply a digital comb filter response for the binary phase shift keying signal therein, and A digital comb filter in which the digital comb filter response to the accompanying area is suppressed; And a symbol determination circuit for receiving the digital comb filter response and for determining a symbol transmitted by the binary phase shift keying signal. 26. The method of claim 25, wherein the clock oscillation has a predetermined number of bit resolutions for each of the samples of the result so digitalized that the analog-to-digital converter 'oversamples' the detector response and digitizes the resulting sample. Means for supplying a digitalized quadrature phase image detector response at the symbol rate for the binary phase shift keying signal, the frequency of generating an oversampled and digitized detector response from the analog-to-digital converter. A digital low pass filter for receiving an 'oversampled' and digitized detector response and generating a digital low pass filter response; And a subsampler to digitize the digital low pass filter response to generate the digitalized quadrature image detector response at the symbol rate for the binary phase shift keying signal. 26. The digital receiver of claim 25, wherein the digital comb filter comprises a cascade followed by a highpass digital frame-comb filter followed by a highpass digital line-comb filter. 28. The apparatus of claim 27, wherein the highpass digital frame-comb filter comprises: an input connection of the highpass digital frame-comb filter to receive the subsampler response; An output connection of said highpass digital frame-comb filter for supplying said highpass digital frame-comb filter response as an input signal to said highpass digital line-comb filter; A 1-frame digital delay line for delaying the subsampler response received at the input connection of the high pass digital frame-comb filter by a time interval corresponding to the duration of frame scanning of the composite image signal; A first input connection for receiving a delayed response from the 1-frame digital delay line, a second input connection connected without substantial delay from the input connection of the high pass digital frame-comb filter, and the first and second input connections. And a first digital subtractor having an output connection for supplying a differential response to a signal at a second input connection to an output connection of the high pass digital frame-comb filter. 29. The apparatus of claim 28, wherein the high pass digital line-com filter comprises: an input connection of the high pass digital line-com filter to receive the high pass digital frame-comb filter response; An output connection of the high pass digital line-comb filter to supply the combined comb filter response; A 1-H digital delay line for delaying the high pass digital frame-comb filter response received at the input connection of the high pass digital line-comb filter by a time interval corresponding to the duration of the horizontal scan line of the composite image signal; A first input connection for receiving a delayed response from the 1-H digital delay line, a second input connection connected without a substantial delay from the input connection of the high pass digital line-comb filter, and the first and second input connections. And a second digital subtractor having an output connection for supplying a differential response to a signal at a second input connection to an output connection of said high pass digital line-comb filter. 30. The apparatus of claim 29, wherein the symbol determination circuit comprises: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for supplying a rectifying response; An input connection for receiving the rectified response from an output connection of the absolute value circuit and in a first state when the rectified response exceeds a threshold level and in a second state when the rectified response does not exceed a threshold level. And a threshold detector having an output connection for feeding bits of the digital signal. 30. The device of claim 29, wherein an output signal bit supplied from an output connection of the symbol determination circuit is supplied at a symbol rate, and the digital signal receiver separates vertical sync pulses from the composite image signal detected by the in-phase image detector. A vertical synchronous separator; A data frame counter for generating a data frame count by counting the separate vertical sync pulses generated when the symbol counts according to the row are not in the middle row region; An input connection connected to receive a bit from an output connection of the symbol determination circuit and to receive the bit only when and when the data frame count modulo-2 has a predetermined value of two values, and a 1/2 symbol And a rate buffer having an output connection for supplying the symbol determination circuit output signal bits at a rate and in a predetermined order. 32. The method of claim 31, wherein the rate buffer is operated as a de-interleaver for supplying the symbol decision circuit output signal bits to an error correction decoder at a half symbol rate and in order of data string units. Digital signal receiver. 32. The digital signal receiver of claim 31, wherein the digital signal receiver counts the symbol clock oscillations to generate a row of symbol counts and the symbols with a predetermined basic count value for the symbol count in response to each of the separate horizontal sync pulses. A symbol counter according to the row for resetting the counts; A data row counting each time a symbol counter according to the row is reset to generate a data row count and resetting the data row count to a predetermined base count value for the data row count in response to each of the separate vertical sync pulses. A counter; When the data frame count modulo-2 has the predetermined one of two values and only then is written by the bit from the output connection of the symbol determination circuit for an individual time, and as the write addressing for the respective time. And at least one random access memory (RAM) included in the rate buffer and receiving the data row count and the symbol count according to the row. 29. The apparatus of claim 28, wherein the high pass digital line-com filter comprises: an input connection of the high pass digital line-com filter to receive the high pass digital frame-comb filter response; An output connection of the high pass digital line-comb filter to supply the combined comb filter response; A first 1-H digital delay for delaying the high pass digital frame-comb filter response received at the input connection of the high pass digital line-comb filter by a time interval corresponding to the duration of the horizontal scan line of the composite image signal. Crypts; A first input connection for receiving a delayed response from the first 1-H delay line, a second input connection connected without a substantial delay from the input connection of the high pass digital line-comb filter, and the first and second input connections. A second digital subtractor having an output connection for supplying a differential response to the signal at the second input connection; A second 1-H digital delay line for delaying the differential response of the second digital subtractor by a time interval corresponding to duration 1-H; A first input connection for receiving a delayed response from the second 1-H digital delay line, a second input connection connected without a substantial delay from an output connection of the second digital subtractor, and the first and second connections; And a third digital subtractor having an output connection for supplying a differential response to a signal at an input connection to an output connection of said high pass digital line-comb filter. 35. The apparatus of claim 34, wherein the symbol determination circuit comprises: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for supplying a rectifying response; An input connection for receiving the rectified response from an output connection of the absolute value circuit, and in a first state when the rectified response exceeds a first threshold level and does not exceed a second threshold level higher than the first threshold level. And a double-threshold detector having an output connection for supplying a bit of a digital signal in a second state when the rectified response does not exceed the first threshold level or exceeds the first and second threshold levels. Digital signal receiver characterized in that. 35. The digital signal receiver of claim 34, wherein the output signal bits supplied from the output connection of the symbol determination circuit are supplied at a symbol rate, and the digital signal receiver separates vertical sync pulses from the composite image signal detected by the in-phase image detector. A vertical synchronous separator; A data frame counter for generating a data frame count by counting the separate vertical sync pulses generated when the symbol counts according to the row are not in the middle row region; An input connection connected to receive a bit from an output connection of the symbol determination circuit and to receive the bit only when and when the data frame count modulo-2 has a predetermined value of two values, and a 1/2 symbol And a rate buffer having an output connection for supplying the symbol determination circuit output signal bits at a rate and in a predetermined order. 37. The method of claim 36, wherein the rate buffer is operated as a de-interleaver for supplying the symbol decision circuit output signal bits to an error correction decoder at a half symbol rate and in data string order. Digital signal receiver. 37. The digital signal receiver of claim 36, wherein the digital signal receiver counts the symbol clock oscillations to generate a row of symbol counts and the symbols with a predetermined basic count value for the symbol count in response to each of the separate horizontal sync pulses. A symbol counter according to the row for resetting the counts; A data row counting each time the symbol count according to the row is reset to generate a data row count and resetting the data row count to a predetermined base count value for the data row count in response to each of the separate vertical sync pulses. A counter; When the data frame count modulo-2 has the predetermined one of two values and only then is written by the bit from the output connection of the symbol determination circuit for an individual time, and as the write addressing for the respective time. And at least one random access memory (RAM) included in the rate buffer and receiving the data row count and the symbol count according to the row. 26. The digital receiver of claim 25, wherein the digital comb filter comprises a cascade followed by a highpass digital line-comb filter followed by a highpass digital frame-comb filter. 40. The apparatus of claim 39, wherein the highpass digital frame-comb filter comprises: an input connection of the highpass digital frame-comb filter to receive a response from the highpass digital line-comb filter; An output connection of the high pass digital frame-comb filter to supply the combined comb filter response; 1-frame digital for delaying the response from the highpass digital line-comb filter received at the input connection of the highpass digital frame-comb filter by a time interval corresponding to the duration of frame scanning of the composite image signal. Delay lines; A first input connection for receiving a delayed response from the 1-frame digital delay line, a second input connection connected without substantial delay from the input connection of the high pass digital frame-comb filter, and the first and second input connections. And a first digital subtractor having an output connection for supplying a differential response to a signal at a second input connection to an output connection of the high pass digital frame-comb filter. 41. The apparatus of claim 40, wherein the high pass digital line-com filter comprises: an input connection of the high pass digital line-com filter to receive the subsampler response; An output connection of the high pass digital line-comb filter to an input connection of the high pass digital frame-comb filter; A 1-H digital delay line for delaying a detector response involving an undesirable detector response received at an input connection of said high pass digital line-comb filter by a time interval corresponding to the duration of a horizontal scan line of said composite image signal; ; A first input connection for receiving a delayed response from the 1-H digital delay line, a second input connection connected without a substantial delay from the input connection of the high pass digital line-comb filter, and the first and second input connections. And a second digital subtractor having an output connection for supplying a differential response to a signal at a second input connection to an output connection of said high pass digital line-comb filter. 43. The apparatus of claim 41, wherein the symbol determination circuit comprises: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for supplying a rectifying response; An input connection for receiving the rectified response from an output connection of the absolute value circuit and in a first state when the rectified response exceeds a threshold level and in a second state when the rectified response does not exceed a threshold level. And a threshold detector having an output connection for feeding bits of the digital signal. 42. The digital signal receiver of claim 41, wherein an output signal bit supplied from an output connection of the symbol determination circuit is supplied at a symbol rate, and the digital signal receiver separates vertical sync pulses from a composite image signal detected by the in-phase image detector. A vertical synchronous separator; A data frame counter for generating a data frame count by counting the separate vertical sync pulses generated when the symbol counts according to the row are not in the middle row region; An input connection connected to receive a bit from an output connection of the symbol determination circuit and to receive the bit only when and when the data frame count modulo-2 has a predetermined value of two values, and a 1/2 symbol And a rate buffer having an output connection for supplying the symbol determination circuit output signal bits at a rate and in a predetermined order. 44. The method of claim 43, wherein the rate buffer is operated as a de-interleaver for supplying the symbol decision circuit output signal bits to an error correction decoder at a half symbol rate and in order of data string units. Digital signal receiver. 44. The digital signal receiver of claim 43, wherein the digital signal receiver counts the symbol clock oscillations to generate a row of symbol counts and wherein the symbols are at a predetermined basic count value for the symbol count in response to each of the separated horizontal sync pulses. A symbol counter according to the row for resetting the counts; A data row counting each time the symbol count according to the row is reset to generate a data row count and resetting the data row count to a predetermined base count value for the data row count in response to each of the separate vertical sync pulses. A counter; When the data frame count modulo-2 has the predetermined one of two values and only then is written in individual time by bits from the output connection of the symbol determination circuit, and as write addressing for the respective time. And at least one random access memory (RAM) included in the rate buffer and receiving the data row count and the symbol count according to the row. 41. The apparatus of claim 40, wherein the high pass digital line-com filter comprises: an input connection of the high pass digital line-com filter to receive the subsampler response; An output connection of the high pass digital line-comb filter to an input connection of the high pass digital frame-comb filter; A first detector for delaying a desired detector response involving an undesirable detector response received at an input connection of said high pass digital line-comb filter by a time interval corresponding to a duration of 1-H of a horizontal scan line of said composite image signal; A 1-H digital delay line; A first input connection for receiving a delayed response from the first 1-H delay line, a second input connection connected without a substantial delay from the input connection of the high pass digital line-comb filter, and the first and second input connections. A second digital subtractor having an output connection for supplying a differential response to the signal at the second input connection; A second 1-H digital delay line for delaying the differential response of the second digital subtractor by a time interval corresponding to duration 1-H; A first input connection for receiving a delayed response from the second 1-H digital delay line, a second input connection connected without a substantial delay from an output connection of the second digital subtractor, and the first and second connections; And a third digital subtractor having an output connection for supplying a differential response to a signal at an input connection to an output connection of said high pass digital line-comb filter. 47. The apparatus of claim 46, wherein the symbol determination circuit comprises: an absolute value circuit having an input connection for receiving the combined comb filter response and an output connection for supplying a rectifying response; An input connection for receiving the rectified response from an output connection of the absolute value circuit, and in a first state when the rectified response exceeds a first threshold level and does not exceed a second threshold level higher than the first threshold level. And a double-threshold detector having an output connection for supplying a bit of a digital signal in a second state when the rectified response does not exceed the first threshold level or exceeds the first and second threshold levels. Digital signal receiver characterized in that. 47. The digital signal receiver of claim 46, wherein an output signal bit supplied from an output connection of the symbol determination circuit is supplied at a symbol rate, and the digital signal receiver separates vertical sync pulses from a composite image signal detected by the in-phase image detector. A vertical synchronous separator; A data frame counter for generating a data frame count by counting the separate vertical sync pulses generated when the symbol counts according to the row are not in the middle row region; An input connection connected to receive a bit from an output connection of the symbol determination circuit and to receive the bit only when and when the data frame count modulo-2 has a predetermined value of two values, and a 1/2 symbol And a rate buffer having an output connection for supplying the symbol determination circuit output signal bits at a rate and in a predetermined order. 49. The method of claim 48, wherein the rate buffer is operated as a de-interleaver for supplying the symbol decision circuit output signal bits to an error correction decoder at a half symbol rate and in data string order. Digital signal receiver. 49. The digital signal receiver of claim 48, wherein the digital signal receiver counts the symbol clock oscillations to generate a row of symbol counts and the symbols with a predetermined basic count value for the symbol count in response to each of the separate horizontal sync pulses. A symbol counter according to the row for resetting the counts; A data row counting each time the symbol count according to the row is reset to generate a data row count and resetting the data row count to a predetermined base count value for the data row count in response to each of the separate vertical sync pulses. A counter; When the data frame count modulo-2 has the predetermined one of two values and only then is written by the bit from the output connection of the symbol determination circuit for an individual time, and as the write addressing for the respective time. And at least one random access memory (RAM) included in the rate buffer and receiving the data row count and the symbol count according to the row.