CN1117686A - Receiver with sigma-delta analog-to-digital conversion for digital signals buried in TV signals - Google Patents

Abstract

Digital signal receivers for detecting BPSK modulation of a suppressed carrier perpendicularyly to a video requency carrier of an interfering analog television signal are described, in which the detected BPSK is digitized with an oversampling analog-to-digital converter prior to digital comb filtering for separating the BPSK from interfering analog television signal remnants. This is done to get an increased number of bits resolution from a relatively inexpensive flash converter so that the BPSK, which is of relatively low amplitude compared to maximally interfering analog television signal remnants, is not overwhelmed by quantizing noise. The oversampling analog-to-digital converter can be of sigma-delta type.

Description

Receiver with ∑-Δ analog/digital conversion of the digital signal that is used to be embedded in the TV signal

The present invention relates to be used to recover imbed the receiver of the digital signal of anolog TV signals.

If digital signals format is kept suitably restriction, it is relatively little that (for example 3～5IRE) signal encoding digital informations can mix with videoblankingsync, and do not have anything significantly to be not suitable in the TV image that is produced by these composite video signals.In the applying date is that October 26, application number in 1993 are 08/141070, the invention exercise question is the U.S. Patent application of " being used for handling the equipment of the NTSC TV signal of the data-signal that has on the quadrature phase video carrier ", Jian Yang has described a kind of system that realizes above-mentioned feature, here in the lump as a reference.Employee's contract of the invention of in employment, finishing according to the transfer that has earlier, the same Samsung Electronics Co., Ltd. of in application number is 08/141070 U.S. Patent application, describing that has been transferred to of invention with the present invention as described herein.U.S. Patent application 08/141070 has been described a kind of binary phase shift keying (BPSK) modulation of suppressed carrier, this suppressed carrier have the frequency identical with video carrier and with this by quadrature phasing.United States Patent (USP) 08/141070 advocates that BPSK is restricted to about 2MHz bandwidth, so that avoid the interference of crosstalk to the colourity in the TV receiver, described receiver separates colourity and do not rely on comb filtering with brightness.U.S. Patent application 08/141070 shows makes the data that are sent out by a partial-response filtering device that is used for deal with data, so that can described data be recovered, be best so that the PSK subcarrier is separated from the brightness part of composite video signal by the multilevel code unit decision circuit after the row comb filtering in the digital signal receiver.The continuous centering that U.S. Patent application 08/141070 also advocates to circulate in the successive frame of ntsc television signal is in each frame of anti-phase BPSK.This datacycle of form being made with frame follows the BPSK of composite video signal (this vision signal obtains with the ntsc television signal demodulator) almost can't see at the image that is used for being presented on the screen that produces from this composite video signal.Thisly also provide the basis of in digital signal receiver, using frame comb filtering to the datacycle of form, so that BPSK is partly separated with the brightness of the composite video signal of the static each several part of description serial image with frame.

U.S. Patent application 08/141070 has been described the problem that runs in digit signal receiver when being digitized after the BPSK judgement, and hypothesis has been used the sampler that is generally used for digital composite video signal.Composite video signal surpasses the residual composition (they are accompanied by this BPSK during by synchronous detection as BPSK) of 750KHz and estimates to understand relatively big more sometimes with BPSK.If after the synchronous detection of BPSK, just carry out digitlization, then many dynamic ranges that provided for analog input signal by sampler can be provided the residual composition of these big composite video signals, and owing to only have the quantizing noise of the sampler about 8 bit resolutions, relatively little bpsk signal is tending towards and can not judges fully.Have the sampler that reaches 12 bits though can make, it is too expensive and can not be used in the electronics industry that is used for mass selling.U.S. Patent application 08/141070 advocates before the bpsk signal digitlization they to be used simulation row comb filtering, so that reduce to follow the relative size of the composite video signal of BPSK above the residual composition of 750KHz.Bpsk signal can be determined in the more digital output area of sampler like this, to reduce the code element mistake.

Thomas Vincent Bolger is that October 26, application number in 1993 are 08/141071 in its applying date, exercise question is pointed out in the U.S. Patent application of " receiver with sampling simulation/digital translation that is used for TV signal digital signal ", though, be moderate relatively for the increase that increases this price of bandwidth that surpasses 2MHz along with the price of the increase transducer of its bit resolution increases sharply.In U.S. Patent application 08/141070, be that 2MHz needs the 4MHz sampling rate so that maximum symbol rate is taken a sample fully to the BPSK bandwidth constraints in the disclosed system, and with 16,32 or even 8 bit samplers of 64 times of these sampling rate work moderate relatively on price.Therefore, Bolger points out that crossing the sampling conversion method can be used, with the significant bit resolution that obtains increasing from 8 such bit samplers.Cross sampling with 16 times of 4MHz sampling rates and can obtain to reach 12 bit effective resolutions, the BPSK that is detected with digitlization and it can not lost in quantizing noise, both made this be detected BPSK with occupying of following the composite video signal of the most of dynamic range of this sampler relatively be relative little.

A kind of being called,, the sampling switch of crossing of " ∑-Δ " analog/digital converter was familiar with by circuit designers, was used for from the many bit resolutions of basic single-bit resolution A DC acquisition.Being used to increase substantially, the ∑ of the bit resolution of many bit resolutions analog/digital converter-Δ analog/digital converter (though seldom talking) is known.In their work, ∑-Δ analog/digital converter feedback digital outputs signal to a digital/analog converter, be fed to an analog subtracter therefrom, being used for producing one will make its digitized error signal at the subsequent step of crossing sample program by basic ADC.During the analog/digital conversion when quantizing noise and rise, because this noise is moved upward in frequency by negative feedback inhibition.So can suppress it, be non-existent at digital-to-analog transition period quantizing noise by low-pass digital filter.In view of this reason, the single-bit encoder is best in ∑-Δ analog/digital converter, and it has avoided the DAC mistake.Use the ADC of single-bit encoder to be unsuitable for surpassing the digital signal receiver that 1Mbit/s speed receives BPSK, because must be carried out so that satisfy the sampling rate of crossing sampling requirement of bit resolution requirement too high and can not realize.The problem that when attempt using the generally well-known ∑ that utilizes many bit encoder-Δ ADC, is run into make Bolger seek to remove to use ∑-Δ modulation sampling method, as in its U.S. Patent application 08/141071, describing.

The T.C.Leslie of Plessey Research Caswell Co., Ltd and B.Singh are at their paper " a kind of improved sigma-delta modulator structure " (1990 IEEESYMPOSIUM ON CIRCUITS﹠amp; SYSTEMS, 90 CH 2868-8900000-0372, PP.372-375) described in by using a ∑-Δ program to improve the bit resolution of a basic high bit resolution ADC, in this ∑-Δ program this substantially only bit of many bit resolutions ADC output signal be converted back to analog signal, be used for each and cross the purpose of feeding back during the sampling procedure.The inventor has recognized that the ∑-Δ conversion of Leslie and Singh type is well suited for solution the low-power BPSK that buries in the ntsc television signal is being carried out the analog/digital conversion problem that corresponding detection is run into afterwards.

The present invention is embodied in the digital signal receiver, be used to detect the BPSK modulation that on phase place, differs the suppressed carrier in 1/4 cycle with a video carrier, wherein before to BPSK comb filtering, utilize the sampling simulation/digital quantizer of crossing of a ∑-Δ type to make detected BPSK digitlization from remaining composite video signal by the composite video signal amplitude modulation(PAM).

Fig. 1 is as the overall schematic that is used to launch a television transmitter with the TV signal that is buried in digital signal wherein described in the U.S. Patent application 08/141070.

Fig. 2 and 3 is schematic diagrames of partial-response filtering device, any in them can be used among Fig. 1 as retouching in this television transmitter in the U.S. Patent application 08/141070.

Fig. 4 is that the usefulness of detailed presentation graphs 1 television transmitter is opposed and will be produced the schematic diagram of a part of the numerical data digital filtering of phase shift keying, and described phase shift keyed signal modulation suppresses the quadrature in phase video carrier.

Each is a schematic diagram of digital signal receiver separately for Fig. 5-8, and described receiver is used to receive a TV signal with the digital signal that is buried in wherein and extracts this buried digital signal, and every kind of digital signal receiver all embodies the present invention.

Figure 13 is a schematic diagram that plays the rate buffer of interleaver effect, and this rate buffer can be used in the part as television transmitter among U.S. Patent application 08/141070 described Fig. 1 shown in Figure 4.

Figure 14 is a schematic diagram that plays the rate buffer of deinterleaver device effect, and this rate buffer can be used in any one digital signal receiver among Fig. 5-8.

Figure 15 is the schematic diagram of a monocycle ∑-Δ transducer, and it can be used in any one digital signal receiver among Fig. 5-8 according to the present invention.

Figure 16 is the schematic diagram of a dicyclo ∑-Δ transducer, and it can be used in any one digital signal receiver among Fig. 5-8 according to the present invention.

In general, deleted isostatic lag in each accompanying drawing, so that make their easy understanding.The technical staff of video signal preprocessor design field will understand that this delay of time array pixel for strictness needs, and promptly owing to carry out different processing in different processing paths, data suffer no delay on these paths.Person of skill in the art will appreciate that such delay is necessary how long can continuing with these delays wherein, therefore will above-mentioned delay will not be described or discuss below.In logical circuit, person of skill in the art will appreciate that the potential delay in the operation of the compensating delay that how to provide required undesirable to overcome " logic competition " conditioned disjunction compensation actuating logic; And the corresponding detailed Logic Circuit Design of the delay of will not discussing and afford redress below.In addition, describe and show an analog/digital converter (ADC) in the present invention, person of skill in the art will appreciate that thisly have the desirability of a transducer of obscuring filter and how to realize, and will be explained in detail no longer below above-mentioned.And, describe and show a digital/analog converter (DAC) in the present invention, person of skill in the art will appreciate that the sort ofly have the desirability of sampling clock band resistance low pass filter and how to realize, and will not be described in further detail below following.

Fig. 1 shows a television transmitter 1, is used to launch a TV signal of wherein burying digital signal.Source 2 applies one or more analog audio signals and gives audio frequency treatment circuit 3, and this audio frequency treatment circuit 3 provides a modulation signal to an audio carrier transmitter 4 that is used to modulate the frequency of audio carrier.Audio frequency treatment circuit 3 comprises as sound-in-sync and the required delay of image.According to the common practice, this audio frequency processing circuit 3 comprises that also the preemphasis network of simulated audio signal is used to produce stereo and device secondary audio program (SAP) subcarrier with comprising, described subcarrier is included in the modulation signal that offers audio carrier transmitter 4.Modulation (FM) audio carrier typically is applied to a multiplexer 5 from transmitter 4, and this multiplexer 5 is by homophase VSB AM pix carrier and quadrature phase VSBBPSK data carrier frequency division multiplexing.At the television transmitter 1 that is used for space broadcasting, this multiplexer 5 is typically taked the form of the antenna of coupling network, and the frequency division multiplex signal that produces is broadcasted away from a transmitting antenna 6.A television transmitter that is used for the front end of cablecast system will not have the transmitting antenna 6 that space broadcasting is used.Multiplexer 5 will adopt different forms, from the frequency division multiplex signal of consideration channel by further by from the frequency division multiplex signal of other channel with offer the consequential signal frequency division multiplex of the junction cable of cablecast system by linear amplifier.

In Fig. 1, source 7 provides an analog composite video signal, this analog composite video signal is the basis that imposes on the modulation signal of transmitter 8, and this transmitter 8 provides VSB AM pix carrier to multiplexer 5 successively, and frequency modulation (FM) sound carrier is by frequency division multiplexing there.Vertical sync pulse, horizontal synchronization pulse and synchronous by the corresponding signal that provides by a platform synchronous generator 9 from the burst signal of the analog composite video signal in source 7.The source 7 of composite video signal and the control connection line 10 between the platform synchronizing generator 9 are expressed as this synchronous.Here source 7 is far-end generators of a composite video signal, the TV station of intown studio or another one and local television networking for example, and control connection line 10 can be that a general locking to platform synchronizing generator 9 connects.Here, source 7 is fixed cameras, and it can be by control connection line 10 from platform synchronizing generator 9 receiving synchronous informations.These or other comprise that the synchronization scenario that is used for video tape recorder and telecine machine equipment is that those skilled in the art are familiar with.Typically, adaptive multiplexer 11 is used to the synchronization blocks information that comprises vertical sync pulse, horizontal synchronization pulse, equalizing pulse, burst signal and blanking pulse (so-called " porch ") is inserted into as modulation signal and is provided in the composite video signal of pix carrier transmitter 8, to replace original synchronization blocks information.

The television transmitter 1 of Fig. 1 is different from present institute use transmitter, and a further AM transmitter 12 produces one and differs residual sideband, binary phase shift keying (VSBBPSK) suppressed carrier in 1/4 cycle with the VSB AM video carrier of NTSC composite video signal on phase place in this transmitter 1.This further VSB AM transmitter 12 can comprise a balanced modulator, anti-carrier wave and anti-BPSK modulation signal are carried out balance, with can further comprise 90 ° of phase-shift networks, be used to receive from the homophase video carrier of VSB AM transmitter 8 and provide the quadrature phase video carrier to this balanced modulator.From the VSB bpsk signal of transmitter 12, be applied to multiplexer 5 as the VSB AM video carrier of the NSTC composite video signal amplitude modulation of origin spontaneous emission machine 8, there by frequency modulation (FM) sound carrier frequency division multiplexing.Source 13 provides a digital signal to error recovery sign indicating number device 14 partially with the form of serial data, be used for error recovery partially the added bit of sign indicating number be inserted into the serial bit stream that is provided for a frame repeater 15.This frame repeater 15 provides the every frame that is received data with the output signal that doubles input signal.Output signal from frame repeater 15 is provided for a partial-response filtering device 16, partial-response filtering device 16 becomes a kind of like this form to data transaction, and promptly it will make the capable comb filtering of in a digital signal receiver inhibition composite video signal being done continue remaining.Digital response from this partial-response filtering device 16 is provided for a digital/analog converter (DAC) 17, so that convert a simulation keying signal to.This DAC 17 offers a high frequency preemphasis and transition mode filter 18 to keying signal, and this keying signal numeral of response " 0 " has a designated positive value, has an appointment negative value and respond a numeral " 1 ".The appointment negative level of modulated-analog signal has the absolute value identical with the designated positive value of modulated-analog signal.It only is monolateral band character that the loss of detection efficiency aspect when filter 18 compensation synchronously detects VSB BPSK, this loss ascribe transmission to.The response of filter 18 is keying signals that impose on balanced modulator in the transmitter 12, and described balanced modulator also receives one and wants modulated quadrature phase video carrier.Provide by the VSB AM video carrier of NTSC composite video signal amplitude modulation and carefully designed and work to the transmitter 8 of multiplexer 5, so that avoid parasitic phase modulation, this parasitic phase modulation may be disturbed the quadrature phase VSB BPSK suppressed carrier from transmitter 12.Because the quadrature phase VSB AM carrier suppressed of PSK, so wherein the phase place adjustment of the combined signal of VSB BPSK and VSB AM carrier wave can not have significantly different with the phase place adjustment of homophase VSB AM video carrier.Separate each other though Fig. 1 shows transmitter 8 and 12, can share same upper sideband filter and final amplifying stage by transmitter 8 and 12 in practice.

Fig. 2 illustrates a kind of form 160 that partial-response filtering device 16 can be taked.Be provided for the first input end of one two input different (XOR) door 162 with the digital input signals of serial data form through an input 161, its output that is connected with an output 163 provides the response of this partial-response filtering device 160 thus.Second input of exclusive-OR gate 162 with a digital delay line 164 read export link and receive a delayed response the output signal response of writing the input link that is applied to digital delay line 164 from a multiplexer 165.This digital delay line 164 provides " 1H " in the cycle that equals a TV horizontal scan line to postpone, it can by one with " read-then-write " (read-then-write-over) typical case of mode work address line storage memory and realize.Except when " the finally capable testing result " that is applied in to multiplexer 165 as control signal is one 1 o'clock (the capable partial-response filtering device 160 that just is being applied to of final data of a Frame of its expression), multiplexer 165 is selected the response of these partial-response filtering devices 160 at output 163, writes the input link with what deliver to data delay line 164.

When " finally go testing result " that be provided for multiplexer 165 as control signal when be " 1 " (the capable partial-response filtering device 160 that just is being provided for of expression final data), what multiplexer 165 handles " mould 2 Frames counting " offered digital delay line 164 writes the input link.Between the final departure date of the final frame of a pair of frame when so provided " mould 2 Frames counting " when being " 0 ", delegation " 0 " is written into data delay line 164, so that data do not change by this partial-response filtering device 160 during another is to first data line of frame.Yet, between first departure date of the start frame of a pair of Frame when " the mould 2 Frames counting " of writing the input link that be provided to digital delay line 164 selected by multiplexer 165 when being one 1, delegation 1 is written into digital delay line 164, so that during this first data line to the final frame of Frame, data are by the data through 160 supplements of partial-response filtering device.This makes this follow-up data to the final frame in the Frame capable is in that supplement to the capable data of the corresponding data of the preposition initial frame in the Frame.

The digital filtering that is provided by partial-response filtering device 160 suppresses the DC terms of an analog signal, this analog signal is to become a keying signal+1 and-1 amplitude produces by conversion at 0 and 1 of the digital response of output 163, and this keying signal is used to control the generation of bpsk signal.This digital filtering is with 1/2 horizontal scan line frequency f _HOdd-multiple present the peak value of response and with this horizontal frequency f _HMultiple present the null value of response.This digital filtering makes a psk signal in response to data have a pectination frequency spectrum, the pectination frequency spectrum complementation of this pectination frequency spectrum and luminance signal, and the pectination frequency spectrum of this luminance signal is with 1/2 horizontal sweep line frequency H _fOdd-multiple present the null value of response and with this horizontal sweep line frequency H _fMultiple present the peak value of response.Partial-response filtering device 160 constitutes the frequency spectrum of PSK, so that will be by one by a single 1H delay line and the high current comb filter of two taps that subtracter constitutes.A kind of so high current comb filter can be loaded into digital signal receiver, is used to be suppressed between the pixel of vertical arrangement have the luminance signal of good correlation and its interference signal as PSK is reduced it.

Fig. 3 shows the another kind of form 166 that partial-response filtering device 16 may be taked, and it comprises a final filtering part that contains with partial-response filtering device 160 components identical 162-165.Partial-response filtering device 166 further comprises an initial filtering part that is similar to its final filtering part.This initial filtering partly has one two input exclusive-OR gate 167, it has be connected with input 161 one first input and has one imports the output that is connected with first of exclusive-OR gate 162, and this output is not to be connected to input 161 like that in the partial-response filtering device 160 of image pattern 2.One second of exclusive-OR gate 167 input with digital delay line 168 read export link and receive a delayed response the output signal response of writing the input link that is applied to digital delay line 168 from multiplexer 169.This digital delay line 168 (as digital delay line 164) provides " 1H " in the cycle that equals a TV horizontal scan line to postpone.Except when " finally go testing result " that is applied to multiplexer 169 as control signal is 1 o'clock (the capable partial-response filtering device 166 that just is being provided for of final data of representing a Frame), multiplexer 169 selects these exclusive-OR gates 167 to be used to deliver to the response of writing the input link of data delay line 168.

When " finally go testing result " that be provided for multiplexer 169 as control signal when being 1, what the indication final data capable partial-response filtering device 166 that just is being applied to, this multiplexer 169 provided that a line " 0 " gives digital delay line 164 writes the input link.Between the final departure date of each Frame, just a pair of " 0 " is written in the data delay line 164 like this.During the initial row of next Frame, this delegation " 0 " is applied to exclusive-OR gate 167, so that the initial row of data is sent to exclusive-OR gate 162 by exclusive-OR gate 167, and the data complement that is used to select, described as partial-response filtering device 160 corresponding to Fig. 2.

Partial-response filtering device 166 has than the more pectination response of pointed tooth of partial-response filtering device 160, and with 1/2 horizontal scan line frequency f _HOdd-multiple present the null value of response and with the horizontal scan line frequency f _HMultiple present the peak value of response.In this digital signal receiver, can use the high current comb filter of one three tap to make psk signal revert to a smooth frequency spectrum and reduce luminance signal as the interference signal of PSK.

Fig. 4 shows the more detailed structure to the part of the numerical data digital filtering that will produce phase shift keyed signal of being used for of Fig. 1 TV transmitter 1.Error recovery encoder 14 provides digital signal to a rate buffer 20 with the serial data form.This encoder 14 preferably produces modified model RS code (Reed-Solomon Code) type; Carry out dual operation with rate buffer 20 as an interleaver.The interleaver operation of this rate buffer 20 is arranged the scanning original order of crosscut by the data in the row of the data of VSB BPSK data transmitter final emission of 12 while, and the respective horizontal scan line of composite video signal is by 8 emissions of VSB AM vision signal transmitter.So do like this so that with the modified model RS code influence of hinting obliquely at the data (rather than to the data in the row of hinting obliquely at the crosscut horizontal scanning line) along the row of horizontal scanning line is compared, the impulsive noise of composite video signal and mid-band frequency (it tends to have in the horizontal direction relevant) interference modified model seldom shows the bit of De-Suo Luomeng.In either case, rate buffer 20 is memories, its timing according to the rules offers one at alternate data image duration and the frame storage memory 21 that only writing during this period with bit, Frame is defined as the piece with 525 row code elements of chip rate appearance, described chip rate is a times of data line sweep speed, and this data line sweep speed is identical with the horizontal sweep wire rate of analog composite video signal.The BPSK code element is a plurality of bits, but the modified model RS code is added in code element normally 2 wherein ^NBit data, N are little positive integers, for example 3,4 or 5.The bit length that each modified model RS code is continued is chosen as less than 525 (for example 256 or 512), interrupts any one modified model RS code along the length of described sign indicating number more than once so that impulsive noise is unlikely.

The relative phasing of the horizontal scan line of data line and composite video signal is such, and promptly each data is consistent with a respective horizontal scan line of composite video signal in time.Each Frame takes place with the speed identical with each frame of the analog composite video signal that is provided by source 7, but because further in this manual disclosed reason, making the stagger horizontal scan line of 9 composite video signals of video signal frame of this Frame is very easily.Frame storage memory 21 is read first Frame, subsequently it is write, and before re-writing second Frame, again it is read, subsequently it is write, so that during consecutive numbers is to the respective frame of Frame, produce the output signal that is provided for partial-response filtering device 16 as input signal.Writing and read by frame storage access-control scheme 22 of rate buffer 20 and frame storage memory 21 controlled.

In transmitter 1, be used for counting a frame counter in eight frame periods and be used for during selected vertical blanking period (VBI) scan line, controlling of the insertion of ghost image elimination reference signal to composite video signal, this counter comprises (thus as one-level) mould 2 data frame counter 23, is used for carrying out timing each follow-up full frame storage memory 21 " reading " and " reading to write then " operation from image duration to Frame.Access-control scheme 22 also receives a data line count signal and receive a code element count signal from a symbol counter 25 from a data linage-counter 24, this access-control scheme 22 is applied to frame storage memory 21 according to reading addressing in row addressing and the row respectively.Data line counting and code element counting constitute complete addressing AD together, and access-control scheme 22 is applied to the frame storage memory 21 among Fig. 4.Circuit 22 also produce one be used for frame storage memory 21 write enabling signal NE and be used for rate buffer 20 write addressing WAD, what offer rate buffer 20 during writing reads that to address AD synchronous with the complete addressing AD that offers frame storage memory 21.When numerical data is sent selectively, circuit 22 also produce one be used for frame storage memory 21 read enabling signal RE.

Specifically, mode of operation is as described below." Frame counting " bit is provided for access-control scheme 22 from frame counter 23, only is used for producing " writing startup " signal when bit is 0 when mould 2 " Frame counting ".What access-control scheme 22 provided domination frame storage memory 21 reads to start and write enabling signal, is to operate by the write-after-read mode in 0 o'clock with convenient mould 2 " Frame counting " bit.When mould 2 " Frame counting " when bit is 1, access-control scheme 22 only provides reads enabling signal.

A final row decoder 27 receives " data line counting " signal and produces from data line counter 24 and is used for the control signal of partial-response filtering device 16 multiplexers 165 and the control signal that generation is used for multiplexer 196 (if filter 16 has used).This final row decoder 27 provides 0 output signal of a conduct " finally capable decoded result " with the response all values that the data line the final row is counted in the expression Frame, multiplexer 165 in the described 0 output signal domination filter 16 is (with multiplexer 169, if you are using), to realize common partial-response filtering by filter 16.Response Table show in the Frame " the data line counting " of final row, final linage-counter 27 provide one 1 with the multiplexer in the response filter 16 165 (with multiplexer 169, if you are using) in case utilize in this filter 16 initial condition for next Frame arrange 1-H delay line 164 (with 1-H delay line 168, loading if you are using).Mould 2 data frame counter 23 provide as " the mould 2 Frames counting " that replace input signal and give multiplexer 165, when providing one " 1 " to give multiplexer 165 as its control signal with the final row decoder 27 of box lunch, its selected 1-H of delivering to delay line 164 the input of writing connect.

Fig. 4 shows symbol timing circuit 30, and it also comprises 31, one zero crossing detectors of a voltage controlled oscillator (VCO) 32,255 counting decoder 33 and automatic frequency and phase control (AFPC) detector 34 except that symbol counter 25.This symbol counter 25 comprises 8 binary counting levels.Zero crossing detector 32 (being called the mean axis crossing detector may be more suitable) is as long as the mean axis of crossing them at a predetermined direction when the sine wave of oscillator 30 just produces a pulse simultaneously.This zero crossing detector 32 generally includes a limiting amplifier, and the pure oscillation that it responds VCO31 produces square wave; A difference engine is used to respond the transformation generation pulse of these square waves; With an amplitude limiter, be used to separate the pulse of same polarity, so that store access-control scheme 22 for purpose regularly is provided for frame.These pulses also are provided for symbol counter 25, so that by each continuous row counting, thereby produce " code element counting " signal that is provided to access-control scheme 22.33 decodings of 255 counting decoders reach 255 code element counting to produce a pulse.Be not to allow " code element counting " to be turned to arithmetic 0 simply, because whole counting is 2 integer power, each pulse from 255 counting decoders 33 can be according to the next pulse that is offered counter 25 by zero crossing detector 32 this counter 25 that is used to reset, like this, make " code element counting " to turn back to arithmetic 0.255 counting decoders 33 provide pulse to AFPC detector 34, so that compare to produce an AFPC voltage that is applied in to VCO31 with horizontal synchronization pulse H.So just finished a feedback loop, the frequency of oscillation that it adjusts VCO31 is that 255 times horizontal sweep line frequency is 4027972Hz.

To consider a kind of method of utilizing the synchronous counting of analog composite video signal by mould 2 data frame counter 23 and data counter 24 now.In this manual in described a kind of system digital signal receiver, preferably make the counter of regeneration " Frame counting " and analog composite video signal every frame row 9 initial synchronously, promptly be after the back edge of vertical sync pulse in the initial field of this frame just.In this case, in the beginning of the row 9 of every frame of this analog composite video signal, the counter of the regeneration in the digital signal receiver " data line counting " is reset to the appointment count value.In this part of transmitter 1 shown in Figure 4, the counting of finishing by mould 2 data frame counter 23 and data line counter 24 synchronously consistent with desired receiver reality.

The output signal of 255 counting decoders 33 is applied to one two input and door 36 as one first input signal.Platform synchronizing generator 9 provide vertical sync pulse V to after one along detector 36, it provides pulse in the end of the row 9 of composite video signal, and is used as second input signal in the mid point output signal of the row 271 of composite video signal and offers this and door 35." Frame end " pulse when being included in the end of row 9 of composite video signal with the response of door 35.In these " Frame end " pulses each is used as a trigger impulse and offers mould 2 data frame counter 23 (so that leading " Frame counting " signal) and also be provided for data line counter 24 so that its " data line counting " resets to the initial value of appointment.In practice, 255 counting decoders 33 can be removed, and can be provided for AFPC detector 34 and offer and door 35 from the carry pulse of the last binary counting level of symbol counter 25, rather than the output signal of this decoder 33 is provided.

The described transmitter of 1-4 is identical with transmitter described in the U.S. Patent application 08/141070 with reference to the accompanying drawings above.Below with reference to embodying accompanying drawing 5-8 of the present invention digital signal receiver is described.

Fig. 5 shows a digital signal receiver 37, is used for being buried in one of them TV signal and being used to extract this buried digital signal from the device receiving digital signals of a for example antenna 42.The television channel that channel selector 43 selections are detected by first detector in it, this first detector is a tunable down-converter (a general super heterodyne type), is used for selected TV signal is converted to one a group of intermediate frequency and a group of picture frequency.A video intermediate frequency (IF) filter 44 selects video intermediate frequency to offer an intermediate frequency (IF) amplifier 45 and elimination group of picture frequency as input signal.According to current custom, a surface acoustic wave (SAM) filter can be used as this video IF filter 44, and video IF amplifier 45 is formed in a monolithic or the integrated circuit (IC), need not whole tuning as a casacade multi-amplifier.Video IF amplifier 45 provides the video IF signal of amplification to an in-phase synchronization vision signal detector 46 with to a quadrature phase synchronization video wave detector 47.Oscillator 48 with nominal frequency 45.75 MHz vibration provides its vibration not have phase shift and offer quadrature phase synchronization video wave detector 47 to in-phase synchronization vision signal detector 46, and 90 ° of hysteresis phase shifts that provided by a phase-shift network 49 are provided.Oscillator 48 has the phase control (AFPC) in response to the automatic frequency of the output signal of quadrature phase synchronization video wave detector 47.Synchronization video wave detector 46 and 47 is comprised in the IC with the each several part of video IF amplifier 45 and oscillator 48 usually.Each vision signal detector 46 and 47 both can be that reinsertion of carrier type also can be true synchronized model.The homophase improvement composite video signal of being recovered by in-phase synchronization vision signal detector 46 is provided for a horizontal synchronization separator 50 and offers a vertical sync separator 51, and they improve recovery level and vertical sync pulse the composite video signal from homophase respectively.

It is known that the aspects of the digital signal receiver of being considered up to now 37 generally is decided to be the technical staff of TV receiver design field, wide and be the center with 45.25MHz although video IF filter 44 only preferably is made into approximately 3.5MHz.This video IF filter 44 provides sound accompaniment filtering in colourity filtering and the channel, and need not sound accompaniment filtering in colourity and the channel after quadrature phase vision signal detector 47.(when digital signal receiver 37 and television receiver are done together, utilize sound accompaniment filtering in the colourity that provided by the filtering after quadrature phase vision signal detector 47 and the channel, video IF filter 44 can be broadened.) bandwidth of quadrature phase vision signal detector 47 should slightly be wider than chip rate, so that the upper frequency in " afterbody " of unattenuated BPSK response.Quadrature phase vision signal detector 47 detection keying signals are attended by the NTSC composite video signal only is higher than the 750KHz place in frequency those parts.

In practice, digital receiver 37 will comprise that usually ghost image suppresses circuit, this circuit is not illustrated individually and significantly in Fig. 5, but it can to have the applying date be that August 20, application number in 1993 are type described in detail in 08/108,311 the U.S. Patent application.Each homophase and quadrature phase vision signal detector 46 and 47 comprise that (after the synchronous detector of itself) ghost image separately eliminates and equalization filter, they be included in other vision signal detector in synchronous detector itself after those filters of use similar.Two parallel adjustment to respond the calculating of making in the computer of adjustable parameter quilt that ghost image is eliminated filter, the adjustable parameter of two equalization filters is also adjusted to respond the further calculating in this computer by parallel.Ghost image is eliminated with reference to (GCR) signal and is extracted from selected vertical blanking period (VBI) scan line by the vision signal of in-phase synchronization vision signal detector 46 detections, when emission, this gcr signal expands to 4.1MHz on frequency, but it only expands to about 2.5MHz owing to its limited IF bandwidth in digital signal receiver.This gcr signal is digitized and offers computer as input signal, is used to calculate the adjustable parameter of ghost image elimination and equalization filter.In addition, direct current in quadrature phase vision signal detector 47 response or low frequency composition can be detected and be eliminated the basis of the adjustable parameter of filter as calculating ghost image.

In the digital signal filter device 37 of Fig. 5, the pulse that the pure oscillation that utilizes a sampling/symbol counter 103 countings to be received from a voltage controlled oscillator 105 by 104 responses of a zero crossing detector produces produces a sampling/code element count signal.Utilize symbol counter 52 countings to produce a code element count signal from the carry of overflowing of sampling/symbol counter 103.55 pairs of decoders reach 255 code element counting decoding, and to produce a pulse, it makes " sampling/code element counting " and " code element counting " turn back to arithmetic 0 according to the next pulse reset counter 103 and 52 that is offered counter 103 by zero crossing detector 104.The pulse that is produced by decoder 55 is provided for an AFPC detector 56, so as with separate by horizontal synchronization separator 50 and relatively by the adjustable several horizontal synchronization pulse H at several branches that postpone a symbol interval of a controllable delay line 57.Result relatively is low pass filtering in AFPC detector 56, to produce an automatic frequency and phase control (AFPC) voltage signal that is used for VCO105.These frequencies of arranging control to lock the vibration that VCO105 provides voluntarily are 16 * 256=4096 horizontal scan line frequency f doubly _H, i.e. 64447545Hz.Mean that about controlled oscillator employed " row locking " speech its frequency of oscillation is to decide than maintaining 15,734.264Hz the scan line frequency, this normally relatively realizes its oscillator frequency when being removed by a suitable factor and horizontal synchronization pulse by the AFPC circuit.

Be provided to a matched filter 58 by the keying signal of quadrature phase vision signal detector 47 detections and the part of following that is higher than the NTSC composite video signal at 750KHz place in frequency, it responds this keying signal, but only is the selected portion of the upper frequency composition of following 750KHz of composite video signal.Matched filter 58 provides a peak response, and the roll-offing of transition shaping unit of this peak response and transmitter median filter 18 is complementary, and is enough to reduce inter symbol interference with expansion PSK bandwidth.Matched filter 58 can also provide further peak response, with compensation since VSB BPSK 0.75 and 1.25MHz between more and more becoming monolateral band in nature and roll-offing upwardly extending frequency field in the frequency field that extends in the detection efficiency of the quadrature phase vision signal detector 47 that causes for monolateral band substantially in nature from 1.25MHz.Yet, because there is deviation each other in the vestigial sideband filter of different TV transmitter, the peak response that roll-offs of the detection effect of quadrature phase vision signal detector 47 finishes at each TV transmitter 1 may be preferably so be used for compensating, and it is by improving transition shaping filter 18 so that the suitable peak response except that the shaping transition to be provided.The preemphasis of this additional peak value at transmitter 1 place or binary system keying signal will (yet) increase the high frequency composition that the BPSK that launches together with luminance signal is higher than 0.75MHz.

Come the response of self-matching filter 58 to be used as input signal and be applied to an analog/digital converter (ADC) 106.Quadrature phase vision signal detector 47 does not recover the combination frequency signal that frequency is lower than 750KHz basically, and the BPSK coding is such: it does not have the zero-frequency composition.During the transmission of the TV image of few of energy, the BPSK part of quadrature phase synchronization video wave detector 47 responses will be from a reversal to another polarity in being higher than the 750KHz frequency.Therefore, ADC106 is a kind of device that can make the analog signal digital of the plus or minus utmost point; According to the present invention, ADC106 is a ∑-Δ transducer.

Specifically, ADC106 is the many bit sigma-Δ transducer with single bit feedback preferably, as (seeing 1990 IEEE SYMPSIUM ON CIRCUITS﹠amp by T.C.Leslie and B.Singh described in their paper " a kind of improved sigma-delta modulator algorithm "; SYSTEMS, 90 CH 2868-8900000-0372, PP.372-375).Sampler (it has moderate price) with 8 bit resolutions is taken a sample to error signal in a second order es-Δ feedback loop, and single bit feedback is used to make digital-to-analog conversion error minimization.Second order es-Δ feedback loop is unconditional stability.With 16 times to 256 sub-level scan line speed f _HChip rate cross sampling rate at 16: 1 as one error signal taken a sample, a pulse of each sampling receives from zero crossing detector 104 through a line 107, to respond it to intersecting the detection of vibration of zero axle from oscillator 105 at assigned direction.The numeral output of this sampler is provided for a FIR low pass filter in the transducer 106, with 16: 1 secondary samples, a pulse of each sampling was overflowed reception through a line 108 from the carry of each code element sampling counter (sample-per-symbol-couber) 103 to the digital response of this filter by a Secondary Sampler.This extraction has reduced subsequently required memory capacity in the decay part of digital comb filtering.With the secondary sample of chip rate (having arbitrary phase) is a kind of form that sync symbols detects, and its suppresses those compositions of the composite video signal that changes with chip rate are played response, but it has sampling with chip rate with quadrature phasing.

A single-bit ADC109, with 16 times to 256 sub-level scan line speed f _HChip rate sampling, in response to the pulse that provides by zero crossing detector 104 on the line 108, provide a sign bit to represent the polarity of these matched filter 58 responses in response to the response of matched filter 58.Described sign bit conduct input separately is provided for an exclusive-OR gate 111 when postponing a sampling in a latch 110.This exclusive-OR gate 111 detects the response of matched filter 58, provides this testing result to an impulse phase phase discriminator 67.This impulse phase phase discriminator 67 according to the suitable phasing of the zero crossing response of the vibration of the controlled oscillator 105 that detects by zero crossing detector 104, detect the skew of zero crossing of the response of the matched filter 58 that detects by exclusive-OR gate 111 selectively.Impulse phase phase discriminator 67 produces a control signal thus to skew (the sampled and maintenance) low-pass filtering of these selected detections, is used for adjusting postponing.Controlled delay line 57 is supplied with the horizontal synchronization pulse H that offers AFPC detection 56.When the response of 47 pairs of composite video signals of quadrature phase vision signal detector was contemplated to be null value, this selectable detection of being done by impulse phase phase discriminator 67 can realize at vertical blanking period.Correspondingly adjusted so that make the inter symbol interference minimum during the digitlization of its second order es-Δ error signal by the phasing of crossing sampling that sampler among the ADC107 is finished.

Each scheme that is used to adjust the phasing of capable locked-in oscillator has the type by co-inventor JungWan Ko exploitation.The AFPC ring of control frequency of oscillation of controlled oscillator 105 and phase place provides a filter function corresponding to the adjustable delay horizontal synchronization pulse H that provides from controlled delay line 57, and this filter function has been avoided between the adjustment period of phase place ADC106 regularly to present a kind of " low-frequency disturbance " or periodically significantly shortened.If attempt meticulous phase place adjustment in regularly then above-mentioned low-frequency disturbance takes place often at ADC106 self.

Vertical sync separator 51 provides lossy integration response in response to separated vertical sync pulse V to a threshold dector 68, and the threshold voltage of this detector is such selection: only surpassed when vertical sync pulse accumulates

Individual many scan lines and being less than

This threshold value is exceeded during individual scan line.The output signal of threshold dector 68 is used as one first input signal and offers an input and door 69, and only when the input signal of threshold dector 68 surpassed its threshold voltage, this threshold dector output signal was 1, otherwise it is 0.Decoder 55, it produces one for the end value of code element counting in every data line (in the end of horizontal scan line) " 1 ", otherwise produce one 0, it provide its output signal to door 69 as one second input signal.With the back edge of door 69 responses at initial the vertical pulse that begins to take place of composite video signal frame, these backs of response that corresponding " Frame end " pulse is provided along in each, but response is not played on the back edge of the vertical pulse that takes place between the initial separately of each frame and end.

Be provided to a mould 2 data frame counter 70 as counting input (CI) signal with " Frame end " pulse in door 69 responses, so that be ahead of " Frame counting " signal of a regeneration, it will be offseted by a scan line according to " Frame counting " signal at the transmitter place.As application number is 08/108, pointed in 311 the U.S. Patent application, arrange in TV transmitter 1 and in digital data receiver 37 to be used for synchronously that the best method of " Frame counting " is to eliminate with reference to (GCR) signal with reference to ghost image, this gcr signal reappears in the appointment arrangement of burst phasing and Bezier linear frequency modulation phasing in the 19th scan line of one four frame circulation.The single binary level counter 70 that produces mould 2 " Frame counting " will often be an one-level in the polybinary counter, and this polybinary counter produces mould 2 ^NFrame counting (wherein N is at least 2 positive integer), it is used to ghost image is eliminated adding up regularly with reference to (GCR) signal.

Also be used as (R) signal that resets with " Frame ends " pulse in door 69 response and offer a data linage-counter 71, arrive arithmetic 0 as " data line counting " (at this moment it should be 524) of its output signal regeneration to reset.Data line counter 71 is connected with the horizontal synchronization pulse H counting to providing from horizontal synchronization separator 50." data line counting " is used to be controlled to be choosing of the VBI scan line that comprises gcr signal in the circuit (not illustrating significantly among Fig. 5) that computer obtains data, and described computer (also not illustrating significantly among Fig. 5) is for balanced and be included in ghost images in vision signal detector 46 and 47 and eliminate filters and calculate adjustable filtering parameter.

A high pass frames comb filter 72 receives the digital response of ADC106 as input signal.This high pass frames comb filter 72 comprises a digital subtractor 73 and a digital frame memory 74, and response is provided to the sample of signal of its input port, in time provides those samples of signal at its output after one frame scan duration.Digital frame storage 74 is made into a RAM who operates by the write-after-read mode usually.This RAM receives " data line counting " from counter 71 and receives " code element counting " as code element addressing (SAD) as row addressing (LAD) with from counter 52.Subtracter 73 receives the sampling of the digitlization keying signal of present frame and stores the corresponding sampling of the digitlization keying signal that is received in preceding frame 74 as a subtrahend input signal as a minuend input signal with from frame from ADC106.Difference signal from subtracter 73 is the response of high pass frames comb filter 72, presents the frame residue brightness composition relevant with frame according to this response and is eliminated.

A high current comb filter 120 receives this response as its input signal.The current comb filter 120 of this height is matched filters that are used for the partial-response filtering device 160 of Fig. 2, and the filter 160 of Fig. 2 is used to the partial-response filtering device 16 in Fig. 1 transmitter 1.Current comb filter 120 inhibition of this height are attended by the composition of the composite video signal of detected keying signal, but are not existing change to row.The ad hoc structure of filter 120 9 and 10 will be described in this manual with reference to the accompanying drawings further.

Be used as analog signal that input signal offers ADC106 and partly represent the binary coding of keying signal; Therefore, it also is like this being used as the digital signal that input signal offers high pass frames comb filter 72.Be used as the binary coding that digital response that input signal offers high current comb filter 120 still is expressed as keying signal in the alternate data frame of valid data frame from high pass frames comb filter 72, subtracter 73 makes up two Frames that wherein respective digital sampling has same magnitude and opposite polarity differentially in those Frames.In intervention alternate data frame as the invalid data frame, being used as the digital response that input signal offers high current comb filter 120 from high pass frames comb filter 72 comes down to ternary, because in these Frames, subtracter 73 makes up wherein differentially, and the respective digital sampling has same magnitude and opposite polarity sometimes, and having two Frames of homophase amplitude and identical polar constantly at other, above-mentioned identical polar can be just also can be negative.In these invalid alternate data frames, come down to 5 grades from the digital response of the current comb filter 120 of height, but be nonsensical according to the bit decision of invalid data frame.In effective alternate data frame, be used as input signal and offer the binary coding that high digitized signal of passing through comb filter 120 is represented keying signal, and represent the ternary coding of keying signal from the respective digital response of the current comb filter 120 of height.

Bit decision circuit 75, the digital response that receives high pass comb filter 120 is as its input signal, and it correspondingly has three is the comparative group zone at center with-1 and 0 and+1 respectively.Bit decision circuit 75 comprises an absolute value circuit 751, and it produces the digital response of a correction, with the output signal of response from the current comb filter 120 of height.The digital response of the correction of absolute value circuit 751 is represented the binary coding of keying signal and is provided for a threshold dector 752.

Threshold dector 752 is the known a kind of bit decision circuit of digital communication technology field, is used to make the binary-coded bit decision about keying signal.Threshold dector 752 from absolute value circuit 751 receiving code flow filaments and make about this code element whether maximum possible be 0 or maximum possible is 1 judgement.Threshold dector 752 typically comprises a digital comparator, be arranged the effect of threshold dector, depend on whether surpass a threshold value, this threshold test result be used to control about this code element whether maximum possible be 1 or maximum possible is 0 judgement.Preferably such one type of threshold dector 752, the threshold value response Baud Length that promptly wherein is used for the threshold value judgement can automatically be adjusted.In above-mentioned situation, threshold dector 752 relative circuit are used to detect the average peak level of the code element stream that is provided by absolute value circuit 751, or its average level or two kinds of level all detect.Has the threshold value that relevant circuit is used for being used for foundation according to the numerical value that each detected level estimation is provided for comparator threshold test.The trace routine that is used for determining the bit decision threshold value is preferably in vertical blanking period and implements selectively, and this moment, composite video signal did not almost have contribute energy to give signal by 47 detections of quadrature phase video detector.

Be used as input signal from the code element stream of bit decision circuit 75 and offer a rate buffer 77, it is arranged by " Frame counting ", only accept from those wherein input samplings of the alternate frame that is not cancelled of keying signal, be not eliminated but do not present the luminance signal composition that interframe changes in this alternate frame.Digital sampling is provided for rate buffer 77 and is used for an error recovery decoder 78 by this rate buffer 77 with the generation of 1/2 chip rate with chip rate.Decoder 78 receives as the court verdict of being made by bit decision circuit 75 of serial data digital input data and to the serial data numerical data that correction is provided of error recovery wherein, these data are dateouts of digital signal receiver 37, and should be corresponding with the serial data numerical data in the source 13 that offers television transmitter 1 shown in Figure 1.

In the preferred embodiment of the digital signal receiver 37 that design can be used simultaneously with the transmitter 1 of use modified model RS code, described modified model RS code exerts an influence to the row of crosscut horizontal scan line, rather than the row along the data of horizontal scan line exerted an influence, rate buffer 77 is used for error recovery decoder 78 as a deinterleaver.The writing address generator of rate buffer 77 does not illustrate in Fig. 6.The data line counter 71 that reading address generator comprises to be provided " data line counting " and be provided in the rate buffer 77 among the RAM (S) respectively " the symbol counter 52 of code element counting as the row and column addressing.

Fig. 6 shows a digital signal receiver 38, and it is a kind of remodeling of the digital signal receiver 37 of Fig. 5, and also design can be used simultaneously with the transmitter 1 that uses partial-response filtering device 160 shown in Fig. 2.Compare with digital signal receiver 37, high pass frames comb filter 72 and high current comb filter 120 have opposite order in their mutual cascades in digital signal receiver 38.

Fig. 7 illustrates a digital signal receiver 39, and it is a kind of remodeling of the digital signal receiver 37 of Fig. 5, and design can be used simultaneously with the transmitter 1 that uses partial-response filtering device 166 shown in Fig. 3.In this digital signal receiver 39, high current comb filter 12 heels have another high current comb filter 130.One of high current pectination 120 and 130 cascade and use 0, the digital delay line of 1-H and the tap of 2-H timing period is identical, to provide input signal to a weighted sum network, in this network with (0.25): 0.5: (0.25) ratio weighting, to generate a filter response.

When the partial-response filtering device in the transmitter is shown in Figure 3 165 type or equal type, and when the digital signal filter device comprises that the three scan lines height of a type shown in Figure 7 passes through comb filter or equal type, for the psk signal of describing, high pass frames comb filter 72 is 5 grades at the digital response of valid data image duration basically, rather than actual ternary.Therefore, in Fig. 7, Fig. 5 or 6 bit decision circuit 75 (it have three respectively with-1 and 0 and-1 comparison value zone by the center) replaced by bit decision circuit 76, it has 5 is the comparison value zone at center with-2 ,-1,0 ,+1 and+2.This bit decision circuit 76 comprises an absolute value circuit 761, and it is to producing the digital response of a correction from the output signal of high pass frames comb filter 72.The digital response of the correction of absolute value circuit 761 represents to be superimposed upon the ternary coding of the keying signal on the direct current voltage reference, rather than the binary coding of expression keying signal, and the digital response of this correction is provided for a dual threshold detector 762 thus.This dual threshold detector 762 receives from the code element stream of absolute value circuit 761 and makes about whether this code element is likely 0, is likely 1 or be likely a judgement of 2, and 2 can regard 0 as.This dual threshold threshold dector 762 typically comprises two digital comparators, each is arranged as a single threshold detector, a threshold value that has is another twice, described dual threshold detector 762 also comprises the circuit of some simple logic, depends on that the threshold test result is used to adjudicate the identity of this code element.If two threshold value neither ones are exceeded, this logical circuit represents that this code element is likely one 0.If only surpass lower threshold value, this logical circuit represents that this code element is likely one 1.If low and higher threshold value all is exceeded, then this logical circuit represents that this code element is likely one 2 and it can regard 0 as.Preferably such one type of this dual threshold threshold dector 762 promptly wherein is provided for each comparator and is used for determining that the numerical value of the threshold value of threshold test is automatically adjusted corresponding to Baud Length.In this case, dual threshold threshold dector 762 has relevant circuit and is used for detecting by absolute value circuit 761, the average level of the code element stream that provides, or its average peak level, or two kinds of level are all detected.Have the circuit that is used for offering the numerical value of digital comparator, be used for the threshold value of threshold test separately to set up them according to each detected level estimation.The trace routine that is used for determining the bit decision threshold value is preferably in vertical blanking period and realizes selectively, and this moment, composite video signal did not almost have contribute energy to give signal by 47 detections of quadrature phase vision signal detector.

Fig. 8 shows a digital signal receiver 40, and it is a kind of remodeling of the digital signal receiver 39 of Fig. 7, and also design can be used simultaneously with the transmitter that uses partial-response filtering device 166 shown in Fig. 3.In this digital signal receiver 40, high pass frames comb filter 72 is placed on high current comb filter 120 and 130 each other after the cascade, rather than as digital signal receiver 39 in be placed on before them.The then high current comb filter 120 of a kind of wherein high pass frames comb filter 72 but are another embodiment of the present invention prior to the scheme of the current comb filter 130 of height.

Bit decision circuit 75 in Fig. 5 and 6 the digital signal receiver 37 and 38, what each all made " firmly " judgement with bit decision circuit 76 in the digital signal receiver 39 and 40 of Fig. 7 and 8 provides binary input signal to decoder 78, is used for the forward error correction that the implementation data communication enineer is called " hard decision ".Certainly, bit decision circuit 75 and 76 can be replaced by the circuit that input signal to the suitable decoder with many level is provided, and is called the forward error correction of " soft-decision " with the implementation data communication enineer.

Fig. 9 at length shows a kind of form 120 that high current comb filter 120 can adopt.An input of filter 127 is connected to the positive input of a difference input amplifier 123, and difference input amplifier 123 makes its output be connected to an output 124 of filter 121.The inverting input of difference input amplifier 123 receives one to the output delay of output signal response from multiplexer 126 from the output connection of an analog delay line 125, and the input that the output signal of multiplexer 126 is provided for delay line 125 connects.Analog delay line 125 provides the delay of the duration that equals a horizontal scan line.Such " 1-H " delay line constitutes (if simulating in nature) by a charge-coupled device (CCD) shift register usually, and difference input amplifier 123 is comprised in the electric charge sensing output stage of CCD shift register usually, injects input circuit with CCD shift register and its electric charge and is contained in a sheet type integrated circuit (IC).Multiplexer 126 generally is contained in and makes among the identical IC of field-effect transistors as transmission gate.

Multiplexer 126 receives control signal from a decoder 61, it with one " 1 " response from data line counter 71 reach with a Frame in " data line counting and with one " 0 " all other values of response " data line counting " of value of final data line correlation.Response decoder 61 is output signals of 1, and multiplexer 126 selects simulation 0 as its output response.Response decoder 61 is output signals of 0, and the detected bpsk signal that multiplexer 126 selects to be applied to input 122 is applied to the input link of 1-H delay line 125.

Figure 10 shows in detail the another kind of form 127 that high current comb filter 120 can be taked, the form shown in its replaceable Fig. 9, but do not comprise element 125 and 126.The output of a multiplexer 128 is connected to the inverting input of difference input amplifier 123 among Figure 10, this multiplexer 128 receives control signal from a decoder 62, it with one " 1 " response from data line counter 71 be reset to a Frame in " the data line counting " of value of primary data line correlation, with " all other values of data line counting; response decoder 62 is output signals of 1, multiplexer 128 select simulation 0 as its output response with " a 0 " response.Response decoder 61 is output signals of 0, and multiplexer 128 selects output signal to be applied to the positive input of difference input amplifier 123 from a 1-H analog delay line 129.From the output signal of 1-H analog delay line 129 are the delayed responses to the signal of the input 122 that is applied to filter 120, and this delay equals the duration of a horizontal scan line.

Figure 11 at length shows a kind of cascade form that high current comb filter 120 and 130 can be taked.Identical among high current comb filter 121 and Fig. 9; The current comb filter 130 of height among Figure 11 has element 132-136, and they are corresponding with the element 122-126 of high current comb filter 121, and carry out similar connection within each filter.

Figure 12 at length shows the another kind of cascade form that high current comb filter 120 and 130 can be taked.Identical among high current comb filter 127 and Figure 10; A high current filter 137 of combing among Figure 12 has element 138 and 139, and they are corresponding to the element 128 and 129 of comb filter 127 with high pass, and carry out similar connection in each filter unit.

Figure 13 shows a kind of form that it can be taked when rate buffer shown in Fig. 4 20 is used as an interleaver, and described interleaver is used for encoding from the modified model Reed-Solomon that error recovery encoder 14 provides.A Frame receives as a carry that provides from data frame counter 23 of its counting input (CI) signal counter 80 exports (CO) signal.Frame is to the alternately write and read of two Frame storage random access memory (RAM)s 81 of counter 80 controls and 82, and two memories 81 and 82 are as an interleaver that is used for the error recovery coding.RAM81 and 82 is written into from mistake correcting coder 14 with 1/2PSK speed interim at alternate frame, and address scan is to carry out by row with by every row code element.Each RAM81 and 82 reads frame storage memory 21 with PSK speed in to the interval at each frame, and described each frame is to following a frame that wherein is written at interval at interval, and address scan is to carry out by row with by each code element.Here the every row " code element " that refers to is PSK code element or bit, is not relevant with the modified model RS code of considering from a coding foothold 2 ^NBit symbol.

An address multiplexer 83 receives " data line counting " and receives " code element/row counting " as reading addressing from code element (being every capable code element) counter 25 from data line counting machine 24.Address multiplexer 83 receives " data rows counting " and receives " code element/column count " as writing addressing from every row symbol counter 85 from a data column counter.Zero crossing detector 32 provides trigger impulse to a trigger 86 with PSK speed, and it is used for providing alternately changing to every row symbol counter 85 as counting input (CI) of its output signal with 1/2PSK speed as a frequency divider.87 pairs of a decoder reaches the code element/column count decoding of full counting (525, suppose that every row code element counting is in 0 beginning), gives data rows counter 84 to provide one 1 as counting input (CI) signal.The output signal of decoder 87 is used as one first input signal and offers one two input or door 88, should or door 88 responses provide one 1 from 1 of decoder 87 and give every row symbol counter 85 as (R) signal that resets, be used to make code element/column count to reset to its initial value.

Arrive or second input signal of door 88 and (R) signal that resets that arrives data rows counter 84 by providing from one 3 input output response with door 89, when the response with door 89 was 1, it made " code element/column count " and " data rows counting " reset to their initial value.When expression that and if only if " data line counting " arrives this Frame final capable, decoder 260 provide a logical one to the first input end of door 89; Otherwise this decoder 260 provides a logical one to output signal to and door 89 as it.(when using partial-response filtering device 160 in the transmitter 1, decoder 260 can be the decoder 270 of Fig. 4, and during therefore and if only if " data line counting " this Frame of expression arrival final capable, decoder 27 is used to provide a logical one).From the output signal of the final symbol decoding device 33 of data line and from the mould 2 Frames counting of data frame counter 23 be applied in to door 88, as two in addition in its three input signals.Only when in odd-numbered frame, arriving the capable final code element of final data, just before even frame arrives when in RAM81 or 82 selected one will be read in the frame storage memory 21 by data line ground the time, export with door 88 that to respond be one 1.

From Frame mould 2 Frames of counter 80 are " 1 " to counting, just arrange address multiplexer 83 and select RAM81 is read addressing, and select RAM82 is write addressing.From Frame mould two Frames of counter 80 for just making RAM81, " 1 " are pursued data line sense data to frame memory 21 to counting, and the binary bit complement code of that counting is that " 0 " just can write RAM82 to data by data rows from error recovery encoder 14.

From Frame mould two Frames of counter 80 are " 0 " to counting, just arrange address multiplexer 83 and select RAM82 read addressing and select RAM81 is write addressing.From Frame to mould two Frames of counter 80 to counting for " 0 " can make RAM82 to frame memory 21 by data line ground sense data, and the complement of two's two's complement of that counting is that " 1 " just can write RAM81 to data by data rows from error recovery encoder 14.

A kind of form of the rate buffer 77 shown in arbitrary figure of Figure 14 presentation graphs 5-8, this moment, it was used as the deinterleave memory access of the modified model Reed-Solomon coding that code element decision circuit circuit 75 or 76 is provided.Frame receives from execution (CO) signal of data frame counter 70 counter 90 and imports (CI) signal as its counting.Frame is that two Frames of the non-interlace device of error correction coding are stored alternately writing and reading of RAM91 and 92 to counter 90 control actions.RAM91 and 92 just writes data during the even frame that replaces, the data that are written to RAM91 and 92 are to be provided by code element decision circuit 75 or 76 speed with PSK, and address scan is line by line and is that the whole code elements of every row are carried out." code element " of every row is meant PSK code element or bit, be not meant from the viewpoint of coding consider relevant with follow-on Reed-Solomon sign indicating number 2 ^NBit symbol.RAM91 and 92 each at alternate frame at interval data being read frame memory 21 with 1/2PSK speed, address scan is by to carrying out, and is to carry out with whole code elements of every row.

Address multiplexer 93 receives from the data line of data line counter 71 and counts and count as writing addressing from code element/row of code element (that is: the code element of every row) counter 52, and address multiplexer 93 receives from the data rows counting of data counter 94 with from code element/column count conduct of every row symbol counter 95 and reads addressing.Zero crossing detector 104 offers the bistable multivibrator 96 that is triggered to trigger impulse with PSK speed, and this oscillator is imported (CI) so that alternately its output signal is delivered to every row symbol counter 95 with 1/2PSK speed as counting as a frequency divider.97 pairs in decoder reaches the code element/column count decoding of full counting (supposing that the zero-based counting of every row is 525), so that provide " 1 " as counting input (CI) signal to data column counter 94.That the signal of decoder 97 output is delivered to 2 inputs or door 98 is as the 1st input signal, or door 98 is corresponding to " 1 " from decoder 97, provide a logic " 1 " to give every row symbol counter 95 again, so that code element/column count reset to its initial value as (R) signal that resets.

According to from 3 inputs and door 99 output to or door 98 the 2nd input signal is provided and provides (R) signal that resets to data rows counter 94, when it was output as " 1 ", code element/column count and data rows counting all reset to their initial values separately.When and have only when data line counting shows the last column that arrives Frame, decoder 61 just provides logic " 1 " to the 1st input with door 99, on the contrary decoder 61 is to providing logic " 0 " as its output signal with door 99.Be sent to and door 98 two input signals in addition from the output signal of the last code element decoder 55 of data line mould 2 Frames counting as its three input signals from data frame counter 70.A selected RAM is when sign indicating number decision circuit 75 or 76 writes data by data line in RAM91 and 92, when only in the odd-numbered frame that just writes before arriving even frame, reaching last symbol of last data line, be only corresponding " 1 " with the output of door 98.

Is " 1 " to mould two Frames of counter 90 to counting from Frame, and it is just arranged multichannel address translator 93 and selects RAM91 read addressing and select RAM92 is write addressing.From Frame to the Frame of counter 90 to counting be " 1 " can make RAM91 data by data rows read in the error recovery decoder 78.2 inputs 101 are delivered to RAM92 to logic " 1 " as writing (WE) signal selectively with door, and this logic " 1 " is corresponding to all being that the Frame counting of " 0 " and Frame are to counting the complement of two's two's complement from counter 70 and 90.This WE signal can make RAM92 write data from code element decision circuit 75 or 76 with pursuing data line.

Is " 0 " to mould two Frames of counter 90 to counting from Frame, and it is just arranged multichannel address translator 93 and selects RAM92 read addressing and select RAM91 is write addressing.Is that " 0 " can make RAM92 pursue data rows ground data read in error recovery decoder 78 to the Frame of counter 90 to counting from Frame.2 inputs 102 are delivered to RAM91 to logic " 1 " as writing (WE) signal selectively with door, and this logic " 1 " is corresponding to be the Frame counting of " 0 " and be the complement of two's two's complement of Frame to counting of " 1 " from counter 90.This WE signal can make RAM91 write data by data line from code element decision circuit 75 or 76.

The gap that stays during for the invalid signals alternate frame that occurs in the frame comb filtering that is filled in discarded paired frame and the speed to buffer that carries out in digital signal receiver 37-40 can be after frame comb filterings and carried out before the code element decision circuit.Yet because frame memory only needs a bit depth rather than the multidigit degree of depth, so speed to buffer carries out after being preferably in sign determination.Because for the frame memory that separates, do not need speed to buffer, so speed to buffer carries out with one of deinterleave access before being preferably in the error recovery decoding.Separate the place of carrying out at speed to buffer and deinterleave, if frame memory is a two-port RAM with read port of dressing up with shift memory, speed to buffer just can only carry out with a frame memory so, and the serial classification of this shift register can be passed through the read/write port delegation of packing into from the access part parallel ground of this RAM simultaneously.

Figure 15 represents that this converter can be used for any digital signal receiver of Fig. 5-8 by the monocycle ∑-Δ converter 200 of the general type of Leslie and Singh description.The high speed converter 201 that this ∑-one of Δ converter 200 usefulness have 8 bit resolutions constitutes as the basic transformation device.For contraposition latch 203 provides digital feedback signal, wired intake device 202 that the highest order (being flag bit) of the digital output signal of a high speed converter 201 is arranged, D/A converter 204 is for conversion into positive or negative analog voltage level to the latch content of position latch 203, produces analog feedback signal therefrom.Analog subtracter 205 cuts this analog feedback signal from delivering to ∑-Δ converter 200 inputs 206 and being delivered to by sampling switch (or sampler) 207 sampling the input signal of subtracter 205, this difference output signal from subtracter 205 is exactly an analog error signal.Analog adder 208 is postponed it to be added on the analog error signal after a sample time by sample-and-hold circuit 209 with output signal again, produce therefrom adder 208 and output signal.From analog adder 208 with output signal be that high speed converter 201 quantizes the result of integration to the integration of the time of analog error signal.D/A converter 204, analog subtracter 205, sampler 207, analog adder 208 and sampling retainer 209 help to constitute switched-capacitor circuit.

The error of using single bit feedback to produce compensates with the method that Leslie and Singh advise, wired intake device 202 of the highest order of the digital output signal of high speed converter 201 (being flag bit) cooperate with wired " 0 " expander 213 filter out time high-order so that produce 8 subtrahends as the digital subtractor 214 of its minuend input signal for the 8 complete bit digital output signals that receive high speed converter 201.After postponing a sample time from this difference output signal of subtracter 214 with one group of 8 latch in parallel 215, (with the digital output signal of high speed converter 201) addition produces 9 and a signal delivering to low pass sum filter 219 in digital adder 218.The corresponding signal of sum filter 219 is by crossing the output 221 of delivering to ∑-Δ converter 220 after sampler 220 carried out taking a sample with chip rate.

Figure 16 represents that this converter 300 can be used for any one digital signal receiver of Fig. 5-8 and comprise a high speed converter 301 as 8 bit resolutions of basic transformation device by the dicyclo ∑-Δ converter 300 of the general type of Leslie and Singh description.For contraposition latch 303 provides digital feedback signal, wired intake device 302 that the highest order (being flag bit) of the digital output signal of a high speed converter 301 is arranged, D/A converter 304 is for conversion into positive or negative analog voltage level to the latch content of latch 303, produces analog feedback signal therefrom.From the input 306 of delivering to ∑-Δ converter 300 and delivered to by sampling switch (or sampler) 3-7 sampling the input signal of subtracter 305 and cut, this difference output signal from subtracter 305 is exactly an analog error signal to analog subtracter 305 this analog feedback signal.Analog adder 308 is postponed it to be added on the analog error signal after a sample time by sample-and-hold circuit 309 with output signal again, produce therefrom adder 308 and output signal.From analog adder 308 with output signal be that the result of an integration delivers to analog subtracter 310 as the minuend signal to the integration of the time of analog error signal, analog subtracter also receives analog feedback signal as subtrahend.Adder 311 is postponed it to be added on the analog error signal of integration after the sample time by sample-and-hold circuit 312 with output signal, with produce analog adder 311 and output signal.From analog adder 311 with output signal be dual-integration to the time of analog error signal, the result behind this dual-integration is quantized by high speed converter 301.D/A converter 304, analog subtracter 305 and 310, sampler 307, analog adder 308 and 311 and sample-and-hold circuit 309 and 312 help constituting switched-capacitor circuit.

The error of using single bit feedback to produce compensates with the method that Leslie and Singh propose, wired intake device 302 of the highest order of the digital output signal of high speed converter 301 (being flag bit) cooperate with " 0 " expander 313 filter out time high-order so that produce 8 subtrahends as the digital subtractor 314 of its minuend input signal for the 8 complete bit digital output signals that receive high speed converter 301.Error amount output signal from subtracter 314 postpones a sample time and further postpones a sample time with one group of 8 latch in parallel 316 with one group of 8 latch in parallel 315.The content of the content of the digital output signal of high speed converter 301, double with wired single-bit displacement device 317 8 and interlocker group 315 and 8 bank of latches 316 in parallel is added up with digital adder 318 and is produced 10 and an output signal delivering to low pass sum filter 319, and the corresponding signal of 320 pairs of sum filters 319 of mistake sampler is crossed the output 321 of delivering to ∑-Δ converter 300 after the sampling.

The inventor is described to the preferred embodiment of the invention, but the those of ordinary skill of communication system, transmitter and receiver design field can be designed different embodiments of the present invention by understanding above-mentioned invention, and this all should derive from the design of this specification accompanying Claim coverage.

Claims (50)

1. digital signal receiver, be used in binary phase shift keying (BPSK) modulation sideband, at suppressed carrier and send in the system of numeric code with the serial of video carrier combination of transmitted mode, the amplitude of video carrier is by the composite video signal modulation, suppressed carrier becomes 90 ° of phase differences with described video carrier, said digital signal receiver comprises:

The detector arrangement of the analog detector response that is made of receiver response of wanting and undesired receiver response is provided in response to said combination of transmitted, this detector arrangement is to binary phase shift keying (BPSK) detection of said suppressed carrier, produce the said receiver response of wanting have said undesired receiver response therefrom, said undesired receiver response be by width of cloth accommodation frequently the remainder branch of the composite video signal that obtains of carrier detection constitute;

For providing the digitlization receiver response to be used for a ∑-Δ A/D converter of analog detector responding digitalization; And

A digital comb filter that receives said digitlization receiver response is in order to produce the response that mainly depends on the said receiver response of wanting and do not rely on undesired receiver response.

2. according to the digital signal receiver of claim 1, it is characterized in that said digital comb filter is a high pass digital frame comb filter.

3. according to the digital signal receiver of claim 2, it is characterized in that ∑-Δ A/D converter comprises:

An analog subtracter, it has one to be used for receiving the minuend input link of said analog detector response, a subtrahend input link and an output link that is used to provide the analog error signal that is proportional to the difference between said receiver response and the said analog feedback signal that is used for receiving analog feedback signal;

Be used for to said analog error signal about the time intercropping at least one integration device;

Be used for a fast transformation device that carries out the analog error signal behind at least integration of time is for conversion into digital sampling with many bit resolutions;

The highest order that is used for receiving each said digital sampling is transformed into said analog feedback signal by a D/A converter as digital feedback signal and it;

For compensation just the said digital feedback signal of single-bit proofread and correct said digital sampling, and produce the device of the digital sampling of proofreading and correct thus; With

Produce the device of the sampling of digitlization receiver response at the weighted accumulation of stipulating of crossing the digital sampling of carrying out said correction in the sampling period.

4. according to the digital signal receiver of claim 1, it is characterized in that said digital comb filter is a high pass numeral row comb filter.

5. according to the digital signal receiver of claim 4, it is characterized in that ∑-Δ A/D converter comprises:

An analog subtracter, it has one to be used for receiving the minuend input link of said analog detector response, a subtrahend input link and an output link that is used to provide the analog error signal that is proportional to the difference between said receiver response and the said analog feedback signal that is used for receiving analog feedback signal;

Be used for to said analog error signal about the time intercropping at least one integration device;

Be used for a fast transformation device that carries out the analog error signal behind at least integration of time is for conversion into digital sampling with many bit resolutions;

The highest order that is used for receiving each said digital sampling is transformed into a D/A converter of said analog feedback signal as digital feedback signal and it;

For compensation just the said digital feedback signal of single-bit proofread and correct said digital sampling, and produce the device of the digital sampling of proofreading and correct thus; With

Produce the device of the sampling of digitlization receiver response at the weighted accumulation of stipulating of crossing the digital sampling of carrying out said correction in the sampling period.

6. according to the digital signal receiver of claim 1, it is characterized in that said digital comb filter is a high pass digital frame comb filter, be connected in series mutually by a high pass numeral row comb filter thereafter.

7. according to the digital signal receiver of claim 6, it is characterized in that ∑-Δ A/D converter comprises:

An analog subtracter, it has one to be used for receiving the minuend input link of said analog detector response, a subtrahend input link and an output link that is used to provide the analog error signal that is proportional to the difference between said receiver response and the said analog feedback signal that is used for receiving analog feedback signal;

Be used for to said analog error signal about the time intercropping at least one integration device;

Be used for a high speed converter that carries out the analog error signal behind at least integration of time is for conversion into digital sampling with many bit resolutions;

The highest order that is used for receiving each said digital sampling is transformed into a D/A converter of said analog feedback signal as digital feedback signal and it;

For compensation just the said digital feedback signal of single-bit proofread and correct said digital sampling, and produce the device of the digital sampling of proofreading and correct thus; With

Produce the device of the sampling of digitlization receiver response at the weighted accumulation of stipulating of crossing the digital sampling of carrying out said correction in the sampling period.

8. according to the digital signal receiver of claim 6, it is characterized in that also comprising:

Reception from the response of said high pass numeral row comb filter and the identity of judging each numeric code in order to produce the code element decision circuit of Bit String digital signal response.

9. according to the digital signal receiver of claim 1, it is characterized in that said digital pectination filter is a high pass numeral row comb filter, is connected in series mutually by a high pass digital frame comb filter thereafter.

10. according to the digital signal receiver of claim 9, it is characterized in that ∑-Δ A/D converter comprises:

An analog subtracter, it has one to be used for receiving the minuend input link of said analog detector response, a subtrahend input link and an output link that is used to provide the analog error signal that is proportional to the difference between said receiver response and the said analog feedback signal that is used for receiving analog feedback signal;

Be used for to said analog error signal about the time intercropping at least one integration device;

Be used for a fast transformation device that carries out the analog error signal behind at least integration of time is for conversion into digital sampling with many bit resolutions;

The highest order that is used for receiving each said digital sampling is transformed into a D/A converter of said analog feedback signal as digital feedback signal and it;

For compensation just the said digital feedback signal of single-bit proofread and correct said digital sampling, and produce the device of the digital sampling of proofreading and correct thus; With

Produce the device of the sampling of digitlization receiver response at the weighted accumulation of stipulating of crossing the digital sampling of carrying out said correction in the sampling period.

11., it is characterized in that also comprising according to the digital signal receiver of claim 9:

In order to receive from the response of said high pass digital frame comb filter and to judge that the identity of each numeric code is so that produce the code element decision circuit of Bit String digital signal.

12. digital signal receiver, be used in suppressed carrier binary phase shift keying (BPSK) modulation sideband, and send in the system of digital signal with the serial of video carrier combination of transmitted mode, the amplitude of video carrier is by the composite video signal modulation, suppressed carrier becomes 90 ° of phase differences with described video carrier, said digital signal receiver comprises:

The detector arrangement of analog detector response is provided in response to said combination of transmitted, two of this detector arrangement detection suppressed carrier carries out phase shift keying (BPSK), produce the receiver response of wanting have undesired receiver response therefrom, said undesired receiver response be by width of cloth accommodation frequently the remainder branch of the composite video signal that obtains of carrier detection constitute;

In order to be the ∑-Δ A/D converter of digital detector response to said analog detector response transform;

The end that is connected in series of high pass numeral row comb filter and connected high pass digital frame comb filter, in order to receive said digitized receiver response and to provide compound comb filter response from the described end that is connected in series, described combination comb filter response has a plurality of level values corresponding to its each numeric code; With

In response to the code element decision circuit of said combination comb filter response, in order to judge the identity of each numeric code, so that produce a Bit String digital signal response.

13. according to the digital signal receiver of claim 12, it is characterized in that said high pass digital frame comb filter be connected in series in after the said high pass numeral row comb filter before and comprise:

Input link in order to the said high pass digital frame comb filter that receives said digitlization receiver response;

In order to the response of high pass digital frame comb filter is provided to the output link of said high pass numeral row comb filter as input signal;

One 1 frame of digital delay line, in its said time interval of digitlization wave detector device operating lag in order to said high pass digital frame comb filter input link is received, this equals the frame scan duration of said composite video signal at interval; And

The 1st digital subtractor, it has the 2nd input link that a reception connects without actual time delay from the 1st input link through the response of time-delay of a said frame of digital delay line, from the input link of said high pass digital frame comb filter and the output link of delivering to the output of said high pass digital frame comb filter corresponding to the difference signal of the signal of the 1st and the 2nd link of said the 1st subtracter.

14., it is characterized in that said 1 frame delay line is the random-access memory (ram) by the write-after-read mode operation according to the digital signal receiver of claim 13.

15., it is characterized in that said high pass numeral row comb filter comprises according to the digital signal receiver of claim 13:

Receive the input link of the said high pass numeral row comb filter of said high pass digital frame comb filter response;

The output link of the said high pass numeral row comb filter of said compound comb filter response is provided;

The digital delay line of 1H, it is used for handle in described time interval of high pass digital frame comb filter operating lag that the input of said high pass numeral row comb filter is received, and this equals the duration of the horizontal scanning line of said composite video signal at interval; And

The 2nd digital subtractor with the 1st input link, the 2nd input link and output link, the 1st input link is in order to receive the time-delay response from the 1H digital delay line, the second input link connects the input of said high pass numeral row comb filter without actual time delay, the output link is used for that the difference of the signal of the 1st and the 2nd input link of said the 2nd subtracter is delivered to said high pass numeral and goes the output of comb filter.

16., it is characterized in that said code element decision circuit comprises according to the digital signal receiver of claim 15:

Absolute value circuit with an input link and an output link, input are used for receiving said compound comb filter response, and output is used to provide calibration response; And

Threshold dector with an input link and an output link, this input link is in order to receive the said calibration response from said absolute value circuit, this output link provides the digital signal bit, when said calibration response surpasses threshold level, each bit is in the 1st state, when said calibration response was no more than said threshold level, each bit was in the 2nd state.

17., it is characterized in that said high pass numeral row comb filter comprises according to the digital signal receiver of claim 13:

Receive the input link of the said high pass numeral row comb filter of said high pass digital frame comb filter response;

The output link of the said high pass numeral row comb filter of said compound comb filter response is provided;

The one 1H digital delay line, it is used for handle in said time interval of high pass digital frame comb filter operating lag that the input link of said high pass numeral row comb filter is received, this equals the duration of the horizontal scanning line of said composite video signal at interval;

The 2nd digital subtractor with the 1st input link, the 2nd input link and output link, the 1st input link is in order to receive the time-delay response from a said 1H digital delay line, the 2nd input connects the input link of said high pass numeral row comb filter without actual time delay, the output link is used to provide the difference that the 1st and the 2nd of said the 2nd subtracter is imported the signal of link;

Be used for one of the difference operating lag of said the 2nd digital subtractor is equaled the 2nd 1H digital delay line in the time interval of 1H duration; With

The 3rd digital subtractor with the 1st input link, the 2nd input link and an output link, the 1st input link is used for receiving the response from the time-delay of the 2nd 1H digital delay line, the 2nd input link connects the output link of the 3rd digital subtractor without actual time delay, and the output link is used for that the difference of the signal of the 1st and the 2nd input link of said the 3rd digital subtractor is delivered to said high pass numeral and goes the output link of comb filter.

18., it is characterized in that said code element decision circuit comprises according to the digital signal receiver of claim 17:

Have one and receive the input link of said compound comb filter response and the absolute value circuit of an output link that calibration response is provided; With

Dual threshold detector with an input link and an output link, this input link receives the said calibration response from the output link of said absolute value circuit, this output provides the digital signal bit, each bit is in the 1st state when said calibration response is no more than the 2nd threshold level that is higher than the 1st threshold level above the 1st threshold level, when said calibration response was no more than the 1st threshold level or promptly surpasses said the 1st threshold level again above the 2nd threshold level, each bit was in the 2nd state.

19. according to the digital signal receiver of claim 12, it is characterized in that said high pass digital frame comb filter is serially connected in after the said high pass numeral row comb filter, it comprises:

Be used for receiving input link from the said high pass digital frame comb filter of the response of said high pass numeral row comb filter;

Be used to provide the output link of the said high pass digital frame comb filter of said compound comb filter response;

1H frame of digital delay line, it is used for going comb filter time interval of operating lag from said high pass numeral of receiving on said high pass digital frame comb filter input link, and this equals the frame scan duration of said composite video signal at interval; And

The 1st digital subtractor with the 1st input link, the 2nd input link and an output link, the 1st input link is used for receiving the time-delay response from said 1 frame of digital delay line, the 2nd input link is received the input link of said high pass digital frame comb filter without actual time delay, and the output link is imported the output link that signal numerical value on the link is delivered to said high pass digital frame comb filter to the 1st and the 2nd of the 1st digital subtractor.

20., it is characterized in that said 1 frame delay line is the random-access memory (ram) according to the write-after-read mode operation according to the digital signal receiver of claim 19.

21., it is characterized in that said high pass numeral row comb filter comprises according to the digital signal receiver of claim 19:

Be used for receiving the said high pass numeral row comb filter input link of said digitlization receiver response;

Receive the input link of the said high pass numeral row comb filter of said high pass digital frame comb filter input;

The 1H digital delay line, it is used for the detector of receiving on the input of said high pass numeral row comb filter of wanting of not wanting receiver response that has is postponed a time interval, and this time interval equals the duration of the horizontal scanning line of said composite video signal; And

The 2nd digital subtractor with the 1st input link, the 2nd input link and output link, the 1st input link is used for receiving the delayed response from said 1H delay line line, the 2nd input link is received the input link of said high pass numeral row comb filter without actual time delay, said output link is used for the signal difference of the 1st and the 2nd input of said the 2nd digital subtractor is delivered to said high pass numeral row comb filter.

22., it is characterized in that said code element decision circuit comprises according to the digital signal receiver of claim 21:

Absolute value circuit with an input and an output, said input is in order to receive said compound comb filter response, and said output is in order to provide calibration response; And

Threshold dector with an input link and an output link, said input link receives the calibration response from said absolute value circuit output link, said output link provides the digital signal bit, when said calibration response surpasses threshold level, each bit is in the 1st state, and when said calibration response was no more than said threshold value, each bit was in the 2nd state.

23., it is characterized in that said high pass numeral row comb filter comprises according to the digital signal receiver of claim 19:

Receive the said input link of crossing the said high pass numeral row comb filter of sampler response;

Receive the output link of the said high pass numeral row comb filter of said high pass digital frame comb filter input link;

The one 1-H digital delay line, it is used for time interval of the operating lag that has the wave detector of wanting of not wanting receiver response of receiving on the input of said high pass numeral row comb filter, this time interval equals the 1-H duration of the horizontal scanning line of said composite video signal;

The 2nd digital subtractor with the 1st input link, the 2nd input link and an output link, the 1st input link receives the time-delay response from the 1st 1-H digital delay line, the 2nd input is received the input of said high pass numeral row comb filter without actual time delay, and said output link is used to provide the difference of the signal on the 1st and the 2nd input of said the 2nd digital subtractor;

The 2nd 1-H digital delay line, it is used in time interval of the difference operating lag of the 2nd digital subtractor, and this time interval equals the 1-H duration; And

The 3rd digital subtractor with the 1st input link, the 2nd input link and an output link, the 1st input link is used for receiving the time-delay response from said the 2nd 1-H digital delay line, the 2nd input link is received the output link of said the 2nd digital subtractor without actual time delay, and said output link is used for the signal difference on said the 3rd digital subtractor the 1st and the 2nd input is provided to the output of the capable comb filter of said high pass numeral.

24., it is characterized in that said code element decision circuit comprises according to the digital signal receiver of claim 23:

Absolute value circuit with an input link and an output link, said input link are used for receiving said compound comb filter response, and said output link provides calibration response; And

Dual threshold detector with an input link and an output link, the input link is used for receiving the calibration response from the output link of said absolute value circuit, the output link is used to provide the digital signal bit, when being no more than the 2nd threshold level when said calibration response the 1st threshold level, each bit is in the 1st state, and each bit is in the 2nd state when said calibration response is no more than said the 1st threshold level or surpasses the 1st and the 2nd these two threshold levels.

25. digital signal receiver, be used in the system of transmitting digital information in the binary phase shift keying modulation sideband, of suppressed carrier, said suppressed carrier becomes 90 ° of phase differences with video carrier, the amplitude of video carrier is by the composite video signal modulation, and said digital signal receiver comprises:

Provide the tuner of intermediate-freuqncy signal, the selected radiofrequency signal that this intermediate-freuqncy signal constitutes in response to the suppressed carrier by width of cloth accommodation frequency carrier wave and binary phase shift keying;

To the intermediate frequency amplifier of said intermediate-freuqncy signal response, said intermediate frequency amplifier comprises filtering and amplifying unit and the response of the intermediate frequency amplifier through amplifying is provided;

The 1st controlled oscillation circuit, the intermediate frequency video carrier that it produces homophase and phase quadrature in order to intermediate frequency and average phase according to the control of frequency error signal and phase error signal;

Receive the homophase vision signal detector of said intermediate frequency amplifier response through amplifying, in order to according to the said homophase intermediate frequency video carrier of sending here therefrom synchronous detection go out composite video signal;

Receive 90 ° of phase difference vision signal detectors of said intermediate frequency amplifier response through amplifying, in order to going out the bi Phase Shift Keying signal according to said 90 ° of phase difference intermediate frequency video carrier synchronous detections of sending here, this binary phase shift keying signal partly is combined among 90 ° of phase difference vision signal detectors responses from said 90 ° of phase difference wave detectors by the composite video signal that comprises said frequency and phase error signal;

Horizontal synchronization pulse from the detection of homophase vision signal detector to composite video signal the horizontal synchronization separator separated;

The 2nd controlled oscillator circuit, it produces clock oscillation with the frequency and the phase place of said horizontal synchronization pulse control of separating, and this frequency is the frequency of multiple-symbol speed concerning said binary phase shift keying signal;

∑-Δ A/D converter with an input link and an output link, the input link receives said 90 ° of phase difference vision signal detectors response, the output link supplies to the sampled signal that said 90 ° of phase difference vision signal detectors respond to the digitlization response with the chip rate of said binary phase shift keying signal, and this sampled signal is taken a sample with said clock oscillation;

A digital comb filter, it receives the response of said digitized 90 ° of phase difference vision signal detectors of sending here with the chip rate of said binary phase shift keying signal, and digital comb filter response offered said binary phase shift keying signal, be suppressed in response to the digital comb filter response of the bound fraction of said composite video signal; And

The code element decision circuit is in order to receive said digital comb filter response and to judge according to the code element that said binary phase shift keying signal sends.

26., it is characterized in that ∑-Δ A/D converter comprises according to the digital signal receiver of claim 25:

Difference input amplifier with the 1st input link, the 2nd input link and an output link, the 1st input link receives said analog detector response, the 2nd input link analog feedback signal, the output link provides the analog error signal that is proportional to the difference between said detection response and the said analog feedback signal;

Be used for said analog error signal is transformed into and have the fast transformation device that many bits are differentiated the sampling of special digital error signal;

A D/A converter, the highest order that is used for receiving said digital error signal is transformed into said analog feedback signal as digital feedback signal and it, and

During the sampling period excessively of regulation, be weighted the device of the said sampling of the digital error signal that adds up, so that produce the sampling of digitlization receiver response.

27., it is characterized in that said digital comb filter comprises that the back is connected to the high pass digital frame comb filter of a high pass numeral row comb filter according to the digital signal receiver of claim 25.

28., it is characterized in that said high pass digital frame comb filter comprises according to the digital signal receiver of claim 27:

The input link of said high pass digital frame comb filter is used for the sampling of said chip rate reception to the said digitlization response of the sampling of said 90 ° of phase difference vision signal detectors;

The output link of said high pass digital frame comb filter is used for the response of high pass digital frame comb filter is offered the input signal of said high pass numeral row comb filter as it;

1 frame of digital delay line is spent sampler time interval of operating lag in order to said high pass digital frame comb filter is imported receive on the link described, and this time interval equals the frame scan duration of said composite video signal; And

The 1st digital subtractor with the 1st input link, the 2nd input link and an output link, the 1st input link receives the response through time-delay from said 1 frame of digital delay line, the 2nd input link is received the input link of said high pass digital frame comb filter without actual time delay, and said output offers the 1st and the 2nd signal difference of importing link of said the 1st digital subtractor the output link of said high pass digital frame comb filter.

29., it is characterized in that said high pass numeral row comb filter comprises according to the digital signal receiver of claim 28:

Receive the said high pass numeral row comb filter input link of said high pass digital frame comb filter response;

The said high pass numeral row comb filter output link of described compound comb filter response is provided;

The 1-H digital delay line, in order in a said time interval of high pass digital frame comb filter operating lag of receiving on the said high pass numeral row comb filter input, this time interval equal said composite video signal horizontal scanning line the duration; And

The 2nd digital subtractor with the 1st input link, the 2nd input link and an output link, the 1st input is used for receiving the response through time-delay from said 1-H digital delay line, the 2nd input link is received the input link of said high pass numeral row comb filter without actual time delay, and said output link is used for that the signal difference of the 1st and the 2nd input of said the 2nd digital subtractor is provided to said high pass numeral and goes the output link of comb filter.

30., it is characterized in that said code element decision circuit comprises according to the digital signal receiver of claim 29:

The absolute value circuit that an input link and an output link are arranged, input link receive said compound comb filter response, and the output link provides calibration response; And

Threshold dector with an input link and an output link, the input link receives the said calibration response from the output of said absolute value circuit, the output link provides the digital signal bit, when said calibration response surpasses threshold level, each bit is in the 1st state, when said calibration response was no more than said threshold level, each bit was in the 2nd state.

31. according to the digital signal receiver of claim 29, it is characterized in that the output signal position of being sent here by the output of said code element decision circuit provides with chip rate, said digital signal receiver also comprises:

A vertical sync separator is used for isolating vertical sync pulse from the composite video signal that said homophase vision signal detector detects;

A data frame counter is used for the isolated vertical sync pulse that produces when every capable code element counting is not in middle row is counted, and produces the Frame counting thus; And

Rate buffer with an input link and an output link, the input link is used for receiving the bit from said code element decision circuit output link, just receive said bit during and if only if said Frame mould 2 countings have in two values setting, the output link be used for 1/2 chip rate and in accordance with regulations order said code element decision circuit output signal is provided.

32. digital signal receiver according to claim 31, it is characterized in that said rate buffer is used as a non-interlace device, so as said code element decision circuit output signal bit by 1/2 chip rate and in accordance with regulations order deliver to the error recovery detector.

33. the digital signal receiver according to claim 31 also comprises:

In order to the every capable symbol counter that said code element clock oscillation is counted, produce every capable code element count value by it, said every capable symbol counter arrives said code element count resets to its basis for establishing count value corresponding to each said isolated horizontal synchronization pulse;

Be used for said every capable symbol counter resetted at every turn and count and produce the data line counter of data line count value thus, said data line counter in response to each isolated vertical sync pulse said data line count resets to its basis for establishing value; And

Be included at least one random-access memory (ram) in the said rate buffer, and only when said Frame mould 2 countings have in two values a described setting, memory just uses the bit from said code element decision circuit output link to write on independent time point, and said memory receives said data line counting simultaneously and every capable code element is counted as the addressing that writes in the said independent time durations.

34., it is characterized in that said high pass numeral row comb filter comprises according to the digital receiver of claim 28:

Receive the said high pass numeral row comb filter input link of said high pass digital frame comb filter response;

The current comb filter output of the said height link of said compound comb filter response is provided;

The one 1-H digital delay line is used for time interval of high pass digital frame comb filter operating lag of receiving on the said high pass numeral row comb filter input, and this time interval equals the duration of the horizontal scanning line of said composite video signal;

The 2nd digital subtractor with the 1st input link, the 2nd input link and an output link, the 1st input link is used for receiving the response from the delay of a said 1-H digital delay line, the 2nd input link is received the input link of said high pass digital comb filter without actual time delay, and said output link provides the difference of the 1st and the 2nd input end signal of said the 2nd digital subtractor;

The 2nd 1-H digital delay line is used in time interval of the difference operating lag of said the 2nd digital subtractor, and this time interval equals the 1-H duration; And

The 3rd digital subtractor with the 1st input link, the 2nd input link and an output link, the 1st input link is used for receiving the time-delay response from the 2nd 1-H delay line, the 2nd input link connects output link from said the 3rd digital subtractor without actual time delay, and said output link is used for the signal difference of the 1st and the 2nd input link of said the 3rd digital subtractor is provided to the output link of the capable comb filter of said high pass numeral.

35., it is characterized in that said code element decision circuit comprises according to the digital signal receiver of claim 34:

Absolute value circuit with an input link and an output link, input link receive said compound comb filter response, and the output link provides calibration response; And

Dual threshold detector with an input link and an output link, its input link receives the said calibration response from said absolute value circuit output link, the output link provides the digital signal bit, when said calibration response is no more than the 2nd threshold level above the 1st threshold level, each bit all is in the 1st state, when said calibration response was no more than the 1st threshold level or surpasses the 1st and the 2nd threshold level, each bit all was in the 2nd state.

36. according to the digital signal receiver of claim 34, it is characterized in that the output signal position of being sent here by the output of said code element decision circuit provides with chip rate, said digital signal receiver also comprises:

A vertical sync separator is used for isolating vertical sync pulse from the composite video signal that said homophase vision signal detector detects;

A data frame counter is used for the isolated vertical sync pulse that produces when every capable code element counting is not in middle row is counted, and produces the Frame counting thus; And

Rate buffer with an input link and an output link, the input link is used for receiving the bit from said code element decision circuit output link, just receive said bit during and if only if said Frame mould 2 countings have in two values setting, the output link be used for 1/2 chip rate and in accordance with regulations order said code element decision circuit output signal is provided.

37. digital signal receiver according to claim 36, it is characterized in that said rate buffer operates to a non-interlace device, so as said code element decision circuit output signal bit by 1/2 chip rate and in accordance with regulations order deliver to the error recovery detector.

38. the digital signal receiver according to claim 36 also comprises:

In order to the every capable symbol counter that said code element clock oscillation is counted, produce every capable code element count value by it, said every capable symbol counter arrives said code element count resets to its basis for establishing count value corresponding to each said isolated horizontal synchronization pulse;

Be used for said every capable symbol counter resetted at every turn and count and produce the data line counter of data line count value thus, said data line counter in response to each isolated vertical sync pulse said data line count resets to its basis for establishing value; And

Be included at least one random-access memory (ram) in the said rate buffer, and only when said Frame mould 2 countings have in two values a described setting, memory just uses the bit from said code element decision circuit output link to write on independent time point, and said memory receives said data line counting simultaneously and every capable code element is counted as the addressing that writes in the said independent time durations.

39., it is characterized in that said digital comb filter comprises that the back is in series with the high pass numeral row comb filter of a high pass digital frame comb filter according to the digital signal receiver of claim 25.

40., it is characterized in that said high pass digital frame comb filter comprises according to the digital signal receiver of claim 39:

Reception is from the input link of the response of said high pass numeral row comb filter;

The output link of the said high pass digital frame comb filter of said compound comb filter response is provided;

1 frame of digital delay line, it is used for going comb filter time interval of operating lag from said high pass numeral of receiving on the said high pass digital frame comb filter input link, and this time interval equals the frame scan duration of said composite video signal; And

The 1st digital subtractor with the 1st input link, the 2nd input link and an output link, the 1st input link receives the response through time-delay from said 1 frame of digital delay line, the 2nd input link connects input link from said high pass digital frame comb filter without actual time delay, and said output offers the 1st and the 2nd signal difference of importing link of said the 1st digital subtractor the output link of said high pass digital frame comb filter.

41., it is characterized in that said high pass numeral row comb filter comprises according to the digital signal receiver of claim 40:

Said high pass numeral row comb filter input link is used for the sampling of said chip rate reception to the said digitlization response of the sampling of said 90 ° of phase difference vision signal detectors;

Receive the output link of said high pass numeral row comb filter of the input link of said high pass digital frame comb filter;

The 1-H digital delay line, it is used for the receiver response of wanting that has undesired receiver response of receiving on the said high pass numeral row comb filter input is postponed a time interval, and this time interval equals the duration of the horizontal scanning line of said composite video signal; And

The 2nd digital subtractor with the 1st input link, the 2nd input link and an output link, the 1st input link receives the response with time-delay from the 1-H digital delay line, the 2nd input link connects input link from said high pass numeral row comb filter without actual time delay, and said output is used for that the difference of the signal on the 1st and the 2nd input link of said the 2nd digital subtractor is provided to said high pass numeral and goes the output link of comb filter.

42., it is characterized in that said code element decision circuit comprises according to the digital signal receiver of claim 41:

Absolute value circuit with an input link and an output link, its input link receive said compound comb filter response, and the output link provides calibration response; With

Threshold dector with an input link and an output link, the input link receives the calibration response from said absolute value circuit output, the output link provides the digital signal bit, when said calibration response surpasses a threshold level, each bit is in the 1st state, and each bit is in the 2nd state when said calibration response is no more than said threshold level.

43. according to the digital signal receiver of claim 41, it is characterized in that the output signal position of being sent here by the output of said code element decision circuit provides with chip rate, said digital signal receiver also comprises:

A vertical sync separator is used for isolating vertical sync pulse from the composite video signal that said homophase vision signal detector detects;

A data frame counter is used for the isolated vertical sync pulse that produces when every capable code element counting is not in middle row is counted, and produces the Frame counting thus; And

Rate buffer with an input link and an output link, the input link is used for receiving the bit from said code element decision circuit output link, just receive said bit during and if only if said Frame mould 2 countings have in two values setting, the output link be used for 1/2 chip rate and in accordance with regulations order said code element decision circuit output signal is provided.

44. digital signal receiver according to claim 43, it is characterized in that said rate buffer operates to a non-interlace device, so as said code element decision circuit output signal bit by 1/2 chip rate and in accordance with regulations order deliver to the error recovery detector.

45. the digital signal receiver according to claim 43 also comprises:

In order to the every capable symbol counter that said code element clock oscillation is counted, produce every capable code element count value by it, said every capable symbol counter arrives said code element count resets to its basis for establishing count value corresponding to each said isolated horizontal synchronization pulse;

Be used for said every capable symbol counter resetted at every turn and count and produce the data line counter of data line count value thus, said data line counter in response to each isolated vertical sync pulse said data line count resets to its basis for establishing value; And

Be included at least one random-access memory (ram) in the said rate buffer, and only when said Frame mould 2 countings have in two values a described setting, memory just uses the bit from said code element decision circuit output link to write on independent time point, and said memory receives said data line counting simultaneously and every capable code element is counted as the addressing that writes in the said independent time durations.

46., it is characterized in that said high pass numeral row comb filter comprises according to the digital signal receiver of claim 40:

The input link of said high pass numeral row comb filter, it is used for the again sub-sampling of said chip rate reception to the said digitlization response of the sampling of said 90 ° of phase difference vision signal detectors;

Receive the output link of the said high pass numeral row comb filter of said high pass digital frame comb filter input link;

The one 1-H digital delay line, it is used for time interval of the operating lag that has the wave detector of wanting of not wanting receiver response of receiving on the input of said high pass numeral row comb filter, this time interval equals the 1-H duration of the horizontal scanning line of said composite video signal;

The 2nd digital subtractor with the 1st input link, the 2nd input link and an output link, the 1st input link receives the time-delay response from the 1st 1-H digital delay line, the 2nd input is received the input of said high pass numeral row comb filter without actual time delay, and said output link is used to provide the difference of the signal on the 1st and the 2nd input of said the 2nd digital subtractor;

The 2nd 1-H digital delay line, it is used in time interval of the difference operating lag of the 2nd digital subtractor, and this time interval equals the 1-H duration; And

The 3rd digital subtractor with the 1st input link, the 2nd input link and an output link, the 1st input link is used for receiving the time-delay response from said the 2nd 1-H digital delay line, the 2nd input link is received the output link of said the 2nd digital subtractor without actual time delay, and said output link is used for the signal difference on said the 3rd digital subtractor the 1st and the 2nd input is provided to the output of the capable comb filter of said high pass numeral.

47., it is characterized in that said code element decision circuit comprises according to the digital signal receiver of claim 46:

Absolute value circuit with an input link and an output link, said input link are used for receiving said compound comb filter response, and said output link provides calibration response; And

Dual threshold detector with an input link and an output link, the input link is used for receiving the calibration response from the output link of said absolute value circuit, the output link is used to provide the digital signal bit, when being no more than the 2nd threshold level when said calibration response the 1st threshold level, each bit is in the 1st state, and each bit is in the 2nd state when said calibration response is no more than said the 1st threshold level or surpasses the 1st and the 2nd these two threshold levels.

48. according to the digital signal receiver of claim 46, it is characterized in that the output signal position of being sent here by the output of said code element decision circuit provides with chip rate, said digital signal receiver also comprises:

A vertical sync separator is used for isolating vertical sync pulse from the composite video signal that said homophase vision signal detector detects;

A data frame counter is used for the isolated vertical sync pulse that produces when every capable code element counting is not in middle row is counted, and produces the Frame counting thus; And

Rate buffer with an input link and an output link, the input link is used for receiving the bit from said code element decision circuit output link, just receive said bit during and if only if said Frame mould 2 countings have in two values setting, the output link be used for 1/2 chip rate and in accordance with regulations order said code element decision circuit output signal is provided.

49. digital signal receiver according to claim 48, it is characterized in that said rate buffer is used as a non-interlace device, so as said code element decision circuit output signal bit by 1/2 chip rate and in accordance with regulations order deliver to the error recovery detector.

50. the digital signal receiver according to claim 48 also comprises:

In order to the every capable symbol counter that said code element clock oscillation is counted, produce every capable code element count value by it, said every capable symbol counter arrives said code element count resets to its basis for establishing count value corresponding to each said isolated horizontal synchronization pulse;

Be used for said every capable symbol counter resetted at every turn and count and produce the data line counter of data line count value thus, said data line counter in response to each isolated vertical sync pulse said data line count resets to its basis for establishing value; And

Be included at least one random-access memory (ram) in the said rate buffer, and only when said Frame mould 2 countings have in two values a described setting, memory just uses the bit from said code element decision circuit output link to write on independent time point, and said memory receives said data line counting simultaneously and every capable code element is counted as the addressing that writes in the said independent time durations.

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