JP2836602B2 - Mold type semiconductor device - Google Patents

Mold type semiconductor device

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Publication number
JP2836602B2
JP2836602B2 JP8252732A JP25273296A JP2836602B2 JP 2836602 B2 JP2836602 B2 JP 2836602B2 JP 8252732 A JP8252732 A JP 8252732A JP 25273296 A JP25273296 A JP 25273296A JP 2836602 B2 JP2836602 B2 JP 2836602B2
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor chip
lead frame
molded
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP8252732A
Other languages
Japanese (ja)
Other versions
JPH1098150A (en
Inventor
和義 上村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP8252732A priority Critical patent/JP2836602B2/en
Publication of JPH1098150A publication Critical patent/JPH1098150A/en
Application granted granted Critical
Publication of JP2836602B2 publication Critical patent/JP2836602B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明はモールド型半導体装
置に関し、特に高周波領域での安定動作を改善するモー
ルド型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a molded semiconductor device, and more particularly to a molded semiconductor device which improves stable operation in a high frequency range.

【０００２】[0002]

【従来の技術】従来、このような回路動作の安定化を図
るためのモールド型半導体装置は、例えば特開平３−７
８２４８号公報および特開平６−２１３２０号公報など
で知られている。2. Description of the Related Art Conventionally, a mold type semiconductor device for stabilizing such a circuit operation is disclosed in, for example, Japanese Patent Application Laid-Open No.
No. 8248 and Japanese Patent Application Laid-Open No. 6-21320.

【０００３】図８はかかる従来の一例を示すモールド型
半導体装置の平面図である。図８に示すように、このモ
ールド型半導体装置４０は、前者の文献に記載されてい
る例であり、リードフレーム４１上に半導体チップ４２
を搭載している。この場合、雑音を発生する回路の電源
用ボンディングパッド４５と、接地用ボンディングパッ
ド４６とは、それぞれ二股に分かれたリードフレーム部
４８および４９の片側端にボンディングワイヤ４７によ
り接続されている。また、上述の回路とは別の回路の電
源用ボンディングパッド４３と、接地用ボンディングパ
ッド４４とは、リードフレーム部４８および４９の他端
にボンディングワイヤ４７によりそれぞれ接続されてい
る。FIG. 8 is a plan view of a molded semiconductor device showing an example of such a conventional semiconductor device. As shown in FIG. 8, this molded semiconductor device 40 is an example described in the former document, and a semiconductor chip 42 is mounted on a lead frame 41.
It is equipped with. In this case, the power supply bonding pad 45 and the ground bonding pad 46 of the noise generating circuit are connected to one end of each of the forked lead frame portions 48 and 49 by a bonding wire 47. The power supply bonding pad 43 and the ground bonding pad 44 of a circuit different from the above-described circuit are connected to the other ends of the lead frame portions 48 and 49 by bonding wires 47, respectively.

【０００４】かかる半導体チップ４２内部の雑音を発生
する回路から発生された雑音は、ボンディングパッド４
５および４６からそれぞれ二股に分かれたリードフレー
ム部４８および４９の一方から他方を通り、ボンディン
グパッド４３および４４へ伝播されるが、これら二股リ
ードフレーム部４８，４９のインダクタンスによって、
伝わる雑音の大きさは低減される。The noise generated from the noise generating circuit inside the semiconductor chip 42 is transmitted to the bonding pad 4.
5 and 46 are transmitted to the bonding pads 43 and 44 from one of the forked lead frame portions 48 and 49 through the other. Due to the inductance of the forked lead frame portions 48 and 49,
The magnitude of the transmitted noise is reduced.

【０００５】上述した前者の例においては、リードフレ
ーム４１の隅と二股リードフレーム部４８の一端との間
にチップコンデンサ５０を搭載し、発生した雑音の他の
回路への影響をさらに低減している。In the former example described above, a chip capacitor 50 is mounted between a corner of the lead frame 41 and one end of the forked lead frame portion 48 to further reduce the influence of generated noise on other circuits. I have.

【０００６】図９は従来の他の例を示すモールド型半導
体装置の平面図である。図９に示すように、このモール
ド型半導体装置５０は、後者の文献に記載されている例
であり、半導体チップとリードフレームをリード・オン
・チップ（ＬＯＣ）構造に実装させている。このモール
ド型半導体装置５０の中央部には、出力バッファ配線領
域７２が形成され、その外側には電源供給用リードフレ
ーム（バスバー）６８，６９および入力回路用のリード
６６，６７が配置される。また、この出力バッファ配線
領域７２においては、中央には各種接続用のボンディン
グパッド５４〜５９およびボンディングパッド７０，７
１とが形成され、その外側には入力回路用の電源供給線
５２，５３と内部回路用の電源供給線６２，６３および
出力回路用の電源供給線６４，６５とが設けられてい
る。これらパッドと電源供給線とは、配線６０で接続し
たり、あるいはリードフレーム６８，６９およびリード
６６，６７との間に、ボンディングワイヤ６１で接続さ
れる。FIG. 9 is a plan view of a mold type semiconductor device showing another example of the prior art. As shown in FIG. 9, this molded semiconductor device 50 is an example described in the latter document, in which a semiconductor chip and a lead frame are mounted in a lead-on-chip (LOC) structure. An output buffer wiring region 72 is formed in the center of the molded semiconductor device 50, and power supply lead frames (bus bars) 68 and 69 and input circuit leads 66 and 67 are arranged outside the output buffer wiring region 72. In the output buffer wiring region 72, bonding pads 54 to 59 for various connections and bonding pads 70 and 7 are provided at the center.
The power supply lines 52 and 53 for the input circuit, the power supply lines 62 and 63 for the internal circuit, and the power supply lines 64 and 65 for the output circuit are provided on the outside. These pads and the power supply lines are connected by wiring 60 or connected between lead frames 68 and 69 and leads 66 and 67 by bonding wires 61.

【０００７】かかる半導体装置において、雑音の回り込
みを防止するために、入力回路用リード６６，６７は、
他のリードフレーム６８，６９とは分離された構造を採
用している。このリードの分離構造により、雑音信号が
リードフレーム６８，６９を通して直接リード６６，６
７に伝わるのを防止している。In such a semiconductor device, the input circuit leads 66, 67 are provided with
A structure separated from the other lead frames 68 and 69 is adopted. This lead separation structure allows noise signals to pass directly through the lead frames 68 and 69 to the leads 66 and 6.
7 is prevented.

【０００８】さらに、上述した２つの周知技術とは別
に、半導体チップを実装する支持基体を複数に分割する
技術も考えられている。しかし、この支持基体の分割技
術は、半導体チップと支持基体の熱膨張係数の違いによ
る実装時の歪を緩和するために、半導体チップを実装す
る支持基板に溝などを形成することにより、歪吸収を行
わせているにすぎない。Further, apart from the above-mentioned two well-known techniques, a technique of dividing a support base on which a semiconductor chip is mounted into a plurality of pieces has been considered. However, this support base dividing technique involves forming a groove or the like in the support substrate on which the semiconductor chip is mounted in order to alleviate distortion during mounting due to the difference in thermal expansion coefficient between the semiconductor chip and the support base, thereby absorbing the strain. It just makes you do.

【０００９】[0009]

【発明が解決しようとする課題】上述した前者のモール
ド型半導体装置は、その半導体装置の構造にマイクロ波
帯で動作する半導体チップを適用したとき、その半導体
チップ裏面の導体部を介して高周波雑音の回り込みが発
生し、回路の安定動作を損われるという不都合を生ず
る。In the former mold-type semiconductor device described above, when a semiconductor chip operating in a microwave band is applied to the structure of the semiconductor device, high-frequency noise is applied through a conductor on the back surface of the semiconductor chip. Wraparound occurs, and the stable operation of the circuit is impaired.

【００１０】その理由は、リードフレームの持つインダ
クタンスのために、半導体チップ裏面が高周波的には完
全に接地されていないためである。この傾向は扱う周波
数が高くなればなる程、大きくなる。The reason is that the back surface of the semiconductor chip is not completely grounded in terms of high frequency due to the inductance of the lead frame. This tendency becomes greater as the frequency handled becomes higher.

【００１１】また、後者のモールド型半導体装置は、Ｌ
ＯＣ構造を採用しており、半導体チップの裏面が接地電
位になっていないので、裏面を接地面として用いるマイ
クロストリップ線路を形成するタイプのマイクロ波集積
回路等への適用ができないという欠点がある。The latter mold type semiconductor device has an L
Since the OC structure is adopted and the back surface of the semiconductor chip is not at the ground potential, there is a drawback that the semiconductor chip cannot be applied to a microwave integrated circuit of a type forming a microstrip line using the back surface as a ground surface.

【００１２】本発明の目的は、かかるマイクロ波帯以上
の周波数でも安定動作させられるとともに、汎用性を持
たせたモールド型半導体装置を提供することにある。An object of the present invention is to provide a molded semiconductor device which can be operated stably even at a frequency higher than the microwave band and has versatility.

【００１３】[0013]

【課題を解決するための手段】本発明のモールド型半導
体装置は、複数の独立した接地用端子を備えた半導体チ
ップと、前記半導体チップを搭載する搭載面および外部
回路への電気的接続を行うリードを備えたリードフレー
ムと、前記半導体チップおよび前記リードを接続するボ
ンディングワイヤとを有し、モールド樹脂により、前記
半導体チップ，前記リードフレーム，前記ボンディング
ワイヤを固定してなるモールド型半導体装置において、
前記半導体チップを搭載する前記搭載面を複数に分割し
て形成した複数のリードフレーム部と、前記複数のリー
ドフレーム部からそれぞれ外部回路へ電気的に導出する
複数の接地用リードとを具備して構成される。SUMMARY OF THE INVENTION A molded semiconductor device of the present invention electrically connects a semiconductor chip having a plurality of independent ground terminals, a mounting surface on which the semiconductor chip is mounted, and an external circuit. A molded semiconductor device comprising: a lead frame having leads; and a bonding wire connecting the semiconductor chip and the leads, wherein the semiconductor chip, the lead frame, and the bonding wires are fixed with a mold resin.
A plurality of lead frame portions formed by dividing the mounting surface for mounting the semiconductor chip into a plurality of portions, and a plurality of ground leads which are respectively electrically derived from the plurality of lead frame portions to an external circuit. Be composed.

【００１４】すなわち、本発明のモールド型半導体装置
は、リードフレームの半導体チップ搭載面が高周波雑音
を発生させる回路と他の回路とを分離するように複数に
分割され、しかも分割されたチップ搭載面からそれぞれ
外部回路へ導出される接地用リードを具備して構成され
る。That is, according to the mold type semiconductor device of the present invention, the semiconductor chip mounting surface of the lead frame is divided into a plurality of parts so as to separate a circuit generating high frequency noise from other circuits, and the divided chip mounting surface is divided. And a grounding lead led out to an external circuit.

【００１５】また、本発明のモールド型半導体装置にお
ける半導体チップは、裏面に分割された複数の導体層を
形成し、前記複数の導体層はそれぞれ前記複数のリード
フレーム部に対応して形成することができる。Further, the semiconductor chip in the molded semiconductor device of the present invention has a plurality of divided conductor layers formed on the back surface, and the plurality of conductor layers are respectively formed corresponding to the plurality of lead frame portions. Can be.

【００１６】さらに、本発明のモールド型半導体装置に
おける半導体チップは、表面に複数の接地用端子を形成
し、前記複数の接地用端子をバイアホールにより前記半
導体チップの裏面へ導通させて形成することができる。Further, the semiconductor chip in the molded semiconductor device of the present invention is formed by forming a plurality of grounding terminals on the front surface and conducting the plurality of grounding terminals to the back surface of the semiconductor chip through via holes. Can be.

【００１７】[0017]

【発明の実施の形態】次に、本発明の実施の形態ついて
図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.

【００１８】図１（ａ），（ｂ）はそれぞれ本発明の第
１の実施の形態を説明するためのモールド型半導体装置
の平面図およびそのＡ−Ａ’線断面図である。図１
（ａ），（ｂ）に示すように、本実施の形態におけるモ
ールド型半導体装置は、２つに分割されたリードフレー
ム部２および３と、これらのリードフレーム部２，３上
に銀ペースト等の接着剤４を用いてマウントされる半導
体チップ１とを備え、リードフレーム部２からは外部回
路へ接続するための接地用リード５および６が導出さ
れ、またリードフレーム部３からは同様に接地用リード
７および８が導出される。FIGS. 1A and 1B are a plan view and a sectional view taken along line AA 'of a mold-type semiconductor device, respectively, for explaining a first embodiment of the present invention. FIG.
As shown in (a) and (b), the molded semiconductor device according to the present embodiment has lead frame portions 2 and 3 divided into two, and silver paste or the like on these lead frame portions 2 and 3. And a semiconductor chip 1 mounted using an adhesive 4 of the type described above. Leads 5 and 6 for grounding for connection to an external circuit are led out from the lead frame part 2, and ground leads are similarly provided from the lead frame part 3. Lead 7 and 8 are derived.

【００１９】一方、搭載される半導体チップ１は、その
表面に形成された接地用パッド９〜１２と、ボンディン
グパッド１７とを形成しており、接地用パッド９〜１２
はそれぞれ接地用リード５〜８に金などのボンディング
ワイヤ１３によって接続される。同様に、ボンディング
パッド１７は外部へ導出されるリード１６にボンディン
グワイヤ１３によって接続される。On the other hand, the semiconductor chip 1 to be mounted has grounding pads 9 to 12 formed on the surface thereof and bonding pads 17, and the grounding pads 9 to 12 are formed.
Are connected to grounding leads 5 to 8 by bonding wires 13 such as gold. Similarly, the bonding pad 17 is connected to a lead 16 led out to the outside by a bonding wire 13.

【００２０】これら半導体チップ１と、リードフレーム
部２，３と、各種リード５〜８，１６と、ボンディング
ワイヤ１３とは、封止領域１４内に注入されるモールド
樹脂１５によって固定される。なお、このモールド樹脂
１５は外力から半導体チップ１を保護する働きも兼ねて
いる。The semiconductor chip 1, the lead frame portions 2 and 3, the various leads 5 to 8 and 16, and the bonding wires 13 are fixed by a molding resin 15 injected into a sealing region 14. The mold resin 15 also has a function of protecting the semiconductor chip 1 from external force.

【００２１】図２は図１におけるリードフレームの平面
図である。図２に示すように、このリードフレーム１８
は、図１におけるリードフレーム部２，３と、接地用リ
ード５〜８と、リード１６とを切断する前の状態であ
る。このリードフレーム１８は、厚さ０．１５ｍｍ程度
の銅板をプレス加工又はエッチング加工を施した後、銀
メッキなどの処理を行って作成することができる。FIG. 2 is a plan view of the lead frame in FIG. As shown in FIG.
1 shows a state before cutting the lead frame portions 2 and 3, the grounding leads 5 to 8, and the lead 16 in FIG. 1. The lead frame 18 can be formed by pressing or etching a copper plate having a thickness of about 0.15 mm and then performing a process such as silver plating.

【００２２】図３（ａ）〜（ｄ）はそれぞれ図１のモー
ルド型半導体装置を製造する際の工程順に示す斜視図で
ある。まず、図３（ａ）に示すように、リードフレーム
１８の２分割されたフレーム部に銀ペースとなどの接着
剤４を塗布し、その上から半導体チップ１をマウントし
固定する。FIGS. 3A to 3D are perspective views showing the order of steps in manufacturing the molded semiconductor device of FIG. First, as shown in FIG. 3A, an adhesive 4 such as a silver paste is applied to the frame portion of the lead frame 18 divided into two, and the semiconductor chip 1 is mounted and fixed thereon.

【００２３】ついで、図３（ｂ）に示すように、金ワイ
ヤ等のボンディングワイヤ１３により、半導体チップ１
のパッドと各リード部とを配線する。Next, as shown in FIG. 3B, the semiconductor chip 1 is bonded by bonding wires 13 such as gold wires.
Are connected to the pads and the respective leads.

【００２４】さらに、図３（ｃ）に示すように、金型
（図示省略）を用い、半導体チップ１，リードフレーム
１８をエポキシ樹脂などのモールド樹脂１５で封止し固
定する。Further, as shown in FIG. 3C, the semiconductor chip 1 and the lead frame 18 are sealed and fixed with a mold resin 15 such as an epoxy resin using a mold (not shown).

【００２５】最後に、図３（ｄ）に示すように、不要な
リードフレーム部分を切断し、しかも残された各リード
５〜８および１６に対して成形することにより、モール
ド型半導体装置２０が完成される。Finally, as shown in FIG. 3D, the unnecessary lead frame portion is cut, and the remaining leads 5 to 8 and 16 are molded, so that the mold type semiconductor device 20 is completed. Be completed.

【００２６】図４は図１におけるモールド型半導体装置
を搭載したプリント基板の平面図である。図４に示すよ
うに、前述したモールド型半導体装置２０をプリント基
板２１に実装するときは、プリント基板２１に銅などの
導体層２２によってＶＤＤ端子，ＶＧＧ端子およびＰＩ
Ｎ端子，ＰＯＵＴ端子に接続される回路パターンや接地
用パターン２５，２６を形成しておき、その上に半田等
のロー材２４を用いて搭載する。また、接地用パターン
２５，２６はスルーホール２３を介して図示していない
裏面の接地面に接続される。FIG. 4 is a plan view of a printed circuit board on which the molded semiconductor device in FIG. 1 is mounted. As shown in FIG. 4, when the above-described molded semiconductor device 20 is mounted on a printed circuit board 21, a VDD terminal, a VGG terminal and a PI terminal are formed on the printed circuit board 21 by a conductor layer 22 such as copper.
Circuit patterns and grounding patterns 25 and 26 connected to the N terminal and the POUT terminal are formed, and mounted thereon using a brazing material 24 such as solder. In addition, the ground patterns 25 and 26 are connected to the ground surface on the back surface (not shown) via the through holes 23.

【００２７】図５は図４におけるプリント基板に搭載し
たモールド型半導体装置の等価回路図である。図５に示
すように、この半導体装置の等価回路は、半導体チップ
に含まれ且つ入力端子ＲＩＮ，出力端子ＰＯＵＴ間に接
続される内部整合回路２７Ａ〜２７Ｃと、２段の増幅器
を形成するＦＥＴＱ１，Ｑ２と、ボンディングワイヤ１
３によるインダクタンス部２８と、リードフレーム部
２，３に相当する接続部２９Ａ，２９Ｂと、接地用リー
ド５，６によるインダクタンス（Ｌ６）３０Ａおよび接
地用リード７，８によるインダクタンス（Ｌ７）３０Ｂ
と、その他の抵抗素子などとから構成され、プリント基
板（図４の２１）の接地パターン３１に接続される。ま
た、インダクタンス部２８は、複数のインダクタンスＬ
１〜Ｌ５からなり、Ｌ１は接地用パッド９と接地用リー
ド５を接続するボンディングワイヤ１３のインダクタン
ス、Ｌ２は接地用パッド１０と接地用リード６を接続す
るボンディングワイヤ１３のインダクタンス、Ｌ３は図
示省略した他のボンディングワイヤ１３によるインダク
タンスであり、同様にＬ４は接地用パッド１１と接地用
リード７を接続するボンディングワイヤ１３のインダク
タンス、Ｌ５は接地用パッド１２と接地用リード８を接
続するボンディングワイヤ１３のインダクタンスであ
る。FIG. 5 is an equivalent circuit diagram of the molded semiconductor device mounted on the printed circuit board in FIG. As shown in FIG. 5, an equivalent circuit of the semiconductor device includes internal matching circuits 27A to 27C included in a semiconductor chip and connected between an input terminal RIN and an output terminal POUT, and FETs Q1 and Q2 forming a two-stage amplifier. Q2 and bonding wire 1
3, connecting portions 29A and 29B corresponding to the lead frame portions 2 and 3, an inductance (L6) 30A by the grounding leads 5 and 6, and an inductance (L7) 30B by the grounding leads 7 and 8.
And other resistance elements, etc., and are connected to the ground pattern 31 of the printed circuit board (21 in FIG. 4). Further, the inductance unit 28 includes a plurality of inductances L.
L1 is the inductance of the bonding wire 13 connecting the ground pad 9 and the ground lead 5, L2 is the inductance of the bonding wire 13 connecting the ground pad 10 and the ground lead 6, and L3 is not shown. L4 is the inductance of the bonding wire 13 connecting the grounding pad 11 and the grounding lead 7, and L5 is the bonding wire 13 connecting the grounding pad 12 and the grounding lead 8. Is the inductance of

【００２８】かかるＦＥＴＱ１，Ｑ２で形成された２段
の増幅器は、ＦＥＴＱ１を中心とする前段回路部の接地
配線と、ＦＥＴＱ２を中心とする後段回路部の接地配線
とをリードフレーム部２，３により分割してモールド領
域の外部に導出しており、プリント配線に実装すること
により、接地パターンを介して接続される。In the two-stage amplifier formed by the FETs Q1 and Q2, the ground wiring of the preceding circuit portion centering on the FET Q1 and the ground wiring of the subsequent circuit portion centering on the FET Q2 are connected by the lead frame portions 2 and 3. It is divided and led out of the mold region, and is connected via a ground pattern by being mounted on a printed wiring.

【００２９】この回路構成において、例えば後段回路部
（Ｑ２側）で発生した高周波雑音αは、ボンディングイ
ンダクタンスＬ４，Ｌ２およびリードインダクタンス
（Ｌ７）３０Ｂ，（Ｌ６）３０Ａを介して、前段回路部
（Ｑ１側）に伝達されるが、リードフレーム部２，３が
分離されており且つリード５，６およびリード７，８が
別個に設けられているため、雑音振幅は大きく減衰す
る。これは前段回路部（Ｑ１側）への雑音の影響も大き
く軽減することができることを意味している。すなわ
ち、半導体チップ搭載面のリードフレームが分割されて
いるため、後段回路部から前段回路部へ回り込む雑音信
号は、半導体チップ裏面の導体部を通過するので、大き
く低減させることができる。In this circuit configuration, for example, the high frequency noise α generated in the subsequent circuit section (Q2 side) passes through the preceding circuit section (Q1) via the bonding inductances L4 and L2 and the lead inductances (L7) 30B and (L6) 30A. Side), but since the lead frame portions 2 and 3 are separated and the leads 5 and 6 and the leads 7 and 8 are separately provided, the noise amplitude is greatly attenuated. This means that the influence of noise on the preceding-stage circuit section (Q1 side) can be greatly reduced. That is, since the lead frame on the mounting surface of the semiconductor chip is divided, the noise signal flowing from the subsequent circuit portion to the preceding circuit portion passes through the conductor portion on the back surface of the semiconductor chip, so that it can be greatly reduced.

【００３０】また、かかる構成のモールド型半導体装置
は、半導体チップの裏面に接地面を形成できるので、マ
イクロ波ストリップ線路を用いるマイクロ波集積回路等
への適用も可能になる。In addition, since the molded semiconductor device having such a structure can form a ground plane on the back surface of the semiconductor chip, it can be applied to a microwave integrated circuit using a microwave strip line.

【００３１】図６（ａ），（ｂ）はそれぞれ本発明の第
２の実施の形態を説明するためのモールド型半導体装置
の平面図およびそのＡ−Ａ’線断面図である。図６
（ａ），（ｂ）に示すように、本実施の形態におけるモ
ールド型半導体装置は、前述した図１（ａ），（ｂ）の
リードフレーム部２，３の分割構造および接地用リード
５〜８と同様の構造を有する。本実施の形態が前述した
実施の形態と比較して異なのは、半導体チップ１の裏面
に導体層３２，３３を形成するとともに、半導体チップ
１をリードフレーム部２，３にマウントする際、金錫等
のロー材３４を用いたことにある。この場合、半導体チ
ップ１の裏面にあらかじめ導体層３２，３３を形成して
いるが、これらの導体層３２，３３は分割したリードフ
レーム部２，３に合わせて分割形成される。FIGS. 6 (a) and 6 (b) are a plan view and a sectional view taken along line AA 'of a molded semiconductor device, respectively, for explaining a second embodiment of the present invention. FIG.
As shown in FIGS. 1A and 1B, the molded semiconductor device according to the present embodiment has the above-described split structure of the lead frame portions 2 and 3 and the grounding leads 5 to 5 shown in FIGS. 8 has the same structure. The present embodiment is different from the above-described embodiment in that the conductor layers 32 and 33 are formed on the back surface of the semiconductor chip 1 and the gold and tin are used when the semiconductor chip 1 is mounted on the lead frame portions 2 and 3. And the like. In this case, the conductor layers 32 and 33 are formed in advance on the back surface of the semiconductor chip 1, and these conductor layers 32 and 33 are formed separately according to the divided lead frame portions 2 and 3.

【００３２】図７は本発明の第３の実施の形態を説明す
るためのモールド型半導体装置の平面図である。図７に
示すように、本実施の形態におけるモールド型半導体装
置は、ボンディングワイヤ１３の一部をバイアホール３
５〜３８で置換したものである。すなわち、半導体チッ
プ１上に形成された接地用パッド９〜１２は、ボンディ
ングワイヤ１３により接地用リード５〜８に接続するの
ではなく、バイアホール３５〜３８により直接チップ裏
面へ接続するものである。その他は、前述した第１，第
２の実施の形態と同様である。FIG. 7 is a plan view of a molded semiconductor device for explaining a third embodiment of the present invention. As shown in FIG. 7, in the molded semiconductor device according to the present embodiment, a part of bonding wire 13 is
Substituted with 5-38. That is, the ground pads 9 to 12 formed on the semiconductor chip 1 are not connected to the ground leads 5 to 8 by the bonding wire 13 but are directly connected to the chip back surface by the via holes 35 to 38. . Others are the same as those of the first and second embodiments.

【００３３】本実施の形態によれば、ボンディングワイ
ヤ１３によるインダクタンスがバイアホール３５〜３８
によるインダクタンスに変わるため、すなわちインダク
タンスが小さくなるため、雑音阻止能力は前述した第
１，第２の実施の形態よりも劣るものの、ボンディング
数が減るため、製造上の各種の利点が生ずる。According to the present embodiment, the inductance due to the bonding wire 13 is reduced to the via holes 35 to 38.
In other words, the inductance is reduced, that is, the inductance is reduced, so that the noise suppression ability is inferior to those of the first and second embodiments. However, the number of bondings is reduced, and various manufacturing advantages are brought about.

【００３４】要するに、これらの実施の形態によれば、
半導体チップの裏面導体部は、雑音を発生する回路部
と、他の回路部とから分離されているため、この裏面導
体部を介する高周波雑音の伝達を大幅に軽減し、その高
周波雑音の回り込みによる回路動作の不安定さを改善す
ることができる。In short, according to these embodiments,
Since the backside conductor of the semiconductor chip is separated from the circuit generating noise and other circuit parts, transmission of high frequency noise through this backside conductor is greatly reduced, and the high frequency noise wraps around. Instability of circuit operation can be improved.

【００３５】[0035]

【発明の効果】以上説明したように、本発明のモールド
型半導体装置は、雑音を発生する回路を備えていても、
接地配線を介して周辺回路に及ぼす雑音の影響を低減で
きるという効果がある。As described above, the molded semiconductor device of the present invention has a circuit for generating noise.
There is an effect that the effect of noise on peripheral circuits via the ground wiring can be reduced.

【００３６】その理由は、雑音を発生する回路の接地配
線とその他の回路の接地配線とを、リードフレームを分
割することにより装置内で分離することができ、雑音の
回り込みに際しては、ボンディングインダクタンスとリ
ードインダクタンスを利用して減衰させるからである。The reason is that the ground wiring of the circuit that generates noise and the ground wiring of other circuits can be separated in the device by dividing the lead frame. This is because attenuation is performed using the lead inductance.

【００３７】また、本発明のモールド型半導体装置は、
リードフレームの分割個所を半導体チップ搭載面に設け
ることにより、半導体チップ裏面から回り込む高周波雑
音信号を十分に低減させることができるので、マイクロ
波帯以上の高周波数帯を扱う半導体チップに対しても雑
音の低減を実現でき、汎用性を高められるという効果も
ある。Also, the molded semiconductor device of the present invention
By providing the split part of the lead frame on the semiconductor chip mounting surface, it is possible to sufficiently reduce high-frequency noise signals circulating from the backside of the semiconductor chip. This also has the effect of increasing the versatility.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施の形態を説明するためのモール
ド型半導体装置の平面およびそのＡ−Ａ’線断面を表わ
す図である。FIG. 1 is a diagram illustrating a plan view of a mold-type semiconductor device and a cross section taken along line AA ′ of the mold-type semiconductor device for describing an embodiment of the present invention;

【図２】図１におけるリードフレームの平面図である。FIG. 2 is a plan view of the lead frame in FIG. 1;

【図３】図１のモールド型半導体装置を製造する際の工
程順に示した斜視図である。FIG. 3 is a perspective view showing the order of steps in manufacturing the molded semiconductor device of FIG. 1;

【図４】図１に示すモールド型半導体装置を搭載したプ
リント基板の平面図である。FIG. 4 is a plan view of a printed board on which the molded semiconductor device shown in FIG. 1 is mounted.

【図５】図４におけるプリント基板に搭載したモールド
型半導体装置の等価回路図である。FIG. 5 is an equivalent circuit diagram of the molded semiconductor device mounted on the printed circuit board in FIG. 4;

【図６】本発明の第２の実施の形態を説明するためのモ
ールド型半導体装置の平面およびそのＡ−Ａ’線断面を
表わす図である。FIG. 6 is a diagram illustrating a plane of a molded semiconductor device and a cross section taken along line AA ′ of the molded semiconductor device for describing a second embodiment of the present invention;

【図７】本発明の第３の実施の形態を説明するためのモ
ールド型半導体装置の平面図である。FIG. 7 is a plan view of a molded semiconductor device for explaining a third embodiment of the present invention.

【図８】従来の一例を示すモールド型半導体装置の平面
図である。FIG. 8 is a plan view of a mold type semiconductor device showing an example of the related art.

【図９】従来の他の例を示すモールド型半導体装置の平
面図である。FIG. 9 is a plan view of a molded semiconductor device showing another example of the related art.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２，３ リードフレーム部 ４ 接着剤 ５〜８ 接地用リード ９〜１２ 接地用パッド １３ ボンディングワイヤ １４ 封止領域 １５ モールド樹脂 １６ リード １８ リードフレーム ２０ モールド半導体装置 ２１ プリント基板 ２２ 導体層（導体パターン） ２３ スルーホール ２４，３４ ロー材 ２５，２６ 接地用パターン ３２，３３ 導体層 ３５〜３８ バイアホール DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2, 3 Lead frame part 4 Adhesive 5-8 Grounding lead 9-12 Grounding pad 13 Bonding wire 14 Sealing area 15 Mold resin 16 Lead 18 Lead frame 20 Molded semiconductor device 21 Printed circuit board 22 Conductive layer ( Conductor pattern) 23 Through hole 24, 34 Low material 25, 26 Grounding pattern 32, 33 Conductive layer 35-38 Via hole

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 複数の独立した接地用端子を備えた半導
体チップと、前記半導体チップを搭載する搭載面および
外部回路への電気的接続を行うリードを備えたリードフ
レームと、前記半導体チップおよび前記リードを接続す
るボンディングワイヤとを有し、モールド樹脂により、
前記半導体チップ，前記リードフレーム，前記ボンディ
ングワイヤを固定してなるモールド型半導体装置におい
て、前記半導体チップを搭載する前記搭載面を複数に分
割して形成した複数のリードフレーム部と、前記複数の
リードフレーム部からそれぞれ外部回路へ電気的に導出
する複数の接地用リードとを具備することを特徴とする
モールド型半導体装置。A semiconductor chip having a plurality of independent ground terminals; a lead frame having leads for electrically connecting to a mounting surface on which the semiconductor chip is mounted and an external circuit; It has a bonding wire for connecting the lead,
In a molded semiconductor device in which the semiconductor chip, the lead frame, and the bonding wire are fixed, a plurality of lead frame portions formed by dividing the mounting surface on which the semiconductor chip is mounted into a plurality of parts; A molded semiconductor device comprising: a plurality of grounding leads each of which is electrically led to an external circuit from a frame portion. 【請求項２】 前記半導体チップは、裏面に分割された
複数の導体層を形成し、前記複数の導体層はそれぞれ前
記複数のリードフレーム部に対応している請求項１記載
のモールド型半導体装置。2. The molded semiconductor device according to claim 1, wherein the semiconductor chip forms a plurality of divided conductor layers on a back surface, and the plurality of conductor layers respectively correspond to the plurality of lead frame portions. . 【請求項３】 前記半導体チップは、表面に複数の接地
用端子を形成し、前記複数の接地用端子をバイアホール
により前記半導体チップの裏面へ導通させる請求項１記
載のモールド型半導体装置。3. The molded semiconductor device according to claim 1, wherein the semiconductor chip has a plurality of grounding terminals formed on a front surface thereof, and the plurality of grounding terminals are electrically connected to a back surface of the semiconductor chip through via holes.
JP8252732A 1996-09-25 1996-09-25 Mold type semiconductor device Expired - Fee Related JP2836602B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8252732A JP2836602B2 (en) 1996-09-25 1996-09-25 Mold type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8252732A JP2836602B2 (en) 1996-09-25 1996-09-25 Mold type semiconductor device

Publications (2)

Publication Number Publication Date
JPH1098150A JPH1098150A (en) 1998-04-14
JP2836602B2 true JP2836602B2 (en) 1998-12-14

Family

ID=17241500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8252732A Expired - Fee Related JP2836602B2 (en) 1996-09-25 1996-09-25 Mold type semiconductor device

Country Status (1)

Country Link
JP (1) JP2836602B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10205563B4 (en) * 2002-02-11 2009-06-10 Advanced Micro Devices, Inc., Sunnyvale Housed semiconductor device with two die paddles and associated manufacturing method
US9349628B2 (en) 2013-02-25 2016-05-24 Advanced Micro Devices, Inc. Method and an alignment plate for engaging a stiffener frame and a circuit board
WO2023157604A1 (en) * 2022-02-15 2023-08-24 ローム株式会社 Semiconductor device and package structure of semiconductor device

Also Published As

Publication number Publication date
JPH1098150A (en) 1998-04-14

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