JP2836370B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a write per bit.
t) A semiconductor memory device having a function.

[0002]

2. Description of the Related Art An example of a conventional semiconductor memory device of this type is shown in FIG.

In this semiconductor memory device, a write enable (Write) is performed at a leading edge (a change point from an inactive level to an active level) of a row address strobe (Row Address Strobe) signal RASb.
Enable) If the signal WEb is at the active level, it is determined that the mode is the write per bit mode, and the write per bit mode determination circuit 1b that generates the write per bit mode determination signal WPBJ of the active level, and the target product is a write per bit product. A write per bit signal WPBa having a level corresponding to the write per bit mode determination signal WPBJ when a write per bit product signal MDW indicating whether or not there is a write per bit product signal MDW; A delay element DL2, an inverter IV3, and a latch circuit 32, which are provided before the row address strobe signal RAS1 (an inverted signal generated from RASb) with mask data DTM for determining whether to mask the data to be written per bit. Sync to edge A mask data holding circuit 31a for taking in and holding, and an inverter IV4, a NAND gate NA4 and an inverter IV5, and a level corresponding to the mask data held in the mask data holding circuit 31a when the write per bit signal WPBa is at an active level. And a mask control circuit 3a for generating the write per bit mask control signal WMK.

Normally, input data including data to be written is a multi-bit parallel input, so that the mask control circuits 3a are provided in the same number as the number of bits of the parallel input.

Next, the operation of the semiconductor memory device will be described. FIG. 6 is a timing chart of signals at various parts for explaining the operation of the semiconductor memory device.

In the write bit mode determination circuit 1b, when the row address strobe signal RASb becomes a low active level, the write enable signal W
If Eb is the low active level, it is determined that the entry is to the write per bit mode, and the write per bit mode determination signal WPBJ becomes the high active level. Here, in the case of a light-per-bit product, the write-per-bit product signal MDW is at the active level (high level), so that the write-per-bit signal WPBa becomes high. If the product is not a write per bit product, or if the product is not in the write per bit mode, the write per bit signal WPBa remains at a low level.

Next, in the mask control circuit 3a, the NA
The mask data DTM when the row address strobe signal RAS1 goes high by the ND gate NA3
Is determined to be a high level or a low level, and is latched by the latch circuit 32. If the write per bit signal WPBa is at a high level, the inverted signal of the mask data held in the latch circuit 32 is changed to the write per bit mask control signal WM.
Output as K.

Accordingly, if the mask data DTM is at a low level and the product is a write per bit product and has been entered in the write per bit mode, the write per bit mask control signal WM becomes a high level (active level).
The data to be written per bit is masked.

[0009]

In this conventional semiconductor memory device, the mask control circuits 3a are provided by the same number as the number of bits of input data input in parallel, and each of the mask control circuits 3a is provided with a write-per-bit signal WPB. Further, since the configuration is such that the row address strobe signal RAS1 is input, there is a problem that the wiring area for the write per bit signal WPB and the row address strobe signal RAS1 increases and the chip area increases.

An object of the present invention is to provide a semiconductor memory device capable of reducing a wiring area and a chip area.

[0011]

According to the semiconductor memory device of the present invention, a mode is determined at the leading edge of a row address strobe signal, and when the result is a write per bit mode, an active level write per bit mode determination signal is generated. A write per bit mode determination circuit for performing a first level change in synchronization with a leading edge of the row address strobe signal and then performing a second level change to a level corresponding to the write per bit mode determination signal A write per bit signal generating circuit for generating a bit signal; and mask data for determining whether or not to mask the data to be written per bit,
A mask control circuit which captures and holds the level change of the write per bit signal and generates a write per bit mask control signal of a level corresponding to the held mask data when the level after the second level change of the write per bit signal is an active level. And

In addition, a write per bit mode determination circuit outputs an active level signal when a write enable signal is at an active level at a leading edge of a row address strobe signal, and latches and holds an output signal of the logic gate. And a delay means for delaying at least one of the output signal of the latch circuit and the output signal of the logic gate.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, a NAND gate NA1 that outputs an active level signal when the write enable signal WEb is at an active level at the leading edge of the row address strobe signal RAS1, and inverts the level of the output signal of the NAND gate NA1. Inverter IV1, latch circuit 11 for latching and holding the output signal of inverter IV1, delay element D for generating a latch control signal for latch circuit 11 from row address strobe signal RAS1.
L1 and an inverter IV2 for inverting the level of the output signal of the latch circuit 11. The mode is determined by the leading edge of the row address strobe signal RAS1, and when the result is the write per bit mode, the active level is determined in the write per bit mode. A write per bit mode determination circuit 1 generated by delaying signal WPBJ from the leading edge of row address strobe signal RAS1, and NAND gate NA2
And a NOR gate NO1, and when the write per bit product signal MDW is at the active level, changes the first level in synchronization with the leading edge of the row address strobe signal RAS1b, and then changes to a level corresponding to the write per bit mode determination signal WPBJ. A write-per-bit signal generation circuit 2 for generating a write-per-bit mode signal WPB for performing a second level change, and a write-per-bit signal WPB combining the input ends of a row address strobe signal RAS1 and a write-per-bit signal WPBa into one. Figure 5 except input
And the same mask control circuit 3 as that of FIG.

Next, the operation of this embodiment will be described.
FIG. 2 is a timing chart of signals at various parts for explaining the operation of this embodiment.

In the conventional semiconductor memory device shown in FIG. 5, if the write per bit signal WPBa and the row address strobe signal RAS1 are simply integrated by an AND gate or the like, the mask data holding circuit 31 Before the DTM is latched, the result is that the write per bit signal WPB is input to the mask control circuit,
The level may change before the level of the write per bit mask control signal WMK is finally determined, and the mask control becomes unstable.

Therefore, in this embodiment, the mask data D is generated by the first level change of the write per bit signal WPB.
TM is latched, and a write per bit mask control signal WMK of a level corresponding to the mask data DTM latched in accordance with the level after the second level change point is output. That is, the leading edge of the write per bit mode determination signal WPBJ is set to the row address strobe signal RAS.
1 and a first level change for latch is generated at the leading edge of the row address strobe signals RS1 and RAS1b.

As described above, the number of wirings for signals input to the mask control circuit 3 is reduced from two conventionally required to one, so that the wiring area can be reduced by half and the chip area can be reduced. can do.

FIG. 3 and FIG. 4 are a circuit diagram showing a second embodiment of the present invention and a timing chart of signals of respective parts thereof.

This embodiment is slightly different from the first embodiment in the circuit configuration of the write per bit mode determination circuit 1a and the write per bit signal generation circuit 2a, but the basic operation and effects are the same as those of the first embodiment. Since it is the same as the example, further description is omitted.

[0022]

As described above, according to the present invention, the write per bit mode determination signal is generated with a delay from the leading edge of the row address strobe signal, and the first level change is synchronized with the leading edge of the row address strobe signal. After that, a write per bit signal that makes a second level change in accordance with the level of the write per bit mode determination signal is generated, and this write per bit signal is input to the mask control circuit. Since the number of necessary signal wirings can be reduced to one, the wiring area can be reduced to half of that of the conventional one, and therefore, there is an effect that the area can be reduced in a chip.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG. 3;

FIG. 5 is a circuit diagram showing an example of a conventional semiconductor memory device.

FIG. 6 is a timing chart of signals at various parts for explaining the operation of the semiconductor memory device shown in FIG. 5;

[Explanation of symbols]

 1, 1a, 1b Write per bit mode determination circuit 2, 2a, 2b Write per bit signal generation circuit 3, 3a Mask control circuit 11 Latch circuit 31 Mask data holding circuit 32 Latch circuit DL1, DL2 Delay elements IV1 to IV5 Inverters NA1 to NA4 NAND gate NO1, NO2 NOR gate

Claims (2)

(57) [Claims] 1. A write per bit mode determination circuit for determining a mode based on a leading edge of a row address strobe signal and generating an active level write per bit mode determination signal when the result is a write per bit mode; A write per bit signal generating circuit for generating a write per bit signal for performing a first level change in synchronization with a leading edge of the strobe signal and then performing a second level change to a level corresponding to the write per bit mode determination signal; The mask data for determining whether to mask the data to be written per bit is captured and held by the first level change of the write per bit signal, and the level of the write per bit signal after the second level change is obtained. Is at the active level, the write of the level corresponding to the held mask data is performed. And a mask control circuit for generating a per-bit mask control signal. 2. A logic circuit for outputting a signal of an active level when a write enable signal is at an active level at a leading edge of a row address strobe signal, and a latch circuit for latching and holding an output signal of the logic gate. 2. The semiconductor memory device according to claim 1, further comprising: a latch circuit that performs the operation, and a delay unit that delays at least one of an output signal of the latch circuit and an output signal of the logic gate.