JPH1064266A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow an amplifier to correctly latch data immediately before a reset by allowing a CAS signal to rise to generate an address transition detection signal even in such a timing that an access time is determined by a column access time. SOLUTION: A column access buffer 1 receives an external address 15 outputs a column address strobe CAS signal during a data expansion output EDO cycle. On the other hand, data of a sense amplifier 6 selected by a column switch 7 is amplified by a first amplifier 8 and a second amplifier 9, and then latched by a latch circuit 10. Herein, an equalizing signal generating circuit 50 and a second amplifier activation signal generating circuit 52 control the latch circuit 10. Thus, even in such a timing that an access time is determined by a column access time, an address transition detection signal is generated by the rise of the CAS signal, so that the amplifier correctly latches data immediately before a reset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a data extension output (Extended Data Output) of a DRAM.
t: EDO) related to a semiconductor integrated circuit for controlling the function.

[0002]

2. Description of the Related Art In recent years, the problem of memory bottlenecks has emerged in which the operating speed of a memory cannot follow the speeding up of a microprocessor, and the performance of the system is limited by the operating speed of the memory. In order to solve this problem, a dynamic RAM (DRAM) having a higher data transfer rate than the conventional first page mode has been proposed, and EDO is one of them (Japanese Patent Laid-Open No. 6-3).
No. 33393).

FIG. 4 shows a data output method in the EDO mode of the DRAM compared with the first page mode.
It is. FIG. 4 shows the RAS (row address strobe) signal, CAS (column address strobe) signal, address timing, and the state of the I / O terminal in the first page mode and the EDO mode in the read cycle. The OE (output enable) signal is at a low level (hereinafter, referred to as “L”), and the WE (write enable) signal is at a high level (hereinafter, referred to as “H”).
It is.

[0004] In the fast page mode, data from the rising edge of the CAS signal after a time t _OFF is Hi-
Z (high impedance) state, ED
In the O mode, Hi at the rising edge of the CAS signal.
It is characterized in that the data output is held from the next falling edge of the CAS signal until the time t _DCH after the next falling edge of the CAS signal.

A conventional semiconductor integrated circuit for controlling EDO will be described below. FIG. 5 is a block diagram of a conventional EDO control circuit and a data router system, and FIG. 6 is an operation timing chart of each unit in FIG. FIG.
In the figure, reference numeral 1 denotes a column address buffer for generating a column address 16 when an external address 15 is input.
Reference numeral 2 denotes a column decoder which receives a column address 15 as an input and selects a specific column selection line 35. An ATD generating circuit 3 generates an address transition signal (ATD signal) 17 with a column address 16 as an input. 4 is ATD
This is an equalizing signal generating circuit that generates an equalizing signal (FF signal) 18 with a signal as an input. 5 is FF signal 1
8 as an input to the second amplifier activation signal (OBR signal 32
And an XOBS signal 33).

Reference numeral 6 denotes a sense amplifier for amplifying the output of a memory cell (not shown). Reference numeral 7 denotes a column switch which receives the data output of the sense amplifier 6 and outputs a DB signal 19 and an XDB signal 20. 8 amplifies the DB signal 19 and the XDB signal 20 according to the FF signal 18 and
The first which outputs the RD signal 21 and the XIORD signal 22
It is an amplifier. 9 is controlled by the OBR signal 32 and the XOBS signal 33 and controlled by the IORD signal 21 and the XIOR
This is a second amplifier that receives the D signal 22 and outputs the LATIN signal 23. 10 latches the LATIN signal 23 in accordance with the EDOLAT signal 25 and outputs the LATOUT signal 2
4 is a latch circuit that outputs a signal No. 4.

Reference numeral 26 denotes a CAS buffer which receives an CAS signal as an external control signal and generates an XCAS signal 27 as an internal control signal. The XCAS signal 27 has the same phase as the CAS signal. Reference numeral 28 denotes a latch circuit control signal generating circuit which receives the XCAS signal 27 and generates an EDOLAT signal 25. 36 is a column address buffer control signal (XCL1C signal 28) with the XCAS signal 27 as input.
Is generated by the column address buffer control circuit.

An output control signal generating circuit 11 generates an output control signal (CG6 signal 29) with the XCAS signal 27 as an input. An AND circuit 12 takes the logical product of the LATOUT signal 24 and the CG6 signal 29 and outputs a PDTOUT signal 34. A buffer circuit 13 buffers the PDTOUT signal 34 and outputs a DTOUT signal 30. 14 receives the DTOUT signal 30 and
An output transistor that outputs an OUT signal 31. An output circuit is composed of circuits from the output control signal generation circuit 11 to the output transistor 14.

In the semiconductor integrated circuit having the above-described configuration, the column address buffer 1 is controlled by the XCL1C signal 28 generated by the column address buffer control circuit 36 based on the XCAS signal 27, and the external control signal during the EDO cycle. , The external address 15 is accepted while the CAS signal is “H”, and the column address 16
Is output. Note that the CAS signal is directly XC
The external address is controlled by the L1C signal 28, but the XCL1C signal 28 is generated at substantially the same timing from the CAS signal. It is determined by a certain CAS signal.

When the transition of the column address 16 output from the column address buffer control circuit 36 is detected by the address transition detection circuit 3, the address transition detection circuit 3
Generates an ATD signal 17. When the ATD signal 17 is input to the equalization signal generation circuit 4, the FF signal 18 is generated by the equalization signal generation circuit 4, and the data bus is equalized. Note that the equalization of the data bus means equalizing the voltage of the data bus. In the example of FIG. 1, there are DB, XDB, IORD, and XIORD as the data bus to be equalized.

On the other hand, column address 16 is decoded by column decoder 2 and a corresponding column selection line 35
Is selected, the corresponding column switch 7 is opened, and the data of the sense amplifier 6 is transmitted to the first amplifier 8. The data input to the first amplifier 8 is amplified by the FF signal 18 and the IORD signal 21 and the XIORD signal of the complementary data bus.
The signal is transmitted to the second amplifier 9 as a signal 22.

Here, when the data input to the first amplifier 8 is amplified by the FF signal 18, the FF signal 1
8 will be described in detail. That is, the FF signal 1
8 becomes “H”, the DB signal 19 and the XDB signal 20
However, the IORD signal 21 and the XIORD signal 22 are equalized. When the FF signal 18 changes from “H” to “L”, the data bus (DB, XDB, IOR)
D, XIORD) is amplified.

The second amplifier activation signal generation circuit 5 outputs a second amplifier activation signal O from the FF signal 18.
A BR signal 32 and an XOBS signal 33 are generated.
The data input to the amplifier 9 is an OBR signal 32, XO
The signal is amplified and latched by the BS signal 33. Specifically, the data latched by the second amplifier 9 is reset by the transition of the OBR signal 32 from “L” to “H”, and the data is input by the transition of the XOBS signal 33 from “H” to “L”. The data is amplified and latched.

LATIN which is the output of the second amplifier 9
The signal 23 is latched by the latch circuit 10. The latch circuit 10 generates the signal E generated from the CAS signal, that is, the XCAS signal 27 by the latch circuit control signal generation circuit 28.
It is controlled by the DOLAT signal 25. Specifically, CA
While the S signal is "L", the latch circuit 10 is set in the through state, and while the CAS signal is "H", the latch circuit is operated to latch the output of the second amplifier 9.

LATO which is the output of the latch circuit 10
The UT signal 24 is a CG6 signal 29 generated by the output control signal generation circuit 11 based on the CAS signal and the AND circuit 1.
ANDed by 2 and its output, PDTOUT
The signal 34 is buffered by the buffer circuit 13,
The DTOUT signal 30 output from the buffer circuit 13 is finally output to the outside as a DOUT signal (data output) 31 via the output transistor 14.

The signals YA, YB, and YC in FIG. 6 correspond to the addresses COL of the column selection lines 35 provided for each column address in the circuit of FIG.
A, COLB, and COLC. The CG6 signal 29, which is the above output control signal, is normally activated when the CAS signal is "L" during a read cycle.
It is activated during the DO read cycle regardless of the state of the CAS signal. With this configuration, the data is latched while the CAS signal is “H”, so that the EDO function can be realized.

[0017]

When the EDO operation is performed at a high speed, the cycle is shortened. Therefore, the operation is guaranteed even when the CAS signal is "L" period ( _tCAS ) and "H" period is shortened. Need to be done. However, in the above configuration, when the column address setup time is shortened and the access time is determined by the column address access time t _AA , the CA represented by t _CAS
When the period during which the S signal is “L” becomes short, the timing at which data is latched by the latch circuit 10 due to the rise of the CAS signal is determined by the output data L of the second amplifier 9.
There is a disadvantage that the timing becomes earlier than the ATIN 23 determination timing, correct data is not latched, and the EDO operation becomes impossible. For example, when the RAS access time is 60 ns, t _AA is 30 ns, t
_About 10 ns is required for _CAS . The reason that such a problem occurs is that the column address setup time can be set arbitrarily, that is, an asynchronous operation is required, while the data output of the EDO needs to be controlled in synchronization with an external CAS signal.

The present invention solves the above-mentioned conventional problems. A semiconductor device capable of correctly latching data and realizing an EDO function even when the access time is determined by t _AA and t _CAS is shortened. It is an object to provide an integrated circuit.

[0019]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit, comprising: an address buffer to which an external address is input and controlled by an external control input to output an internal address; and an address for detecting a transition of the internal address. A transition detection circuit, an amplifier that is controlled by an amplifier activation signal generated based on an output of the address transition detection circuit and amplifies data, a latch circuit that latches an output of the amplifier, and a latch circuit that is latched by the latch circuit. And a latch circuit control signal generated using a delay signal generated by delaying a signal generated by detecting a transition of the external control input by a predetermined amount. The circuit is controlled to latch data.

According to this configuration, the access time is t _AA
Even when the timing is determined by the above equation, an address transition detection signal is generated by the rise of the CAS signal, and the data immediately before the amplifier is reset can be latched. That is, data corresponding to the last column address input asynchronously, in other words, data to be latched can be latched. Therefore, even when the access time is determined by t _AA and t _CAS is shortened, data can be latched correctly and the EDO function can be realized.

According to a second aspect of the present invention, in the semiconductor integrated circuit of the first aspect, an equalizing signal is generated by an output of the address transition detecting circuit by a first equalizing signal generating circuit, and the first equalizing signal is generated from the equalizing signal. And a second equalizing signal generating circuit having the same configuration as the first equalizing signal generating circuit and the first amplifier activating signal generating circuit. The delay signal is generated by using a second amplifier activation signal generation circuit.

According to this configuration, the second equalizing signal generating circuit and the second amplifier activating signal generating circuit having the same configuration as the first equalizing signal generating circuit and the first amplifier activating signal generating circuit are used. Since the delay signal is generated, the delay signal for controlling the latch circuit can be accurately set. According to a third aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, an internal control signal generated by buffering an external control input by a buffer circuit is used as a first input, and a delay signal is used as a second input. And the flip-flop generates the latch circuit control signal.

According to this configuration, data can be correctly latched even when t _CAS is shortened due to extension of the delay signal, and the delay does not affect the access time.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 shows a part (second amplifier 9, latch circuit 10, latch circuit control signal generation circuit 54, AND circuit) of the semiconductor integrated circuit of FIG.
FIG. 3 shows a detailed diagram of the circuit 12), and FIG. 3 shows an operation timing diagram. In the configuration of FIG. 1, the portion different from the conventional example (FIG. 5) is LA signal which is the output signal of the second amplifier 9.
A generator for generating a signal EDOLAT'60 for controlling the latch circuit 10 that latches the TIN signal 23. The generator includes an equalize signal generation circuit 50, a second amplifier activation signal generation circuit 52, and a latch circuit control signal generation circuit 54. The equalizing signal generating circuit 50 and the second amplifier activating signal generating circuit 52 have the same configuration as the equalizing signal generating circuit 4 and the second amplifier activating signal generating circuit 5.

Hereinafter, the operation of the semiconductor integrated circuit will be described. In this semiconductor integrated circuit, the XCAS signal 27
, The column address buffer 1 is controlled by the XCL1C signal 28 generated by the column address buffer control circuit 36, and during the EDO cycle, the external address 15 is accepted while the CAS signal as the external control signal is "H". The address 16 is output.

When the transition of the column address 16 output from the column address buffer 1 is detected by the address transition detection circuit 3, the address transition detection circuit 3
Signal 17 is generated. When the ATD signal 17 is input to the equalization signal generation circuit 4, the FF signal 18 is generated by the equalization signal generation circuit 4, and the data bus is equalized.

On the other hand, the column address 16 is decoded by the column decoder 2 and the corresponding column selection line 35
Is selected, the corresponding column switch 7 is closed, and the data of the sense amplifier 6 is transmitted to the first amplifier 8. The data input to the first amplifier 8 is amplified by the FF signal 18 and the IORD signal 21 and the XIORD signal of the complementary data bus.
The signal is transmitted to the second amplifier 9 as a signal 22.

The second amplifier activating signal generating circuit 5 outputs the second amplifier activating signal O from the FF signal 18.
A BR signal 32 and an XOBS signal 33 are generated.
The data input to the amplifier 9 is an OBR signal 32, XO
The signal is amplified and latched by the BS signal 33. Specifically, the data latched by the second amplifier 9 is reset by the transition of the OBR signal 32 from “L” to “H”, and the data is input by the transition of the XOBS signal 33 from “H” to “L”. The data is amplified and latched.

The above operation is the same as in the conventional example. Next, the LATIN signal 23, which is the output of the second amplifier 9, is latched by the latch circuit 10. The method of generating the EDOLAT 'signal 60, which is the control signal, is different from the conventional example as described above. In this embodiment, an equalize signal generation circuit 50 and a second amplifier activation signal generation circuit 52
Is newly provided, and the transition of the CAS signal from “L” to “H” is detected by the equalize signal generation circuit 50, and the FF ′ signal 51 is generated from the equalize signal generation circuit 50. An OBR ′ signal 53 is generated from an amplifier activation signal generation circuit 52.

As described above, the second amplifier activation signal generation circuit 52 has the same configuration as the second amplifier activation signal generation circuit 5, and the signal delay amounts are substantially equal. OBR 'signal 53
Is generated by the transition of the CAS signal from "L" to "H", and the OBR signal 32 is generated by the transition of the column address 16. The transition of the column address 16 that generates the OBR signal 32 occurs. Since the CAS signal transitions from "L" to "H" and the column address buffer 1 is enabled, the OBR 'signal 53 becomes the OBR signal.
It occurs at a timing slightly earlier than 32. From the OBR 'signal 53, the latch circuit control signal generation circuit 54 generates E
A DOLAT 'signal 60 is generated.
The signal 60 controls the latch circuit 10. Latch circuit 10
Is output in the same manner as in the prior art.

Since the OBR 'signal 53 is earlier than the OBR signal 32, the EDOLAT' signal 60 is slightly earlier than the OBR signal 32 timing. As a result, the data immediately before the second amplifier 9 is reset by the OBR signal 32 generated by the transition of the CAS signal from “L” to “H”, that is, the LATIN signal 23 of the data to be latched can be latched. Therefore, even if the column address transits several times during the period when the CAS signal is “H” (the period during which the column address is received) and the latch data of the second amplifier 9 is updated, the data corresponding to the last address, that is, true. Can be latched. Thus, even if t _CAS becomes short, if the CAS signal changes from “L” to “H” again and the second amplifier 9 is reset, if the data corresponding to the column address is latched,
Correct data can be latched by the latch circuit 10, and the EDO operation can be guaranteed.

Here, the condition that the data corresponding to the column address needs to be latched when the CAS signal changes from "L" to "H" again to reset the second amplifier 9 will be described in detail. explain. That is, the CAS signal changes from “L” to “H” again, and
When the BR signal 32 changes from “L” to “H”, the second amplifier 9 is reset. That is, LATIN, XLATI
Both N become "L". Since the latch circuit 10 operates by receiving the output of the second amplifier 9, in order to latch correct data, before the second amplifier 9 is reset,
The correct data must be received from the second amplifier 9 and latched.

The latch circuit 10 is controlled by the signal EDOLAT 'signal 60 generated by the latch circuit control signal generating circuit 54 from the CAS signal via the equalizing signal generating circuit 50 and the second amplifier activating signal generating circuit 52. . In other words, while the CAS signal is "L", the latch circuit 10 is in a through state, and while the CAS signal is "H", the latch circuit 10 performs this latch operation and latches the output of the second amplifier 9.

LATO which is the output of the latch circuit 10
The UT signal 24 is a CG6 signal 29 generated by the output control signal generation circuit 11 based on the CAS signal and the AND circuit 1.
ANDed by 2 and its output, PDTOUT
The signal 34 is buffered by the buffer circuit 13,
The DTOUT signal 30 output from the buffer circuit 13 is finally output to the outside as a DOUT signal (data output) 31 via the output transistor 14.

The CG6 signal 29 which is the above output control signal
Is activated during the read cycle, but is activated during the EDO read cycle regardless of the state of the CAS signal.
With this configuration, the data is latched while the CAS signal is “H”, so that the EDO function can be realized. As described above, according to this semiconductor integrated circuit, a signal having the same pulse width as the equalize signal (FF signal) is generated at the rising edge of the external CAS signal, and the second amplifier activation signal (OBR signal 32) is generated from the signal. OB at the same timing as)
'To generate a signal 53, the OBR' R by construction that operates the latch circuit 10 to make a EDOLAT 'signal 60 based on the signal 53, a timing that the access time is determined by t _AA and t _CAS is shortened In such a case, an excellent semiconductor integrated circuit capable of correctly latching data and realizing the EDO function can be realized.

Next, the configurations of the second amplifier 9, the latch circuit 10, the AND circuit 12, and the latch circuit control signal generation circuit 54 will be described in detail with reference to FIG.
As shown in FIG. 2, in this embodiment, a flip-flop is used for the latch circuit control signal generation circuit 54,
When the CAS signal becomes "L", the XCAS signal which is an internal control signal generated by buffering the CAS signal becomes "L", and the output of this flip-flop, that is, EDOL
The AT 'signal becomes "H". As a result, the latch circuit 10
Are in a through state, and the data of the second amplifier 9 is output from the latch circuit 10 as it is. When the CAS signal goes to "H", the XCAS signal also goes to "H", but the OBR 'signal 53 is generated from the transition through a delay by the equalize signal generation circuit 50 and the second amplifier activation signal generation circuit 52. 'The signal 53 causes the output of the flip-flop to go "L". As a result, the data is latched by the latch circuit 10, and the previous data is held until the CAS signal becomes “L” and new data is prepared by the second amplifier 9. During a period from when the CAS signal becomes “H” to when the data is latched by the latch circuit 10, the CAS signal becomes “H” before t _CAS becomes shorter and the output of the second amplifier 9 is determined to be correct data. However, a delay occurs so that correct data can be latched, but this delay does not occur during a period from when the CAS signal becomes "L" to when the latch enters a through state. Therefore, this delay does not adversely affect the access time.

[0037]

According to the semiconductor integrated circuit of the first aspect, even when the access time is determined by t _AA , the data immediately before the address transition detection signal is generated by the rise of the CAS signal and the amplifier is reset. Can be latched, and thus the data to be latched can be latched. Therefore, even when the access time is determined by t _AA and t _CAS is shortened, data can be latched correctly and the EDO function can be realized.

According to the semiconductor integrated circuit of the second aspect,
The delay signal is generated using the second equalizing signal generating circuit and the second amplifier activating signal generating circuit having the same configuration as the first equalizing signal generating circuit and the first amplifier activating signal generating circuit. , The delay signal for controlling the latch circuit can be accurately set. According to the semiconductor integrated circuit of the third aspect, the data can be correctly latched even when t _CAS is shortened due to the extension of the delay signal, and the delay does not affect the access time.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit (EDO control circuit and data router system) according to an embodiment of the present invention.

FIG. 2 shows a part of the semiconductor integrated circuit shown in FIG. 1 (second amplifier, latch circuit, latch circuit control signal generation circuit, AND circuit)
3 is a detailed circuit diagram of FIG.

FIG. 3 is an operation timing chart showing an operation of the semiconductor integrated circuit of FIG. 1;

FIG. 4 is a timing chart for comparing a data output method and a first page mode in an EDO mode of a DRAM.

FIG. 5 is a block diagram of a conventional semiconductor integrated circuit (EDO control circuit and data router system).

FIG. 6 is an operation timing chart showing an operation of the semiconductor integrated circuit of FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Column address buffer 2 Column decoder 3 Address transition detection circuit 4 Equalize signal generation circuit 5 Second amplifier activation signal generation circuit 6 Sense amplifier 7 Column switch 8 First amplifier 9 Second amplifier 10 Latch circuit 11 Output control signal generation circuit 12 AND circuit 13 Buffer circuit 14 Output transistor 26 CAS buffer 36 Column address buffer control circuit 50 Equalize signal generation circuit B 52 Second amplifier activation signal generation circuit 54 Latch circuit control signal generation circuit

Claims (3)

[Claims] An address buffer for receiving an external address and outputting an internal address under the control of an external control input, an address transition detecting circuit for detecting a transition of the internal address, and an output of the address transition detecting circuit. Controlled by the amplifier activation signal generated by
An amplifier for amplifying data, a latch circuit for latching the output of the amplifier, and an output circuit for outputting the data latched by the latch circuit to the outside, and are generated by detecting a transition of the external control input. A semiconductor integrated circuit wherein the latch circuit is controlled by a latch circuit control signal generated using a delay signal generated by delaying a signal by a predetermined amount to latch data. 2. An equalization signal is generated by an output of an address transition detection circuit by a first equalization signal generation circuit, and the amplifier activation signal is generated by the first amplifier activation signal generation circuit from the equalization signal. Generating the delay signal using a second equalizing signal generating circuit and a second amplifier activating signal generating circuit having the same configuration as the first equalizing signal generating circuit and the first amplifier activating signal generating circuit 2. The semiconductor integrated circuit according to claim 1, wherein: 3. A flip-flop further comprising: an internal control signal generated by buffering an external control input by a buffer circuit as a first input; and a flip-flop having the delay signal as a second input. 3. The semiconductor integrated circuit according to claim 1, wherein a circuit control signal is generated.