JP2833022B2 - Frequency conversion circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency conversion circuit, particularly to a frequency conversion circuit suitable for a communication radio.

2. Description of the Related Art In recent years, as wireless devices such as portable wireless telephones have become smaller and lighter, the number of users has continued to increase rapidly. Is an important issue. Such a small, lightweight,
2. Description of the Related Art A frequency conversion circuit using a field effect transistor (hereinafter, referred to as an FET) having a simple circuit configuration and a conversion gain is often used for a reception circuit of a mobile communication wireless device or the like that requires low cost. Hereinafter, referring to FIG. 3 and FIG.
A frequency conversion circuit using an FET will be described. In FIG. 3, reference numeral 1 denotes a dual-gate FET having first and second two gate terminals. Reference numeral 2 denotes a second gate terminal, in which a local signal generated by the local signal source 7 is amplified by the local signal amplifier 8 and input in a state where a DC bias is set from the gate bias terminal 28 via the gate bias resistor 30. 3
Denotes a first gate terminal, and a high frequency signal (hereinafter referred to as RF) from the RF input terminal 9 in a state where a DC bias is set from the gate bias terminal 29 via the gate bias resistor 31.
Signal) is amplified through the RF signal amplifier circuit 33,
input. The RF signal amplifying circuit 33 includes a common source active element 3
5. An input matching circuit 34, an output matching circuit 36, and a DC bias circuit (not shown). A drain terminal 4 outputs an intermediate frequency (hereinafter referred to as IF) signal from an IF output terminal 10 via a matching circuit 37. The source terminal 5 is grounded or grounded at a high frequency. The drain bias circuit is omitted in the figure. FIG. 4 shows the circuit configuration of FIG. 3 in more detail. Portions having the same functions as in FIG. 3 are assigned the same reference numerals, and detailed description is omitted. In FIG. 4, the RF signal amplifying circuit 33 comprises an FET 41 and matching and biasing elements 45, 46, 47, 48, 49, 50, 51, 52, 53. FET 41 has a gate terminal 42 as an input terminal and a drain terminal 43
Is used as an output terminal, and the source terminal 44 is grounded at a high frequency by a high-frequency bypass capacitor 52. The IF signal from the drain terminal 4 of the FET 1 is connected to, for example, the capacitors 19, 20, 2
The signal is output from the IF output terminal 10 through a matching circuit composed of 4, 25, transmission lines 21, 22 and inductors 23, 26. 6 is a drain bias terminal for applying a DC bias, and 27 is a high frequency bias capacitor. The operation of the above configuration will be described below. For example, in the case of a radio,
RF signal, not shown, antenna (antenna)
After inputting the signal and removing unnecessary band signals through a band-pass filter, the signal reaches the RF input terminal 9 shown in FIGS. Thereafter, the RF signal is amplified by a desired gain in the RF signal amplifier circuit 33 in order to improve the noise characteristics, and then the first gate of the dual gate FET 1 is amplified.
To the gate terminal 3. On the other hand, the local signal generated by the local signal source 7 is amplified by the local signal amplifier 8 to a level necessary for the frequency conversion circuit to obtain a desired conversion gain, and then applied to the second gate terminal 2 of the dual gate FET 1. The RF signal and the local signal generate an IF signal as a secondary distortion component due to the nonlinear operation characteristics of the dual gate FET1,
From the drain terminal, it is obtained from the IF output terminal 10 via the matching capacitors 19, 20, 24, 25 and the transmission lines 21, 22. A DC drain bias and a DC gate bias are applied from a drain bias terminal 6 and gate bias terminals 28 and 29, respectively. 30 and 31 are protection resistors for protecting the gate from excessive current. As described above, since the separation characteristics between the first gate terminal 3 and the second gate terminal 2 are good, an RF signal and a local signal can be directly applied without using a directional coupler or the like, and a diode is used. The circuit configuration is simpler than the frequency conversion circuit. Also, since the gate is used as an input terminal, a high conversion gain is obtained, and it is often used for a heterodyne receiving circuit of a radio.

However, in the above-described configuration using the high frequency amplifier using the FET mixer and the grounded source active element, the input matching circuit of the high frequency amplifier for setting the RF input terminal to (generally) 50Ω. Inductors and capacitors will become obstacles in downsizing and integrated circuits (ICs), especially in monolithic ICs in the 1GHz or lower band. An object of the present invention is to solve the above-described problems and to realize a frequency conversion circuit suitable for a monolithic IC with a simpler circuit configuration.

Means for Solving the Problems A frequency conversion circuit according to the present invention comprises a dual gate FET (1) having a source terminal grounded at high frequency and having a first gate terminal and a second gate terminal, and a first gate of the dual gate FET. A second FET (12) in which a drain terminal is connected to a gate terminal and the gate terminal is grounded at a high frequency;
The impedance matching resistor (17) connected between the source terminal of
The high frequency signal of the source terminal of the dual gate FET is input, the local signal is input to the second gate of the dual gate FET, and the output signal is extracted from the drain terminal of the dual gate FET.

According to another aspect of the present invention, there is provided a first FET having a source terminal as an input terminal of a local signal, a second FET having a drain terminal connected to a gate terminal of the first FET, and a gate terminal grounded at a high frequency. And an impedance matching resistor connected between a source terminal of the second FET and a high-frequency ground terminal. A high-frequency signal is input to a source terminal of the second FET. In this configuration, an output signal is taken out from the drain terminal of the FET.

Action The present invention has the above-mentioned configuration, and has a gate-ground type second FET.
By the resistor (17) connected to the source terminal of (12),
Impedance matching with a high-frequency signal source is performed, and an input matching circuit such as an inductor or a capacitor can be omitted, so that a small-sized frequency conversion circuit suitable for a monolithic IC is obtained.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an equivalent circuit of the frequency conversion circuit according to the first embodiment of the present invention. In FIG. 1, components having the same functions as those in FIG. 3 are given the same numbers. 1 is a dual gate FET, 2
Is a second gate terminal of the dual gate FET 1, to which the output terminal of the local signal amplifier 8 connected to the local signal source 7 is connected. Reference numeral 3 denotes a first gate terminal of the dual gate FET 1, to which an output terminal of an RF signal amplifier circuit 11 having an RF input terminal 9 as an input is connected. The RF signal amplifying circuit 11 has a gate terminal 13 grounded or grounded at a high frequency, a drain terminal 14 as an output terminal, a source terminal 15 as an input terminal, and an FET 12 connected to the RF input terminal 9.
And inductor 16, used for setting the DC bias,
It comprises a resistor 17 and a DC blocking capacitor 18. 4 is a drain terminal of the dual gate FET1, and capacitors 19, 20, and
It is connected to the IF output terminal 10 via a matching circuit composed of 24, 25, transmission lines 21, 22, inductors 23, 26, and a high-frequency bias capacitor. Reference numeral 6 denotes a drain bias terminal for applying a DC bias. Reference numerals 28, 30 and 29, 31 denote a gate bias terminal for applying a DC bias to the second gate terminal and the first gate terminal of the dual gate FET 1 and a protection resistor, respectively. The operation of the above configuration will be described below. The RF signal is amplified by a desired gain in an RF signal amplifier circuit 11 to improve noise characteristics from an RF input terminal 9 and applied to the first gate terminal 3 of the dual gate FET 1. Since the RF signal amplifying circuit 11 is configured such that the FET 12 is grounded at the gate terminal 13 or at a high frequency and the source terminal 15 is used as an input terminal, the gate width of the FET 12 and the value of the resistor 17 are selected so that the RF input terminal 9 The input impedance seen can be reduced to 50Ω. On the other hand, the local signal generated by the local signal source 7 is amplified by the local signal amplifier 8 to a level necessary for the frequency conversion circuit to obtain a desired conversion gain, and then applied to the second gate terminal of the dual gate FET 1. The RF signal and the local signal generate an IF signal as a second-order distortion component due to the non-linear operation characteristics of the dual gate FET 1, and the capacitor 1
9,20,24,25, transmission line 21,22, inductor 23,26, high frequency bypass capacitor 27
After removing unnecessary signals such as an RF signal, the signal is extracted from the IF output terminal 10. A DC bias is applied from the drain bias terminal 6 and the gate bias terminals 28 and 29. As is apparent from the above description, according to the present embodiment, since an input matching circuit including an inductor and a capacitor, which causes an increase in the size of the RF signal amplifier circuit, is not necessary, the frequency conversion circuit can be significantly reduced in size. The effect is particularly remarkable when monolithic ICs are used. FIG. 2 is a configuration diagram showing an equivalent circuit of the frequency conversion circuit in the embodiment described in claim 2. In FIG. 2, parts having the same functions as those in FIG. 1 are given the same reference numerals, and detailed description is omitted. In FIG. 2, reference numeral 20 denotes an FET, 21 denotes a gate terminal of the FET 20, 22 denotes a drain terminal of the FET 20, and 23 denotes a source terminal of the FET 20. The gate terminal 21 is connected to the output terminal of the RF signal amplifier circuit 11 which receives the RF input terminal 9 as an input. The source terminal 23 is connected to the output terminal of the local signal amplifier 8 while being connected to the local signal source 7. Drain terminal 22 is a capacitor 19, 20, 24, 25, transmission line 21, 22, inductor 23, 26, high frequency bypass capacitor
It is connected to the IF output terminal 10 via a matching circuit composed of 27. The RF signal amplifying circuit 11 has a gate terminal 13 grounded or grounded at a high frequency, a drain terminal 14 as an output terminal, a source terminal 15 as an input terminal, and an FET 12 connected to the RF input terminal 9.
And inductor 16, used for DC bypass setting,
It comprises a resistor 17 and a DC blocking capacitor 18. 6 is FET
Reference numeral 20 denotes a drain bias terminal, reference numerals 29 and 31 denote gate bias terminals and protection resistors. 32 is a source bias resistor for direct current feedback of the FET 20. In the above configuration,
Hereinafter, the operation will be described. The RF signal is supplied from the RF input terminal 9 to the RF signal amplifier circuit 11 for a desired gain to improve noise characteristics.
It is amplified and applied to the gate terminal 21 of the FET 20. Since the RF signal amplifier circuit 11 has a configuration in which the FET 12 is grounded at the gate terminal 13 or grounded at a high frequency, and the source terminal 15 is used as an input terminal, the RF input terminal 9 is selected by selecting the gate width of the FET 12 and the value of the resistor 17. Input impedance can be set to 50Ω. On the other hand, after the local signal generated by the local signal source 7 is amplified by the local signal amplifier 8 to a level necessary for the frequency conversion circuit to obtain a desired conversion gain,
0 is applied to the source terminal. RF signal and local signal are FET
Generates an IF signal as a second-order distortion component due to non-linear operation characteristics such as 20 mutual conductance, drain conductance, gate-source capacitance, and eliminates unnecessary signals such as local signals and RF signals with a matching circuit connected to the drain 22 After doing
Extracted from IF output terminal 10. A DC bias is applied from the drain bias terminal 6, the gate bias terminal 29, and the source bias resistor 32. As is apparent from the above description, according to the present embodiment, a single-gate FET is used, and a frequency conversion circuit having a simpler circuit configuration than the first embodiment of FIG. It is possible to achieve simplification and downsizing of a circuit in which the input matching circuit of the signal amplification circuit is omitted.

Effect of the Invention As described above, the frequency conversion circuit of the present invention performs impedance matching with a high-frequency signal source by selecting the value of the impedance matching resistor, while performing RF amplification of a gate-grounded FET, Frequency conversion with little noise is performed. Also, even without using a matching circuit such as an inductor or a capacitor, impedance matching with a high-frequency signal source is performed, so that the circuit configuration is greatly simplified and the frequency conversion circuit can be downsized. large.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an equivalent circuit of the frequency conversion circuit according to the first embodiment of the present invention, FIG. 2 is a configuration diagram of an equivalent circuit of the frequency conversion circuit according to the second embodiment of the present invention, and FIG. FIG. 4 is a configuration diagram of a conventional frequency conversion circuit, and FIG. 4 is a more detailed configuration diagram of an equivalent circuit of the conventional frequency conversion circuit. 1, dual gate FET, 12, 41, FET 2, second gate terminal of dual gate FET, 3, first gate terminal of dual gate FET, 4, 14, drain terminal, 5, 15
... Source terminal, 13,42 ... Gate terminal, 6 ... Drain bias terminal, 7 ... Local signal source, 8 ... Local signal amplifier, 9 ... RF input terminal, 10 ... IF output terminal, 11 ... … RF
Signal amplification circuit (gate ground), 16, 23, 26 ... inductor, 17, 30, 31 ... resistor, 18, 19, 20, 24, 25, 27 ... capacitor, 21, 22 ... transmission line, 28 , 29 …… Gate bias terminal.

Continuation of front page (72) Inventor Shutaro Nanbu 1006 Kazuma Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-63-187701 (JP, A) JP-A-63-142716 ( JP, A) JP-A-57-76903 (JP, A) JP-A-59-176909 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03D 7/12

Claims (2)

(57) [Claims] 1. A dual gate FE having a source terminal grounded at a high frequency and a first gate terminal and a second gate terminal.
T, a second terminal in which a drain terminal is connected to a first gate terminal of the dual gate FET, and the gate terminal is grounded in high frequency.
And an impedance matching resistor connected between a source terminal of the second FET and a high-frequency ground terminal. A high-frequency signal is input to a source terminal of the second FET, A frequency conversion circuit for inputting a local signal to a second gate of a dual gate FET and extracting an output signal from a drain terminal of the dual gate FET. A first terminal having a source terminal as an input terminal of a local signal;
And a second FET in which a drain terminal is connected to a gate terminal of the first FET and the gate terminal is grounded at high frequency.
And an impedance matching resistor connected between a source terminal of the second FET and a high-frequency ground terminal. A high-frequency signal is input to a source terminal of the second FET, and the first A frequency conversion circuit that extracts the output signal from the drain terminal of the FET.