JP2832921B2 - Functional simulation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function simulation device for simulating the operation of a logic circuit.

[0002]

2. Description of the Related Art In recent years, digital circuits have been greatly developed into LSIs, and have been used in various fields.
Since the LSI cannot directly observe the internal signal, it is necessary to check the operation of the circuit in advance, and as the scale increases, the technology of simulating the operation of the circuit becomes more and more important.

In a function simulation of a circuit, for example, when simulating an arithmetic and logic operation circuit,
It is not only necessary to handle a binary logical operation consisting of purely logical signals 0 and 1, but it is necessary to perform a simulation in consideration of various states in an actual circuit. That is, in an actual circuit, a logic signal is a don't care (hereinafter, represented by a symbol X) or a high impedance (hereinafter, represented by a symbol Z). 1,
It is necessary to handle the signal as a quaternary logic signal that takes any one of X and Z.

Conventionally, when simulating an arithmetic and logic operation circuit that handles a multi-digit multi-valued logic signal, it is complicated and difficult to directly obtain the result of the arithmetic and logic operation between the multi-valued logic signals by some kind of operation. Because it is difficult, an operation table storing the operation result for each bit is provided in advance, and the operation table is subtracted for each bit according to the value of the input signal to be operated, so that the operation table is obtained for each digit. The processing for obtaining the operation result was performed. The calculation result for each bit obtained in this manner is integrated with the bit width to become a simulation result.

[0005]

However, according to the function simulation apparatus in the above-mentioned prior art,
Since a process of obtaining an operation result for each bit is performed, when simulating an arithmetic logic operation circuit between multi-valued logic signals having a plurality of bit widths, there has been a problem that the simulation time is greatly increased.

It is an object of the present invention to provide a function simulation apparatus capable of performing a high-speed simulation of a plurality of digits in a function simulation for executing an arithmetic and logic operation between multi-valued logic signals having a plurality of bit widths. With the goal.

[0007]

In order to solve the above-mentioned problems, a function simulation apparatus according to the present invention has a multi-bit width of which each bit is represented by one of four values of logical signals 0, 1, X and Z. A functional simulation apparatus for simultaneously simulating all bits of an arithmetic and logic operation between input signals, wherein a 0 drive bit indicating whether a logical signal 0 can be taken for each bit of the input signal, a logical signal Encoding means for encoding into two encoded bits of one drive bit indicating whether or not 1 can be taken, and outputting the encoded bit as an encoded input signal; Z-> X conversion means for outputting a conversion-coded input signal obtained by converting a coded bit into a coded bit for a logical signal X; Is, 0 drives word transform coding an input signal, 0 based on the 1 drives word, corresponding to the result of the arithmetic logic to be simulated
Output signal evaluation means for obtaining an encoded output signal consisting of a drive word and one drive word;
Decoding means for restoring each drive bit in a drive word and one drive word to a representation of any one of four logical signals of logical signals 0, 1, X and Z, and using the result as an output signal; I have.

The Z-> X conversion means receives the coded input signal from the coding means, calculates the logical sum of 0 drive word and 1 drive word of the coded input signal, and converts the result into an intermediate result. AND output means, and the intermediate result is input, bit inversion of each bit of the intermediate result is determined, and the result is output as a Z-> X conversion mask. Z-> X
The conversion mask is input, the logical sum of the 0 drive word of the coded input signal and the Z-> X conversion mask is obtained, and the result is output as the 0 drive word of the converted coded input signal. It may comprise Z-> X conversion mask processing means for calculating the logical sum of the drive word and the Z-> X conversion mask, and outputting the result as one drive word of the conversion encoding input signal.

[0009]

According to the above means, in the functional simulation apparatus of the present invention, each bit of the multi-bit input signal represented by any one of the four values of the logical signals 0, 1, X, and Z is
The encoding means encodes two bits, a 0 drive bit indicating whether a logical signal 0 can be taken and a 1 drive bit indicating whether a logical signal 1 can be taken. Further, in the coded input signal, the coded bit portion for the logic signal Z is converted into coded bits for the logic signal X by the Z-> X conversion means. On the basis of the 0 drive word and the 1 drive word of the transform coded input signal, the output signal evaluation means outputs an encoded output consisting of the 0 drive word and the 1 drive word corresponding to the operation result of the arithmetic logic operation to be simulated. Find the signal. At that time, the output evaluation means determines that both drive words are 0,
Since it is a binary logic signal consisting of 1, an encoded output signal corresponding to the result of the arithmetic and logic operation to be simulated is obtained by a logical operation on all bits at once. Each drive bit in the 0 drive word and 1 drive word of the encoded output signal thus obtained is
By the decoding means, the output signal is restored to an output signal represented by any one of four values of logic signals 0, 1, X, and Z.

Further, in the Z-> X conversion means, each bit of the intermediate result output from the logical sum evaluation means is inverted by the bit inversion means to form a Z-> X conversion mask. The coded input signal and the Z-> X conversion mask are input, and the logical sum of 0 drive word of the coded input signal and the Z-> X conversion mask, and 1 drive word of the coded input signal and Z-> X Find the logical sum of the conversion mask. As a result, the former is output as a drive word of the transform coded input signal, the latter is output as a drive word of the transform coded input signal,
The result of the Z-> X conversion is obtained.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A function simulation apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram illustrating a configuration example of a functional simulation device. In the figure, reference numeral 1 denotes an encoding means, which receives an input signal group including a plurality of multi-bit width input signals in which each bit is represented by one of four values of logical signals 0, 1, X, and Z; Each bit of each input signal of the input signal group 1 is encoded with two bits: a 0 drive bit indicating whether a logical signal 0 can be taken and a 1 drive bit indicating whether a logical signal 1 can be taken.

More specifically, FIG. 2 shows the correspondence between input and output when the encoding means 1 performs encoding. In FIG. 2, "logic signal" indicates four values of 0, 1, X (don't care), and Z (high impedance). "0 drive bit"
When it is “1”, it indicates that the corresponding “logic signal” is likely to take the logic signal 0, and when it is “0”, it is unlikely that the corresponding “logic signal” takes the logic signal 0, and “1 drive bit” is “1”. When it is, it indicates that the corresponding logic signal has a high possibility of taking the logical value 1, and when it is "0", it indicates that the possibility of taking the reverse value is small.

FIG. 3 shows a specific example of encoding a logic signal having a 4-bit width. In FIG. 3, “logic signal” is an example of a 4-bit width logic signal, and is “01XZ”. “0 drive word” is a collection of 0 drive bits when each bit is encoded, and “1 drive word” is a collection of 1 drive bits when each bit is encoded. The encoded signal of the logical signal “01XZ” according to the encoding correspondence shown in FIG. 2 is expressed by two drive words of 0 drive word “1010” and 1 drive word “0110”.
The result of encoding the input signal (group) by the encoding means 1 as described above is referred to as an encoded input signal (group).

Reference numeral 2 denotes a Z-> X conversion means to which a group of coded input signals is inputted, and for each bit of each coded input signal,
If the bit is a coded bit for the logic signal Z, the coded bit is converted to a coded bit for the logic signal X. The encoded input signal (group) is Z-> X conversion means 2
Is referred to as a transform-encoded input signal (group).

Numeral 3 is an output signal evaluation means to which a group of transform-encoded input signals is input, and evaluation (simulation) of functions such as logical operations using 0 drive word and 1 drive word of each transform-encoded input signal. To obtain and output an encoded output signal consisting of 0 drive word and 1 drive word representing the evaluation result. The evaluation (simulation) here is performed in correspondence with various arithmetic logic operations including multi-bit width multi-input multi-output.

More specifically, when evaluating the AND operation of two inputs and one output, the 0 drive word of the coded output signal is obtained by combining the 0 drive word of the transform coded input signal A with the 0 drive word of the transformed coded input signal. B is obtained by taking the logical sum of the 0 drive words of B, and 1 drive word of the encoded output signal is 1 of the transform encoded input signal A.
It is obtained by taking the logical product of the drive word and one drive word of the transform coding input signal B.

When evaluating a logical OR operation of two inputs and one output, the 0 drive word of the coded output signal is the same as the 0 drive word of the transform coded input signal A and the 0 drive word of the transformed coded input signal B. And one drive word of the encoded output signal is the logical sum of one drive word of the transformed encoded input signal A and one drive word of the transformed encoded input signal B. Required by

When evaluating the logical NOT operation, the output signal evaluation means 3 determines the 0 drive word which is a collection of the 0 drive bits of the encoded output signal by using the 0 drive word of the transform coding input signal. It is determined by exchanging one drive word of the transform encoded input signal.
Reference numeral 4 denotes a decoding means to which a group of coded output signals is inputted,
Each encoded output signal consisting of one drive word and one drive word is decoded into an output signal represented by one of four values of logical signals 0, 1, X, and Z.

FIG. 5 is a functional block diagram showing a detailed configuration example of the Z-> X conversion means 2 described above.
There is no need to perform X conversion, and Z-> X conversion is performed collectively. In the figure, reference numeral 51 denotes a logical sum evaluating means to which a group of coded input signals coded by the coding means 1 of FIG. 1 is input, and a logical sum of 0 drive word and 1 drive word of each coded input signal. Ask for. The result of the encoded input signal obtained by the OR evaluation means is called an intermediate result.

Reference numeral 52 denotes a bit inverting means to which an intermediate result is input, and obtains bit inversion of each bit of the intermediate result. The result of the intermediate result obtained by the bit inversion means is called a Z-> X conversion mask. 53 is a Z-> X conversion mask processing means, which receives the coded input signal and the Z-> X conversion mask, and drives the 0-drive word of the coded input signal and Z->
The logical sum with the X conversion mask and the logical sum of one drive word of the encoded input signal and the Z-> X conversion mask are obtained.
Then, a transform coding input signal having the former result as 0 drive word and the latter result as 1 drive word is output.

The operation of the functional simulation apparatus according to the embodiment of the present invention configured as described above will be described. As an example of the operation to be subjected to the function simulation, a 2-bit 1-output AND operation with a 4-bit width will be described with reference to a schematic diagram showing a process of converting each signal group shown in FIG.

First, as shown in FIG. 4, the input signal group is
A 4-bit input signal A whose logical value is “01XZ”;
2 of the 4-bit input signal B whose logical value is “0101”
It is assumed that the input signal is composed of two input signals to be operated. This input signal group is converted by the encoding means 1 into an encoded input signal group according to the encoding table shown in FIG. That is, the input signal A is converted into an encoded input signal A consisting of a 0 drive word having a logical value of “1010” and a 1 drive word having a logical value of “0110”. Similarly, the input signal B is converted to a 0 drive word. It is converted into an encoded input signal B composed of “1010” and one drive word “0101” (see “encoded input signal group” in FIG. 4).

Next, the coded input signal is converted by the Z-> X conversion means 2 into a group of coded input signals. More specifically, the Z-> X conversion means 2 shown in FIG.
Will be described with reference to FIG. 6 showing a process of performing Z-> X conversion. In FIG. 6, the “logic signal” is the input signal A
And “encoded input signal” is an encoded input signal A obtained by encoding the input signal A. The coded input signal A is converted into 0 drive word “1010” and 1
The logical sum with the drive word "0110" is obtained to obtain an intermediate result "1110" (see "Intermediate result" in FIG. 6), and furthermore, a Z-> X conversion mask in which each bit is inverted by the bit inversion means 52. "0001" is obtained (see "Z-> X conversion mask" in FIG. 6).

Subsequently, Z-> X conversion mask processing means 53
Is the 0 drive word “1010” of the encoded input signal A.
And "1011" obtained by performing a logical sum of the Z-> X conversion mask "0001" as the 0 drive word of the conversion coded input signal A, and 1 drive word "0110" of the coded input signal A "0111" obtained by ORing this Z-> X conversion mask "0001" is set as one drive word of the conversion coded input signal A (see "Conversion coded input signal" in FIG. 6).

In the above Z-> X conversion mask, the logical value 1
Is a bit corresponding to the logical value Z in the original input signal. Therefore, by taking the logical sum of each drive word of the encoded input signal and the Z-> X conversion mask, the encoded bit for the logical signal Z is obtained. Are converted into encoded bits for the logic signal X. The “logic signal corresponding to the transform coding input signal” in FIG. 6 is obtained by inversely coding (decoding) the “transform coding input signal” according to FIG. Has been converted to.

As described above, the Z-> X conversion is performed by the Z-> X conversion means 2 on the coded input signal B.
As a result of the Z-> X conversion, since the first bit of the input signal A is the logic signal Z, this bit is converted into a code bit for the logic signal X, The drive word is “1011” and one drive word is “0111”. Encoded input signal B
, The input signal B does not have the logic signal Z, so that the 0 drive word of the transform coded input signal B is “1010” and the 1 drive word is “0101” (see the “transformed coded input signal of FIG. 4”). Group "). In this way, the bits of the logic signal Z are converted into the logic signal X by the batch processing without Z-> X conversion for each bit by the Z-> X conversion means 2.

Thereafter, the output signal evaluation means 3 evaluates (simulates) various logical operations and the like for the transform coded input signal A and the transform coded input signal B by using these as inputs. In order to simulate the two-input one-output AND operation in this embodiment, if at least one of the two input signals is zero, the operation result becomes zero.
Since the logical sum of the 0 drive bits that are highly likely to be 0 becomes the 0 drive bit of the operation result, and the operation result becomes 1 if both of the two input signals are 1, the logical value may be 1. The logical product of one drive bit having a higher value becomes one drive bit of the operation result. That is, the 0 drive word of the coded output signal corresponding to the operation result is obtained by the logical sum of the 0 drive words of the transform coded input signal A and the transform coded input signal B. The logical product of one drive word of A and the transform encoding input signal B yields one drive word of the encoded output signal corresponding to the operation result.

In the example of FIG. 4, 0 of the encoded output signal
The drive word is the logical sum “1011” of the 0 drive word “1011” of the transform coded input signal A and the 0 drive word “1010” of the transform coded input signal B, and 1 drive word of the coded output signal. Is the logical product "0101" of one drive word "0111" of the transform encoded input signal A and one drive word "0101" of the transformed encoded input signal B (see "encoded output signal group" in FIG. 4). ).

Finally, each coded bit of each coded output signal of the coded output signal group is decoded by the decoding means 4 into four-valued logic signals 0, 1, X and Z. In the case of this embodiment, each encoded bit is set to (0 drive bit, 1 drive bit,
Drive bit), it is decoded as follows: The fourth encoded bit is (1, 0), the corresponding logical signal is 0, and the third encoded bit is (0, 1).
, The corresponding logical signal is 1, the second coded bit is (1, 0), the corresponding logical signal is 0, and the coded bit is 1.
The bit is (1, 1) and the corresponding logic signal is X.

As a result, the output signal becomes "010X" (see "output signal group" in FIG. 4). As described above, a simulation can be performed collectively without drawing an operation table for implementing a target arithmetic and logic operation for each bit.

[0031]

As described above, according to the function simulation apparatus of the present invention, the encoding means converts each bit of the multi-bit logic signal represented by multi-value into 0 drive bit and 1 drive bit. By encoding into an encoded input signal composed of two drive bits and treating the output evaluation means as a binary signal and processing a plurality of digits collectively, there is no need to obtain the operation result for each bit, and a plurality of The effect is that the simulation of the arithmetic logic operation circuit between multi-valued logic signals having a bit width can be speeded up. As a result, there is an effect that the speed of the functional design verification of the logic circuit or the logic device is improved and the efficiency is improved.

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating a configuration of a functional simulation device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a correspondence relationship between input and output of encoding of quaternary logic signals 0, 1, X and Z in an encoding unit 1 in the embodiment.

FIG. 3 is a diagram showing a result of encoding a logical signal having a 4-bit width in the embodiment.

FIG. 4 is a schematic diagram showing a process of converting each signal group, taking as an example an arithmetic operation to be subjected to a functional simulation in the embodiment, a 2-input 1-output AND operation having a 4-bit width.

FIG. 5 is a functional block diagram showing one configuration example of a Z-> X conversion means in the embodiment.

FIG. 6 is a diagram showing a process in which the input signal A is Z-> X converted by the Z-> X conversion means of FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Encoding means 2 Z-> X conversion means 3 Output signal evaluation means 4 Decoding means 51 Logical sum evaluation means 52 Bit inversion means 53 Z-> X conversion mask processing means

Claims (2)

(57) [Claims] 1. Each bit is a logical signal 0, 1, X, Z
A functional simulation apparatus for simultaneously simulating all bits of an arithmetic logic operation between multi-bit input signals represented by any one of values, wherein a logic signal 0 is provided for each bit of the input signal. Encoding means for encoding a 0 drive bit indicating whether or not a logical signal 1 can be taken and an encoded bit consisting of two drive bits of 1 drive bit to output as a coded input signal; Z-> X conversion means for outputting a conversion coding input signal obtained by converting a coding bit corresponding to the logic signal Z into a coding bit corresponding to the logic signal X among the bits of the signal; and a conversion coding input signal. , Based on the 0 drive word and 1 drive word of the transform coding input signal, 0 drives word to the output signal evaluating means for determining the encoded output signal comprising one drive word, 0 drive words of a coding output signals, each drive bit in one drive word, logic signals 0, 1, X, Z
Decoding means for restoring the expression to any one of the four values of the logical signal and using the result as an output signal. 2. The Z-> X conversion means receives an encoded input signal from the encoding means, calculates a logical sum of 0 drive word and 1 drive word of the encoded input signal, and outputs the result as an intermediate result. OR evaluation means for outputting as a result, bit intermediate of the intermediate result is input, bit inversion of each bit of the intermediate result is obtained, and the result is output as a Z-> X conversion mask; The Z-> X conversion mask is input, the logical sum of the 0-drive word of the coded input signal and the Z-> X conversion mask is obtained, and the result is converted to the 0 of the coded input signal.
Z-> X conversion mask processing means for outputting as a drive word, calculating the logical sum of one drive word of the coded input signal and the Z-> X conversion mask, and outputting the result as one drive word of the converted coded input signal 2. The functional simulation device according to claim 1, comprising: