JP2831818B2 - Tracking error signal generator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a tracking error signal generation device for an optical disc player, and more particularly to a tracking error signal generation device using a time difference detection method.

2. Description of the Related Art In an optical disk player that plays a disk-shaped recording medium (hereinafter, simply referred to as a disk) such as a video disk or a digital audio disk, an optical spot for reading information of a pickup has a recording track regardless of the eccentricity of the disk. A tracking servo device for controlling so as to always accurately track is indispensable.

This tracking servo device generates a tracking error signal corresponding to the amount of deviation of the information reading light spot with respect to the recording track of the disk in the disk radial direction, and provides a tracking actuator for biasing the information reading light spot in the disk radial direction. Performing position control of the information reading light spot with respect to the recording track by driving according to the tracking error signal,
This is a so-called closed servo control system.

Further, in such a servo device, at the time of a so-called jump operation in which the information reading light spot jumps over the recording track, the servo loop is opened (opened), and an acceleration signal having a polarity corresponding to the jump direction is supplied to the tracking actuator. At the time of zero crossing of the tracking error signal level during operation, a deceleration signal of the opposite polarity to the acceleration signal is supplied to the actuator for a certain period of time to apply a certain braking force, then the servo loop is closed (closed) and the servo is closed. (See Japanese Patent Application Laid-Open No. 2-79228).

As a method of generating a tracking error signal, a three-beam method, a push-pull method, a time difference detection method, and the like are known.
Among these generation methods, the time difference detection method is disclosed in Japanese Patent Application Laid-Open No. 57-1814.
As is apparent from the description of JP-A-33-33, four photoelectric conversion elements 41a to 41d arranged so that the light receiving surface is divided into four as shown in FIG. 3 are used as light receiving means for receiving the light beam reflected from the disk. A so-called quadrant photodetector 41 composed of 41d is used. Assuming that each output signal of the quadrant photodetector is Sa, Sb, Sc, Sd, the total sum of the output signals Sa + Sb + Sc + Sd is read.
It is used for signal reproduction as an RF signal. The adder 42 adds the sum signals Sa + Sc and Sb + Sd of the output signals from the photoelectric conversion elements which are in a diagonal relationship with respect to the intersection of two division lines on the light receiving surface.
43, and the two diagonal sum signals Sa + Sc, S
The phase difference of b + Sd is obtained. The amount of this phase difference corresponds to the amount of tracking deviation, and whether the phase difference is advanced or delayed corresponds to which direction of tracking. That is, of the phase difference between the outputs of these optical conversion elements, a phase change component that changes according to the amount of deviation of the information reading light spot with respect to the recording track in the disk radial direction is detected and derived as a tracking error signal. Things.

Thus, two diagonal sum signals are used to detect the phase difference.
Sa + Sc and Sb + Sd are separately supplied to a phase comparator (PC) 46 via limiters (LIM) 44 and 45, and a tracking error signal is obtained from a phase difference output of the phase comparator 46. The polarity and level of the tracking error signal indicate the direction and amount of deviation of the information reading beam spot in the disk radial direction with respect to the recording track of the disk. This tracking error signal is supplied to a tracking actuator (not shown).
The total output (Sa + Sc + Sb + Sd) of the outputs of the photoelectric conversion elements 41a to 41d is obtained by the adders 47 to 49 and is derived as a read RF signal for reproduction.

FIG. 4 shows a conventional phase comparison circuit. In this phase comparison circuit, four D-type flip-flops 1 to 4 are provided. These D-type flip-flops 1-4 are ECL
(Emitter Coupled Logic). The clock terminals CK and the clear terminal CL of the D-type flip-flops 1 and 3 are non-inverting inputs, and input signals are input as they are. Also, the clock terminals CK and the clear terminal CL of the D-type flip-flops 2 and 4
Is an inverting input, and an input signal is inverted and input.
The clock terminals CK of the D-type flip-flops 1 and 2 and the clear terminal CL of the D-type flip-flops 3 and 4 have a first terminal.
The RF signal (a pulse signal the diagonal sum signals Sa + Sc obtained through the limiter 44) is supplied from the input terminal IN _1. The second RF terminal is connected to the clock terminal CL of the D-type flip-flops 1 and 2 and the clear terminal CK of the D-type flip-flops 3 and 4.
Signal (a pulse signal of the diagonal sum signals Sb + Sd obtained through the limiter 45) is supplied from the input terminal IN _2.

The output signals of the D-type flip-flops 1 and 2 are ORed by the OR circuit 5 and supplied to the subtractor 7 via the LPF 6. The output signals of the D-type flip-flops 3 and 4 are ORed by the OR circuit 8 and supplied to the subtractor 7 via the LPF 9.

In the phase comparison circuit having such a configuration, if the first RF signal is S ₁ , its inverted signal is S ₁₁ , the second RF signal is S ₂ , and its inverted signal is S ₂₂ , the first RF signal S ₁ Phase of the second RF
If you are ahead signal S _2, the output signal from the D-type flip-flops 1 and 2 as shown in FIG. 5 (A) S _3, S ₄ are obtained. The output signals S ₃ and S ₄ are added by the OR circuit ₅ to become a signal S ₅ and supplied to the LPF 6. At this time, no output signal is obtained from the D-type flip-flops 3 and 4.

On the other hand, when the phase of the _first RF signal S ₁ is behind the phase of the second RF signal S ₂ , as shown in FIG. 5B, the output signals S ₆ , S ₇ is obtained.
The output signals S ₆ and S ₇ are added by the OR circuit ₈ to become a signal S ₈ and supplied to the LPF 9. At this time, no output signal is obtained from the D-type flip-flops 1 and 2.

Since the difference between the signals obtained through the LPFs 6 and 9 is obtained in the subtractor 7, the phase of the _first RF signal S1 is changed to the second RF signal.
If you are ahead of the signal S ₂ is the signal indicating the positive phase difference is obtained as a tracking error signal, the first RF signals S ₁
Of the case where the phase is delayed from the second RF signal S ₂ signal indicating the negative phase difference is obtained as a tracking error signal.

FIG. 6 specifically shows the configuration of the D-type flip-flop. In this flip-flop, transistors 11 and 15, transistors 13 and 17,
19 and 25, transistors 18 and 22 and transistor 21
And 26 each constitute a differential amplifier. Transistor
The clock terminal is the base of 15 and the base of transistor 18
Commonly connected to CK. Further, the transistor 17 and the base and the base of the transistor 26 are commonly connected to the clear terminal CL. Resistors 31, 32, and 33 are connected in series between the ground (GND) and the voltage V _EE (−5 V). Further, resistors 34, 35, 36 and 37 are connected between the ground and the collectors of the transistors 12, 16, 20 and 23.

Transistors 11 and 22 are connected to the connection point between resistors 31 and 32
Connected to the base. The connection point between the resistors 32 and 33 is connected to the bases of the transistors 13 and 21.
The emitters of the transistors 11 and 15 are connected to the collector of the transistor 13, and the emitters of the transistors 18 and 22 are connected to the collector of the transistor 21. A current source 14 is connected between the emitters of transistors 13 and 17 and voltage _VEE.
Similarly, a current source 24 is connected between the emitters of the transistors 21 and 26 and the voltage _VEE . The collector of the transistor 17 is connected to the base of the transistor 12, the collector of the transistor 16, and the base of the transistor 19. Collector of transistor 12, transistor
The base of 16, the collector of transistor 11 and the base of transistor 25 are connected together, and the emitters of transistors 12 and 16 are connected to the collector of transistor 15. The collector of transistor 26 is connected to the base of transistor 20 and the collectors of transistors 23 and 25. The collector of the transistor 19, the collector of the transistor 20, and the base of the transistor 23 are commonly connected. The emitter of the transistor 19 is connected to the collector of the transistor 18 and the emitter of the transistor 25.
Further, the emitters of the transistors 20 and 243 are connected to the collector of the transistor 22. The collector of the transistor 23 is connected to the output terminal Q.

In the D-type flip-flop having such a configuration, when the clock terminal CK and the clear terminal CL are both at the low level, the transistors 17, 26, 15 and 18 are turned off, and the transistors 13, 21, 11 which are paired with these transistors are turned off.
And 22 are turned on. The transistors 23 and 20 maintain the state before the transistors 22 and 21 are turned on.Before the clock terminal CK and the clear terminal CL are both at the low level, the transistor 23 is on and the transistor 20 is off. The state is maintained. Therefore, the potential of the output terminal Q becomes low because the transistors 23, 22 and 21 are on.

Then, the input level of the clock terminal CK, as shown in FIG. 7 (a) is changed from a low level at time t ₁ to a high level,
Assuming that the clear terminal CL remains at the low level, the transistor 18 is turned on and the transistor 22 is turned off.
As a result, the transistors 20 and 23 are turned off because no current flows. The transistor 25 is turned off because the potential at the collector point a of the transistor 12 is low as shown in FIG. 7C. Therefore, the potential of the output terminal Q changes to a high level as shown in FIG.
Since the transistors 22 and 23 are turned off in this order from the rise of the input level of the clock terminal CK to the change of the potential of the output terminal Q to the high level, a delay occurs between them.

Then, the input level of the clear terminal CL as shown in FIG. 7 (b) is changed from a low level at time t ₂ to a high level,
Assuming that the clock terminal CK remains at the high level, the transistor 26 is immediately turned on, so that the potential of the output terminal Q is immediately inverted from the high level to the low level as shown in FIG.

As described above, the time until the level change of the output terminal Q occurs differs between the case where the input signal level of the clock terminal CK changes to a high level and the case where the input signal level of the clear terminal CL changes to a high level. . Clock terminal CK
Tau ₁ a delay time from the rise of the input signal until the rise of the output terminal Q of _the delay time tau ₂ from the rising of the input signal of the clear terminal CL and the fall of the output terminal Q
Then, τ ₁ > τ ₂ . The time difference is τ ₁ −τ ₂
≒ 3nsec. Although the delay time is ignored in FIG. 7, the input signal of the clock terminal CK and the clear terminal CL are actually shown in FIGS. 8 (a) and 8 (b).
As shown in FIG. 8 (c), the output signal of the output terminal Q changes with a delay with respect to the input signal of FIG.

However, since there is such a delay time difference, when there is almost no phase difference between the input signals of the clock terminal CK and the clear terminal CL, as shown in FIG. After the rising, the level of the output terminal Q changes to the high level, and the rising of the input signal of the clear terminal CL shown in FIG. 9 (b) causes the output terminal Q to rise as shown in FIG. 9 (c). There is a dead zone where the level of Q does not change. When the video carrier of the RF signal is 8.1 MHz, the delay time difference 3nsec is ± 180
The dead band of ± 2.4% is obtained as the phase comparison circuit of ゜. This is equivalent to ± 4.3% when converted to an angle, and as an empirical value ±
There is a problem that a tracking deviation of up to 0.06 μm cannot be detected.

SUMMARY OF THE INVENTION [Object of the Invention] Accordingly, an object of the present invention is to prevent the occurrence of a dead band of a flip-flop even when there is almost no phase difference between input signals of a clock terminal CK and a clear terminal CL. An object of the present invention is to provide a tracking error signal generating device capable of obtaining a tracking error signal.

[Constitution of the Invention] A tracking error signal generating apparatus according to the present invention is a photodetector for receiving a reflected light beam from an information recording surface obtained by an objective lens for converging an irradiation light beam on an information recording surface of a disk-shaped recording medium. Is divided into two along the tangential direction of the recording track and further divided into two along the direction perpendicular to the track, so that the light receiving surface is arranged so as to be divided into four.
First and second pulse signals in an optical disc player having a pickup composed of a plurality of photoelectric conversion elements by adding and shaping waveforms of output signals of diagonal relations among the four photoelectric conversion elements. And the first and second
A tracking error signal generation device for detecting a phase difference between pulse signals as a tracking error by a phase comparison circuit, wherein the phase comparison circuit supplies a first pulse signal to a clock terminal and a second pulse signal to a clear terminal. A D-type flip-flop is provided, and a second pulse signal is supplied to a clear terminal of the flip-flop via a delay circuit.

[Operation of the Invention] In the tracking error generation device according to the present invention, the delay time from the rising of the input signal of the clock terminal CK to the rising of the output terminal Q, and the falling of the output terminal Q from the rising of the input signal of the clear terminal CL. The delay circuit delays the second pulse signal supplied to the clear terminal CL even in a D-type flip-flop having a delay time difference from the delay time up to. This allows the clock terminal
When there is almost no phase difference between the input signals of the CK and the clear terminal CL, it is possible to prevent a dead zone from being formed and detect a phase difference, so that an appropriate tracking error signal can be obtained.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a phase comparison circuit in a tracking error generation device according to the present invention. In this phase comparison circuit, the same parts as those shown in FIG. 4 are denoted by the same reference numerals, and the input terminal IN ₁ is directly connected to the clock input terminals CK of the D flip-flops 1 and 2 and The flip-flops 3 and 4 are connected to the clear terminal CL via a delay circuit 51. Input terminal IN ₂ is D
It is directly connected to the clock input terminal CK of the type flip-flops 3 and 4 and connected to the clear terminal CL of the D-type flip-flops 1 and 2 via the delay circuit 52. Other configurations are the same as those of the conventional phase comparison circuit shown in FIG.

In such a configuration, the delay time from the rise of the input signal of the clock terminal CK to the rise of the output terminal Q of the D flip-flops 1 to 4 is τ ₁ , and the delay time from the rise of the input signal of the clear terminal CL to the fall of the output terminal Q is Assuming that the delay time is τ ₂ , the delay time τ _{3 of the} delay circuits 51 and 52 is
Is set slightly longer than τ ₁ −τ ₂ (for example, 3 nsec).

If the D flip-flop shown in FIG. 6 is described as the D flip-flop 1, a signal is input to the clear input terminal CL via the delay circuit 51. Therefore, as shown in FIG. 2 (a), the input level of the clock terminal CK is
changes from low level to high level at t _1, when the clear terminal CL and remain low, transistor 18 is turned on, the transistor 22 is turned off. As a result, the transistors 20 and 23 are turned off because no current flows. The transistor 25 is turned off because the potential at the point a is low.

During such operation (i.e., within a period up to the time tau ₁ from time t ₁ has elapsed) from the low-level input level at time t ₂ of the input terminal IN _2, as shown in FIG. 2 (b) to Suppose it has changed to a high level. This level change is delayed by the delay circuit 51. Therefore, the output level of the delay circuit 51 changes from the low level to the high level after a lapse of the delay time τ ₃ from the time point t ₂ as shown in FIG. 2C, and this is input to the clear terminal CL.

Since τ ₃ > τ ₁ −τ ₂ , the potential of the output terminal Q changes from the low level to the high level after the time τ _{1 has} elapsed from the time point t ₁ as shown in FIG. Then, from time t ₂ after the lapse of the delay time tau _3, the transistor 26 is turned on by the high level signal inputted to the clear terminal CL, the time from the time t ₂ as shown in FIG. 2 (d) tau ₂ + τ
After a lapse of _three, the potential of the output terminal Q is inverted from the high level to the low level. Therefore, when there is almost no phase difference between the input signals of the input terminals IN ₁ and IN ₂ , that is, from when the input signal of the input terminal IN ₁ rises to when the level of the output terminal Q changes to a high level. Input terminal
Level of the output terminal Q by the rising of the input signal IN ₂ can be prevented the occurrence of a dead zone does not change. This means that not only the D flip-flop 1 but also the D flip-flops 2 to 4 have delay circuits at the clear terminals.
The same applies because the signal is supplied via 51 or 52. Thus, the D flip-flop 1-4 is also when the phase difference between the input signals of the input terminals IN ₁ and IN ₂ are hardly it is possible to detect the phase difference, it is possible to obtain an appropriate tracking error signal.

As described above, in the tracking error signal generation device according to the present invention, the output signals of the four photoelectric conversion elements of the photodetector that are in a diagonal relationship are added and the waveform is shaped. The obtained first and second pulse signals are D
Is supplied to a phase comparison circuit comprising flip-flops,
The first pulse signal is directly supplied to the clock terminal CK of the D-type flip-flop, and the second pulse signal is supplied to the clear terminal CL of the D-type flip-flop via a delay circuit. Therefore, a D-type flip-flop having a delay time difference between the delay time from the rising of the input signal of the clock terminal CK to the rising of the output terminal Q and the delay time from the rising of the input signal of the clear terminal CL to the falling of the output terminal Q. The second pulse signal supplied to the clear terminal CL is delayed by the delay circuit even in the case of the pulse. This prevents a dead zone from being formed when there is almost no phase difference between the input signals of the clock terminal CK and the clear terminal CL, and the phase difference can be detected, so that an appropriate tracking error signal can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of each unit of the apparatus shown in FIG. 1, FIG. 3 is a block diagram showing a conventional example of a tracking error generating apparatus, FIG.
FIG. 5 is a block diagram showing a conventional phase comparator, FIG. 5 is a waveform diagram showing the operation of the circuit of FIG. 4, and FIG. 6 is a circuit showing a specific configuration of a D-type flip-flop in the circuit of FIG. Figure,
7 to 9 are waveform diagrams showing the operation of the D-type flip-flop. Description of Signs of Main Parts 1-4 D-type flip-flop 5, 8 OR circuit 6, 9 Low-pass filter 7 Subtractor 41 Four-split photodetector 42, 43, 47, 48 … Adder 44,45 …… Limiter 46 …… Phase comparison circuit 51,52 …… Delay circuit

Continuation of the front page (72) Inventor Nobuko Obitsu 4-2610 Hanazono, Tokorozawa-shi, Saitama Prefecture Pioneer Corporation Tokorozawa Plant (56) References JP-A-2-108245 (JP, A) JP-A-2-305018 (JP, A) JP-A-59-152545 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11B 7/09-7/095

Claims (1)

(57) [Claims] 1. A photodetector for receiving a reflected light beam from an information recording surface through an objective lens for converging an irradiation light beam on an information recording surface of a disk-shaped recording medium is divided into two minutes along a tangential direction of a recording track. In the optical disc player provided with a pickup composed of four photoelectric conversion elements arranged so that the light receiving surface is divided into four by dividing the two areas further in the track orthogonal direction into two parts, The output signals of the photoelectric conversion elements having a diagonal relationship are respectively added and the waveforms are shaped to obtain first and second pulse signals, and the phase difference between the first and second pulse signals is determined by a phase comparison circuit. A tracking error signal generating device for detecting a tracking error, wherein the phase comparison circuit supplies the first pulse signal to a clock terminal and outputs the second pulse signal to a clock terminal. It includes a D-type flip-flop which is supplied to the A terminal, tracking error signal generation device to the clear terminal and said second pulse signal is supplied via a delay circuit.