JP2829881B2 - Solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device using, as pixels, an imaging device having an amplification function, in which fixed pattern noise is suppressed.

[Conventional technology]

In general, in a solid-state imaging device using an imaging element having an amplification function as a pixel, the output of the imaging device contains a large amount of fixed pattern noise because the offset and gain of the amplification unit of each pixel are different. For example, in the case of the FET type amplifying unit, the variation is mainly caused by the variation of the amplification operation start voltage _Vth , which corresponds to the variation of the output when the photodiode on the gate side is not irradiated with light. Therefore, this occurs when the light input is small, and when capturing an image with low illuminance, fixed pattern noise is detected, deteriorating the image quality.

On the other hand, the fixed pattern noise caused by the difference in gain of the amplifying unit is a fixed pattern noise generated in proportion to the input of light, and is small in a dark scene and has a low detection limit.
(Reference: “Study on detection limit characteristics of fixed pattern noise in solid-state imaging device”, Proceedings of the National Convention of the Institute of Television Engineers of Japan, 2-10, 1989) Many proposals have been made as follows.

(1) A method has been proposed in which an output when there is no light input is stored in a two-dimensional memory, and the memory output is subtracted from a light accumulation output signal of the image sensor to suppress fixed pattern noise.

(2) Also, as one of the conventional four proposed techniques, there is an example of an amplification type image sensor BASIS (Base Store Image Sensor).
In this technique, in an XY address type two-dimensional imaging device, an analog line memory for one horizontal line (1H) is provided in the device, and immediately after a light accumulation output signal from a 1H pixel is recorded, As in the case of resetting the optical signal charge and reading out the black signal, the difference from the signal previously recorded in the line memory is taken to reduce fixed pattern noise. (Reference: “A Novel Bipolar Imaging Devi
ce with Self-Noise Reduction Capability "IEEE ED V
ol. 36, No. 1, NOBUYOSHI TANAKA January 1989) (3) As one of the conventional technologies, FGA (Floating Ga
te Arrey). In this technique, in an XY address type two-dimensional imaging device, a vertical signal line is divided by a capacitor, an output signal reset every 1H, that is, a black portion is clamped, and then a signal component is sampled. is there. This means that the black signal is equivalently subtracted from the light accumulation output signal, and the fixed pattern noise is suppressed. (Reference: “A NEW DEVICE ARCHITEOTURE SUITAB
LE FOR HIGH-RESOLUTION AND HIGH-PEPFORMANCE "JARO
SLAV HYNECEK IEEE ED Vol.135, No.5, May 1988, pp.646
(652) (4) As another example of the prior art, there is a dot sequential time division differential system. This method is an XY address type 2
In the two-dimensional imaging device, a reset transistor is provided for each pixel, reset is performed in the middle of the readout period of one pixel, and the light accumulation signal output and the black output are continuously read and subtracted to reduce fixed pattern noise. This is a method of suppressing. (Reference: Japanese Patent Application No. 62-273052, “Solid-state imaging device”) [Problems to be Solved by the Invention] As described above, many proposals have been made regarding a method of suppressing fixed pattern noise by an offset component. However, the proposed techniques have the following disadvantages.

First, the method of suppressing the fixed pattern noise by the external memory in the item (1) has a high canceling accuracy, but requires a large circuit scale, and is disadvantageous in terms of power consumption and price.

(2) Suppress fixed pattern noise inside the element
In the example of BASIS, the disadvantage of the technique described in the above item (1) can be solved, but it is difficult to remove the vertical stripe-like fixed pattern noise generated from the 1H memory. This is because there is a variation in the capacity provided for storing the output of each pixel in the 1H memory, and thus, fixed pattern noise in the form of vertical stripes is inevitable. Similar disadvantages mentioned in (3)
There are some that use FGA. Such a problem of the vertical stripe-shaped fixed pattern noise arises from the imperfectness of the noise canceling method itself.

As described above, most of the fixed pattern noise suppression methods using the offset component are based on the principle that the element is reset or the optical input is turned off to form a state without photocharge, and the output in that state is subtracted from the signal component. Is based on In the current technology, the method of resetting the element takes a 1H period due to its structure. Therefore, in order to utilize the above principle, a memory of 1H period is inevitably required. Therefore, since the variation of each memory in each pixel is a 1H memory, it is easily detected as fixed pattern noise in the form of vertical stripes.

The point-sequential time-division differential system that does not require the 1H memory described in the above item (4) has a disadvantage that a reset transistor must be provided for each pixel, and the configuration of the element becomes very complicated. Further, when the element is driven at a high frequency, the readout period of one pixel is shortened, and it is difficult to perform a series of operations of signal readout, reset, and signal readout immediately after reset during one pixel period.

The present invention has been made to solve the above-described problem in the conventional solid-state imaging device that suppresses fixed pattern noise, and can easily suppress fixed pattern noise without providing a reset transistor or 1H memory for each pixel. It is an object of the present invention to provide a solid-state imaging device as described above.

[Means and actions for solving the problem]

In order to solve the above-described problems, the present invention provides a solid-state imaging device in which imaging elements having an amplification function are two-dimensionally or one-dimensionally arranged as pixels, and sequentially performs an operation of sequentially reading a light accumulation signal of each pixel. 1 horizontal selection circuit, a second horizontal selection circuit that performs a reset operation after reading a light accumulation signal by the first horizontal selection circuit of each pixel, and performs an operation of reading a pixel signal immediately after the reset operation. And a means for reducing the fixed pattern noise included in the light accumulation signal of each pixel by subtracting the light accumulation signal from the light accumulation signal and the pixel signal immediately after the reset operation.

In the solid-state imaging device configured as described above, the light accumulation signal output of each pixel is read out by the operation of the first horizontal selection circuit, and then the operation of each pixel is completed by the operation of the second horizontal selection circuit. Is reset and the pixel signal immediately after the reset is read out. Then, the output of the light accumulation signal of the same pixel and the pixel signal immediately after reset are subtracted, and a signal output in which fixed pattern noise is suppressed is output.

This allows a special reset transistor for each pixel,
It is possible to realize a solid-state imaging device that does not require a 1H memory and can easily suppress fixed pattern noise. Further, in the present invention, the readout of the light accumulation signal output, the reset and the readout of the pixel signal immediately after the reset can be performed at different timings. Therefore, the present invention is effective even when the readout period of one pixel is shortened. It can sufficiently cope with high-speed imaging operations such as HDTV.

〔Example〕

Next, examples will be described. FIG. 1 is a schematic circuit configuration diagram showing an embodiment of a solid-state imaging device according to the present invention. In the figure, 1-11, 1-12, ..., 1-31, 1-32, ...
Is a CMD (C) that constitutes pixels arranged in a two-dimensional array.
harge Modulation Device) type phototransistor.
Reference numeral 2 denotes a noise suppression circuit that suppresses fixed pattern noise included in the output signal of the CMD type phototransistor.
First, the imaging operation of the CMD type phototransistor will be described. The imaging operation of the CMD type phototransistor constituting the pixel is divided into three operations: photoelectric conversion and charge accumulation operation, readout operation for outputting a result of photoelectric conversion, and reset operation for discharging accumulated charge. For each operation mode, the potential distribution map under the gate electrode of the CMD type phototransistor and the source
FIG. 2 (A) shows the potential distribution between the drains.
It is shown in (B). At the time of photoelectric conversion and charge accumulation, as shown by the solid line, a negative voltage such that the phototransistor is cut off is applied to the gate electrode, and the charge generated by the photoelectric conversion is accumulated immediately below the gate electrode. At the time of reading, as shown by a broken line, a potential is applied to the gate electrode so that the phototransistor is turned on from cutoff. At this time, a current corresponding to the charge accumulated immediately below the gate electrode flows from the drain to the source, and this current becomes an output signal. At the time of reset for releasing accumulated charges, the potential of the source is set to an appropriate negative potential as indicated by a chain line, and accumulated charges (holes) are ejected to the substrate side by a potential gradient.

The solid-state imaging device 3 is configured by arranging the CMD-type phototransistors that operate as described above in a two-dimensional array. A vertical shift register 4 selects one row of the solid-state imaging device 3. Reference numerals 5 and 5 denote first horizontal shift registers for reading out the light accumulation output signals of the pixels in the selected one row for each pixel. Reference numeral 6 denotes a second horizontal shift register for resetting the selected row after reading out the signal for each pixel and reading out the pixel signal immediately after the reset. 7-1, 7-2, ... are horizontal selection switches driven by the first horizontal shift register 5, and 8-1, 8-2, ..., 9-1, 9-2, ... , A reset switch driven by the second horizontal shift register 6 and a horizontal selection switch for reading after reset.

V ₁ , V ₂ ,... Are drive pulses applied from the vertical shift register 4 to the 1, 2,..., Row selection lines, and are H ₁₁ , H ₁₂ ,.
From the first horizontal shift register 5 to the horizontal selection switch 7
-1,7-2,..., And similarly, H
_21, H _22, ..., the second reset switch 8-1 from the horizontal shift register 6, ... and reset to read horizontal selection switches 9-1 and 9-2, the drive to be applied to ... It is a pulse.

Next, the operation of the solid-state imaging device thus configured will be described.
This will be described with reference to the timing chart of FIG.
By sequentially scanning the vertical shift register 4 and the first horizontal shift register 5, output signals corresponding to the intensity of the entered light sequentially appear on the output signal line 11 from each pixel constituting the image sensor.

Here, a case where the first row of the vertical selection line is applied to the read driving pulse shown in pulse V ₁ of the FIG. 3, for further detail Operation. Drive pulse H ₁₁ from the first horizontal shift register 5, H _12, when .... is output, the horizontal selection switches 7-1 and 7-2, ... is sequentially turned on, leading to the first row of the vertical selection line The pixel output signals of the horizontal pixel columns 1-11, 1-12,... Are sequentially read out to the output signal lines 11. Pixel output signal read out to the output signal line 11 is amplified by the preamplifier 13-1 is an output signal V _1. This output signal V ₁
As shown in FIG. 3, in addition to the output signal components S ₁₁ , S ₁₂ ,... Corresponding to the optical signal charges stored in each pixel, Non-uniform output offset components N ₁₁ , N ₁₂ ,... Are respectively included.

Meanwhile, after the light accumulating the output signals of the first column of pixels 1-11 is output, the same as the timing of the drive pulses H ₁₂ to start reading of the second row of light accumulation output signals of the pixels 1-12 timing, by the drive pulses H ₂₁ from the second horizontal shift register 6, a first column reset switch 8
-1 is turned on, and a reset voltage _VRR is applied to the vertical signal line of the first column so as to have a negative potential with respect to the gate electrode at the time of reading. Reset is performed for -11.

Then the same timing as the third row of horizontal selection drive pulse H _13, second by drive pulses H ₂₂ in the second column is applied in the horizontal shift register 6, the first column reset after read horizontal selection switch 9-1 There turned on, the pixel signals of the pixels 1-11 of the first row and first column just above reset operation is completed is read out to the output line 12, is amplified by a preamplifier 13-2, an output signal V _2. The output signal V ₂ is substantially equal to the output signal of the dark pixel (for when normally dark output includes output components by dark charges differ by the output component),
Then, only the output offset components N ₁₁ and N ₁₂ that directly embody the output non-uniformity of each pixel are included.

Then the fixed pattern noise suppressing circuit 2 delays the output signal V ₁ of the phase delay elements 2a, to match the corresponding same pixel reset after the output signal V ₂ of the phase, to a subtraction in the differential circuit 2b , The non-uniform output offset components N ₁₁ , N ₁₂ ,... Resulting from the non-uniform characteristics of each pixel.
, And a corrected output signal OUT with good S / N of only the output signal components S ₁₁ , S ₁₂ ,... Can be obtained.

In this embodiment, fixed as a pattern noise suppressing circuit, although the delay difference circuit to take a difference between the pixel signal V ₂ immediately after reset After delaying the light accumulation output signal V ₁ as described above, In addition, for example, a double sample and hold circuit using two sample and hold circuits can be used.

Further, in this embodiment, the CMD type phototransistor is used as a pixel, but the present invention is applicable to other amplifying type image pickup devices such as SIT type, AMI type, BASIS type, and FGA type. Can be applied to a solid-state imaging device using the same, and although the method of realizing the reset is different, essentially the same effect can be obtained.

According to the present invention, the following effects can be additionally obtained. That is, in the conventional fixed pattern noise suppression method in the element, the light signal charge integration time from the reset operation to the readout differs between the horizontal pixels by about one horizontal scanning period. In particular, the integration time is shortened by the electronic shutter operation. In this case, the difference in the integration time appears as horizontal shading, which is a problem in image quality.
According to the present invention, since the reset is performed for each pixel, a difference in integration time does not occur, and the above problem is solved.

Furthermore, according to the present invention, it is possible to reduce the number of reset level generation circuits required in the conventional vertical scanning circuit,
It is possible to reduce the scanning circuit area or the chip area, which is advantageous in terms of yield and cost.

〔The invention's effect〕

As described above based on the embodiments, according to the present invention, the reset transistor and the 1H memory for each pixel are not required, and the area of the scanning circuit or the chip is reduced, thereby reducing the cost. A solid-state imaging device that can easily suppress fixed pattern noise can be provided. In addition, reading of the light accumulation signal output, resetting, and reading of the pixel signal immediately after the reset can be performed at different timings.
A solid-state imaging device that suppresses fixed pattern noise and that can sufficiently cope with a high-speed imaging operation in which a pixel readout period is short is obtained.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram showing an embodiment of a solid-state imaging device according to the present invention, and FIGS. 2A and 2B show potential distribution inside a CMD type phototransistor in each operation mode. FIG. 3 and FIG. 3 are timing charts for explaining the operation of the solid-state imaging device shown in FIG. In the figure, 1-11, 1-12,... Are CMD type phototransistors, 2 is a fixed pattern noise suppression circuit, 3 is an image sensor, 4 is a vertical shift register, 5 is a first horizontal shift register, and 6 is a 2 horizontal shift registers, 7-1, 7-2, ...
.. Are reset switches, 9-1, 9-2,... Are reset-read horizontal select switches, 11, 12 are output lines, 13-1, 13 -2 indicates a preamplifier.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yoshihiro Fujita 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the Japan Broadcasting Corporation Research Institute (72) Inventor Fumio Okano 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Masao Fujiwara 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (56) References JP-A-49-132922 (JP, A) JP-A-61-128683 (JP, A) JP-A-2-79682 (JP, A) JP-A-55-15822 (JP, U) JP-A-56-99972 (JP, U) (58) Fields investigated (Int) .Cl. ⁶ , DB name) H04N 5/30-5/335

Claims (3)

(57) [Claims] An image pickup device having an amplification function is defined as a pixel.
In a solid-state imaging device having a pixel array arranged one-dimensionally or one-dimensionally, a first horizontal selection circuit that performs an operation of sequentially reading a light accumulation signal of each pixel and a first horizontal selection circuit of each pixel A second horizontal selection circuit that performs a reset operation after reading the light accumulation signal and reads the pixel signal immediately after the reset operation, and subtracts the light accumulation signal of the same pixel from the pixel signal immediately after the reset operation to perform Means for reducing fixed pattern noise included in the light accumulation signal of the pixel. 2. An image pickup device constituting a pixel, comprising a phototransistor, wherein the reset operation by the second horizontal selection circuit is performed by setting a source potential connected to a signal output line of the phototransistor to a negative potential compared to a gate potential. 2. The solid-state imaging device according to claim 1, wherein the operation is performed by discharging the gate accumulated photocharge. 3. The method according to claim 2, wherein the first and second horizontal selection circuits are formed in the same element as the pixel array, and the fixed pattern noise reducing means is configured in the same element or as an external circuit. The solid-state imaging device according to claim 1.