JP2823029B2 - Multi-chip module - Google Patents
Multi-chip moduleInfo
- Publication number
- JP2823029B2 JP2823029B2 JP4074085A JP7408592A JP2823029B2 JP 2823029 B2 JP2823029 B2 JP 2823029B2 JP 4074085 A JP4074085 A JP 4074085A JP 7408592 A JP7408592 A JP 7408592A JP 2823029 B2 JP2823029 B2 JP 2823029B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor chip
- insulating substrate
- semiconductor
- chip module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
複数の半導体チップが、収納されるマルチチップモジュ
ールの構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a multi-chip module in which a plurality of semiconductor chips are stored.
【０００２】[0002]
【従来の技術】従来のマルチチップモジュールは第５図
の断面図に示すように、複数の半導体チップ４が電気配
線パターン（図示せず）を有する電気絶縁基板の同一面
上に収納されており、前記電気絶縁基板１と前記半導体
チップ４とは、金属細線１０によって電気的に接続さ
れ、前記電気絶縁基板１の電気配線パターンは、外部リ
ード６によって電気的に接続されている。2. Description of the Related Art In a conventional multi-chip module, as shown in a sectional view of FIG. 5, a plurality of semiconductor chips 4 are housed on the same surface of an electrically insulating substrate having an electric wiring pattern (not shown). The electrically insulating substrate 1 and the semiconductor chip 4 are electrically connected by thin metal wires 10, and the electrical wiring patterns of the electrically insulating substrate 1 are electrically connected by external leads 6.
【０００３】この従来構造で例えば、ＣＰＵ（Ｃｅｎｔ
ｒａｌ Ｐｒｏｃｅｓｓｉｎｇ Ｕｎｉｔ）１個, ＦＰ
Ｕ（Ｆｌｏｔｉｎｇ Ｐｒｏｃｅｓｓｉｎｇ Ｕｎｉ
ｔ）１個, ＢＩＵ（Ｂｕｔｈ Ｉｎｔｅｒｆａｃｅ Ｕ
ｎｉｔ）１個, キャッシュメモリ６個の合計９個の半導
体チップで構成されるマルチチップモジュールであれ
ば、電気絶縁基板の大きさは、約８５ｍｍ角となる。With this conventional structure, for example, a CPU (Cent
ral Processing Unit) 1 pc, FP
U (Floating Processing Uni)
t) 1 piece, BIU (Bus Interface U)
nit) In the case of a multi-chip module composed of a total of nine semiconductor chips of one and six cache memories, the size of the electrically insulating substrate is about 85 mm square.
【０００４】[0004]
【発明が解決しようとする課題】ところで、この従来の
マルチチップモジュールでは、半導体チップ４が電気絶
縁基板１の同一面のみに収納されているため、半導体チ
ップの収納数が増えると電気絶縁基板の大きさも大きく
ならざるを得ない。従って電気配線の線路長が長くな
る。By the way, in this conventional multi-chip module, the semiconductor chip 4 is housed only on the same surface of the electrically insulating substrate 1, so that when the number of housed semiconductor chips increases, the size of the electrically insulating substrate increases. The size must be large. Therefore, the line length of the electric wiring becomes longer.
【０００５】このように、電気配線の線路長が長くなる
と、配線の持つキャパシタンスが大きくなり、信号の伝
播遅延時間が大きくなる。このため、マルチチップモジ
ュールを高速動作させようとした場合、１つのクロック
の時間内に信号が戻らなくなり、マルチチップモジュー
ルが高速動作しなくなるといった問題があった。[0005] As described above, when the line length of the electric wiring is increased, the capacitance of the wiring is increased, and the signal propagation delay time is increased. For this reason, when trying to operate the multi-chip module at high speed, there is a problem that the signal does not return within one clock time, and the multi-chip module does not operate at high speed.
【０００６】この問題は、非常に大きな問題であり、高
速動作すればするほど信号の処理スピードが上がるのに
対し、高速動作ができないという問題があった。This problem is a very serious problem. The higher the operation speed, the higher the signal processing speed. However, the higher speed operation cannot be performed.
【０００７】この発明はこのような従来技術の課題に鑑
みて提案されたもので、フリップチップ接続等のマルチ
チップモジュールにおいて、実装密度の向上および電気
配線の線路長を短くし、上記従来技術の欠点を除去する
ことを目的とする。The present invention has been proposed in view of such problems of the prior art. In a multi-chip module such as flip-chip connection, the mounting density has been improved and the line length of electric wiring has been reduced. The aim is to eliminate disadvantages.
【０００８】[0008]
【課題を解決するための手段】本発明によれば、複数の
半導体チップを収納し、前記半導体チップがバンプによ
り所定の電気配線パターンを有する電気絶縁基板に電気
的に接続されてなるマルチチップモジュールにおいて、
前記電気絶縁基板には水平方向に複数の凹部が並設さ
れ、これらの凹部に前記半導体チップが収容されてお
り、前記複数の凹部には多段式のものがあり、該多段式
凹部には前記半導体チップが上下方向に相互に離間して
収容されていることを特徴とするマルチチップモジュー
ルが得られる。According to the present invention, there is provided a multi-chip module in which a plurality of semiconductor chips are housed, and the semiconductor chips are electrically connected by bumps to an electrically insulating substrate having a predetermined electric wiring pattern. At
The electrical insulating substrate has a plurality of concave portions arranged in a horizontal direction.
The semiconductor chip is housed in these recesses.
The plurality of recesses include a multi-stage type, and the multi-stage type
The semiconductor chips are vertically separated from each other in the recess.
A multi-chip module characterized by being housed is obtained.
【０００９】[0009]
【実施例】まず、参考例のマルチチップモジュールにつ
いて説明する。図１に示すように、半導体チップ４は、
電気配線パターン２を有する電気絶縁基板１に設けられ
た多段の凹部にそれぞれ離間並行に上下方向多段式に収
容されている。そして半導体チップ４を載置する段部に
はバンプ３が形成されている。各半導体チップ４はこの
バンプ３上に載置されており、電気配線パターン２に
て、任意の半導体チップ同士、あるいは、外部リード６
と接続されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a multichip module of a reference example will be described. As shown in FIG. 1, the semiconductor chip 4
The multi-stage concave portions provided on the electric insulating substrate 1 having the electric wiring patterns 2 are housed in a vertically multi-stage manner in parallel with each other. The bump 3 is formed on a step portion on which the semiconductor chip 4 is mounted. Each semiconductor chip 4 is mounted on the bump 3, and any of the semiconductor chips or the external leads 6 are connected by the electric wiring pattern 2.
Is connected to
【００１０】この場合、半導体チップ４として、チップ
コンデンサ等の搭載も可能である。なお、図中５はキャ
ップ、７は封止材である。In this case, a chip capacitor or the like can be mounted as the semiconductor chip 4. In the drawings, reference numeral 5 denotes a cap, and 7 denotes a sealing material.
【００１１】次に、本発明の第１実施例のマルチチップ
モジュールについて説明する。第１実施例のマルチチッ
プモジュールは図２に示すように、水平方向にも半導体
チップ４を並列させるように複数の凹部をもつ半導体チ
ップ載置部を形成しておくものである。なお、このよう
な縦方向のみではなく横方向への半導体チップ４の配置
や数は図示のものに限定されるものでないことはいうま
でもない。Next, a multi-chip module according to a first embodiment of the present invention will be described. As shown in FIG. 2, the multi-chip module according to the first embodiment has a semiconductor chip mounting portion having a plurality of recesses formed so that the semiconductor chips 4 are arranged in a horizontal direction. It goes without saying that the arrangement and number of the semiconductor chips 4 in the horizontal direction as well as in the vertical direction are not limited to those shown in the drawings.
【００１２】参考例の半導体チップ４の配置によれば、
上方に行くにしたがって半導体チップの大きさが大きく
ならざるを得ず、同じ大きさの半導体チップ４を同一基
板に配置することができなかったが、この第１実施例の
配置にすることにより、搭載される半導体チップ４の大
きさ多種多様であっても対応させることが可能となる。According to the arrangement of the semiconductor chip 4 of the reference example ,
Although the size of the semiconductor chip had to be increased as going upward, the semiconductor chips 4 of the same size could not be arranged on the same substrate, but by adopting the arrangement of the first embodiment , Even if the size of the semiconductor chip 4 to be mounted is various, it is possible to correspond.
【００１３】次に、本発明のマルチチップモジュールに
放熱手段となるヒートシンクを取り付ける場合について
説明する。図３は参考例のマルチチップモジュールにヒ
ートシンク９を取り付けた場合の断面図である。ヒート
シンク９を発熱性の高い半導体チップを最上部に接続
し、前記半導体チップとヒートシンク９を高熱伝導性接
着材８を介して接着したものである。Next, a case where a heat sink as a heat radiating means is attached to the multichip module of the present invention will be described. FIG. 3 is a cross-sectional view when the heat sink 9 is attached to the multichip module of the reference example . A heat sink 9 is connected to a semiconductor chip having high heat generation at the uppermost portion, and the semiconductor chip and the heat sink 9 are bonded via a high thermal conductive adhesive 8.
【００１４】図４は、本発明の第１実施例のマルチチッ
プモジュールにヒートシンク９を取り付けた第２実施例
の断面図である。発熱性の高い半導体チップを複数収納
する場合、第２実施例のように電気絶縁基板の凹部の最
上部に前記複数の半導体チップを接続することで、複数
の半導体チップにヒートシンクを接着可能となる。FIG. 4 is a sectional view of a second embodiment in which a heat sink 9 is attached to the multi-chip module according to the first embodiment of the present invention. In the case where a plurality of semiconductor chips having high heat generation are stored, a heat sink can be bonded to the plurality of semiconductor chips by connecting the plurality of semiconductor chips to the uppermost portion of the concave portion of the electrically insulating substrate as in the second embodiment. .
【００１５】なお、上記電気絶縁基板１の材料として
は、アルミナ基板及びガラスエポキシ基板等が従来より
用いられているが、フリップチップ実装の信頼性から考
えると半導体チップと熱膨張率の整合のとれたイビデン
（株）より市販されているセラコム基板という商品名の
基板を用いるのが適切である。As a material of the electric insulating substrate 1, an alumina substrate, a glass epoxy substrate, or the like has been conventionally used. However, considering the reliability of flip-chip mounting, the thermal expansion coefficient of the semiconductor chip can be matched with that of the semiconductor chip. It is appropriate to use a substrate having a trade name of Ceracom substrate commercially available from Ibiden Co., Ltd.
【００１６】セラコム基板においてのフリップチップ実
装評価実績として、１２５℃〜−６５℃の温度サイクル
試験にて１０００サイクルで断線の発生なしという結果
が得られている。As a result of flip chip mounting evaluation on a Ceracom board, a result that no disconnection occurs in 1000 cycles in a temperature cycle test at 125 ° C. to −65 ° C. is obtained.
【００１７】上記本発明の各実施例によれば、従来技術
で電気絶縁基板の大きさが約８５ｍｍ角必要であるもの
を、約５０ｍｍ角程度まで小さくすることが可能であ
る。According to each of the embodiments of the present invention, it is possible to reduce the size of the conventional electrically insulating substrate, which requires a size of about 85 mm square, to about 50 mm square.
【００１８】[0018]
【発明の効果】以上説明したように本発明は、電気絶縁
基板に設けられた多段の凹部に半導体チップを離間並行
して縦方向に収容するとともに、その凹部と水平方向に
並んだ他の凹部にも半導体チップを収容することで、搭
載される半導体チップの大きさや数による制限を受ける
ことなく、電気絶縁基板を小さくすることができ、実装
密度の向上および電気配線の線路長を短くして信号伝播
遅延時間を短くでき、マルチチップモジュールの高速動
作を可能ならしめるという効果がある。The present invention described above, according to the present invention is configured to accommodate the longitudinal direction of the semiconductor chip to the multi-stage recess provided in electrical insulating substrate spaced parallel, in the recess and the horizontal direction
By accommodating the semiconductor chips also in the other recesses arranged side by side, the size of the electrically insulating substrate can be reduced without being limited by the size and number of the semiconductor chips to be mounted, thereby improving the mounting density and improving the wiring of the electric wiring. By shortening the length, the signal propagation delay time can be shortened, and the multichip module can be operated at high speed.
【図面の簡単な説明】[Brief description of the drawings]
【図１】参考例を示す断面図である。FIG. 1 is a sectional view showing a reference example .
【図２】本発明の第１実施例を示す断面図である。FIG. 2 is a sectional view showing a first embodiment of the present invention.
【図３】参考例にヒートシンクを取り付けた例の断面図
である。3 is a cross-sectional view of the example in which the heat sink to the reference example.
【図４】本発明の第１実施例にヒートシンクを取り付け
た第２実施例の断面図である。FIG. 4 is a sectional view of a second embodiment in which a heat sink is attached to the first embodiment of the present invention.
【図５】従来のヒートシンク付マルチチップモジュール
を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional multi-chip module with a heat sink.
１ 電気絶縁基板 ２ 電気配線パターン ３ バンプ ４ 半導体チップ ５ キャップ ６ 外部リード ７ 封止材 ８ 高熱伝導性接着材 ９ ヒートシンク １０ 金属細線 DESCRIPTION OF SYMBOLS 1 Electrically insulating substrate 2 Electrical wiring pattern 3 Bump 4 Semiconductor chip 5 Cap 6 External lead 7 Sealing material 8 High thermal conductive adhesive material 9 Heat sink 10 Fine metal wire
Claims (2)
体チップがバンプにより所定の電気配線パターンを有す
る電気絶縁基板に電気的に接続されてなるマルチチップ
モジュールにおいて、前記電気絶縁基板には水平方向に
複数の凹部が並設され、これらの凹部に前記半導体チッ
プが収容されており、前記複数の凹部には多段式のもの
があり、該多段式凹部には前記半導体チップが上下方向
に相互に離間して収容されていることを特徴とするマル
チチップモジュール。1. A housing a plurality of semiconductor chips in the semiconductor chip multichip module comprising electrically connected to the electrically insulating substrate having a predetermined electrical interconnect pattern by the bumps, the said electrically insulating substrate horizontally To
A plurality of recesses are provided in parallel, and the semiconductor chip is inserted into these recesses.
And a plurality of recesses are accommodated in the plurality of recesses.
And the semiconductor chip is vertically inserted into the multistage recess.
A multi-chip module, wherein the multi-chip module is housed separately from each other .
熱手段を備えていることを特徴とする請求項１に記載の
マルチチップモジュール。2. A semiconductor device thermally connected to the semiconductor chip.
The multi-chip module according to claim 1, further comprising a heating unit .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4074085A JP2823029B2 (en) | 1992-03-30 | 1992-03-30 | Multi-chip module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4074085A JP2823029B2 (en) | 1992-03-30 | 1992-03-30 | Multi-chip module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05275611A JPH05275611A (en) | 1993-10-22 |
| JP2823029B2 true JP2823029B2 (en) | 1998-11-11 |
Family
ID=13536985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4074085A Expired - Fee Related JP2823029B2 (en) | 1992-03-30 | 1992-03-30 | Multi-chip module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2823029B2 (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69626747T2 (en) | 1995-11-16 | 2003-09-04 | Matsushita Electric Ind Co Ltd | Printed circuit board and its arrangement |
| US5728972A (en) * | 1996-04-22 | 1998-03-17 | United Microelectronics Corporation | Multiple chip module for packaging integrated circuits |
| DE19635582C1 (en) * | 1996-09-02 | 1998-02-19 | Siemens Ag | Power semiconductor component for bridge circuits with high or low side switches |
| JP3314139B2 (en) * | 1996-09-27 | 2002-08-12 | 京セラ株式会社 | Semiconductor device |
| US6890798B2 (en) | 1999-06-08 | 2005-05-10 | Intel Corporation | Stacked chip packaging |
| JP2001156251A (en) | 1999-11-25 | 2001-06-08 | Mitsubishi Electric Corp | Semiconductor device |
| KR100368607B1 (en) * | 2000-04-17 | 2003-01-24 | 주식회사 케이이씨 | semiconductor package |
| JP2002176137A (en) | 2000-09-28 | 2002-06-21 | Toshiba Corp | Laminated semiconductor device |
| US7098070B2 (en) * | 2004-11-16 | 2006-08-29 | International Business Machines Corporation | Device and method for fabricating double-sided SOI wafer scale package with through via connections |
| JP5145732B2 (en) * | 2007-02-28 | 2013-02-20 | パナソニック株式会社 | Semiconductor module and card type information device |
| JP4947388B2 (en) * | 2009-03-31 | 2012-06-06 | Ｔｄｋ株式会社 | Electronic component built-in module |
| JP2014209091A (en) | 2013-03-25 | 2014-11-06 | ローム株式会社 | Semiconductor device |
-
1992
- 1992-03-30 JP JP4074085A patent/JP2823029B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05275611A (en) | 1993-10-22 |
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