JP2820889B2 - controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a controller used for controlling a plant such as a steel plant.

[0002]

2. Description of the Related Art FIG. 13 is a block diagram showing a controller described in, for example, an instruction manual for a steel plant controller MELPLAC-550. In FIG. 13, 1A is a central processing control unit (hereinafter, referred to as CPU), 2 is a program counter for managing the order of instructions in the CPU 1, and 3 is a bus (hereinafter, referred to as a bus) for reading a program written in the program memory 4. , C-BUS), 4 is a program memory in which a program for plant control is written,
5 is a bus for transferring the execution result of the instruction (hereinafter referred to as P-BUS).
, 6 is an input signal group necessary for controlling the plant,
7 is an output signal group for outputting the operation result of the CPU 1;
A data memory 9 for storing an intermediate result of the operation of the PU 1 is a man-machine device called a programming panel for editing, writing, correcting and monitoring a program.

Next, the operation will be described. The CPU 1 reads an instruction at a program memory address managed by the program counter 2 from the program memory 4 via the C-BUS 3 and executes it. In general, one instruction of a program written in the memory 4 has an instruction part K as shown in FIG.
1 and operand part (or control target address or source)
K2. For example, the load instruction "; IW
10 ", the CPU 1 stores the IW10 on the P-BUS5.
Of the input signal group 6 corresponding to the IW 10
Returns the data to the P-BUS 5, and the CPU 1 reads the data returned from the input signal group 6 to the P-BUS 5. If the store instruction is “→ OW100”, the CP
U1 represents the data of the operation result and the address of OW100 as P-
The data is transmitted on the BUS 5, and the output signal group 7 corresponding to the OW 100 reads the data and outputs the data to the control target device of the plant. The above is the basic operation of the controller.

Next, consider a case where various kinds of control data are monitored and adjusted during the control by the controller. For example, when monitoring the MW 25 of the data memory 8 as a monitor source, it is possible to collect digital data or trend data using the monitor function of the man-machine device 9, but in general, an analog chart output using a pen oscilloscope is used. Is used as a very effective method. To achieve this, as shown in FIG. 14, the controller creates a monitor program P2 in addition to the application program P1 and performs serial processing.

[0005]

As described above, the conventional controller requires the CPU 1 to serially process the control program P1 and the monitor program P2 irrelevant to control for monitoring as described above. There is an inherent problem that the cycle of executing the control program as the execution time of the CPU 1 becomes longer, and the control performance decreases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to significantly reduce the execution time of a CPU by performing the original control and other processes such as monitoring and maintenance in parallel. This is to achieve a significant reduction in control performance and to achieve a dramatic improvement in control performance.

[0007]

According to a first aspect of the present invention, there is provided a controller which doubles the amount of information of one instruction by two times, and a main CPU in charge of original control and a controller other than original control. And a sub CPU for realizing the above function, and only the main CPU manages the instruction execution order of the program.

According to a second aspect of the present invention, there is provided a controller according to the second aspect, wherein a man-machine device for editing, writing, modifying, and monitoring a program is connected to the sub CPU of the first aspect. .

According to a third aspect of the present invention, in the controller according to the third aspect, the first half of the program memory of the first aspect is a control memory, and the second half of the program memory is a control memory similar to the first half. Things.

According to a fourth aspect of the present invention, there is provided a controller according to the first aspect, wherein the first half of the program memory of the first aspect is a control memory, and the second half of the program memory is a measurement memory.

According to a fifth aspect of the present invention, there is provided a controller, wherein the first half of the program memory of the first invention is used as a control memory, and the second half of the program memory is forcibly instructed when an input signal is read. It is a memory.

A controller according to a sixth aspect of the present invention is a controller in which a data memory is connected to the sub CPU of the first aspect of the invention, and input signal time axis change data is input to the data memory.

According to a seventh aspect of the present invention, in the controller according to the seventh aspect, the sub-CPU of the first aspect further has an address management function of the program memory, and the same information is provided in the first half and the second half of the program memory. Is inserted.

According to an eighth aspect of the present invention, in the controller according to the eighth aspect, the sub CPU of the first aspect is provided with a main CPU.
A tracing means is provided for tracing the address management data of the program memory flowing from the U to the program memory side and causing a pause in the data memory connected to the sub CPU when the main CPU is abnormal.

According to a ninth aspect of the present invention, the controller according to the ninth aspect uses the first half and the second half of the program memory of the first invention as a control memory, and uses the second half as a main CP.
When the program of U is wrong, change it and change the main CP
U and the sub CPU are configured to operate in parallel.

A controller according to a tenth aspect of the present invention is configured such that an instruction corresponding to an output at the time of simulation is written in the latter half of the program memory of the first aspect.

[0017]

In the controller according to the first aspect of the present invention, when the main CPU reads an instruction, the sub CPU simultaneously reads and executes the accompanying information.

According to a second aspect of the present invention, the controller comprises a sub CPU
Bears the request from the man-machine device.

A controller according to a third aspect of the present invention comprises a main CP
Multi-control by U and the sub CPU is performed.

A controller according to a fourth aspect of the present invention easily measures an execution time measurement program without imposing a burden on a main CPU.

A controller according to a fifth aspect of the present invention controls the main CPU without stopping even when it is necessary to delete an instruction.

A controller according to a sixth aspect of the present invention executes a high-level simulation when debugging a program.

A controller according to a seventh aspect of the present invention comprises a main CP
The sub CPU backs up when U is abnormal.

According to an eighth aspect of the present invention, the controller comprises a main CP
The address management data of the program memory flowing from the U to the program memory side is paused in the data memory of the CPU, thereby enabling troubleshooting.

According to a ninth aspect of the present invention, the controller comprises a main CP
The parallel operation of the partially changed sub CPU when the program of U is not correct confirms the data, and if there is no abnormality, the processing of the main CPU is replaced with the processing of the sub CPU.

The controller according to the tenth aspect of the present invention omits the test program from the first half of the program memory and realizes the simulation without affecting the operating conditions of the main CPU.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to FIGS.
In the following description, the same parts as those in the conventional example are denoted by the same reference numerals. Embodiment 1 (corresponding to claims 1 and 2). FIG. 1 is a configuration diagram illustrating a controller as a first embodiment, and FIG. 2 is a first embodiment.
It is a flowchart of FIG. In FIG. 1, reference numeral 4A denotes a program memory, which has an information amount of 2 for one instruction.
The first half (the left half of the program memory 4 in FIG. 1) 4A-F has a program counter 2
Is connected via C-BUS3,
A sub CPU 10 having no program counter is connected to the latter half (the right half of the program memory 4 in FIG. 1) 4A-R of the program memory 4 by a C-BUS 11. A man-machine device 9 is connected to the sub CPU 10 by a cable 12 and a data memory 13 is connected by a local bus (hereinafter, referred to as L-BUS) 14.
PU1 connects P-BUS5 which connects data memory 8 and input signal group 6 and output signal group 7 to main CPU1 and P-BUS5 to P-BUS5.
US15, and the sub CPU 10 is connected to the main CPU 1
Is to execute a maintenance instruction in addition to the control instruction to be executed.

Next, the operation of the first embodiment will be described.
The basic operation of the main CPU 1 is completely the same as that of the above-described conventional example, and therefore will not be described. Hereinafter, a case where the monitor program is executed will be described with reference to FIG. As shown in FIG. 2, application programs 4A-F are provided in the first half of the program memory 4.
1 is written, and the monitor program 4A-R1 is written in the second half of the program memory 4. The main CPU 1 reads “→ MW 25” 16 from the program memory 4 and simultaneously sends “MONnGA” to the sub CPU 10.
IN (monitor instruction; output nth gain) instruction 17 is read. Therefore, when the main CPU 1 outputs the data of the accumulator to the MW 25 of the data memory 8 via the P-BUS 5, the sub CPU 10
-BUS5 is intercepted via P-BUS15, the data is gained and output to the n-th output.

In short, according to the first embodiment, the main CPU 1 executes the application program 4A-F1 written in the first half 4A-F of the program memory 4, and at the same time, the sub CPU 10 executes the second half 4A-F of the program memory 4. Monitor program 4A written in R
-R1 in parallel, and as a result, the main CPU 1
Perform the original control, and the sub CPU 10 performs monitoring, so that the execution time of the main CPU 1 can be greatly reduced.
This corresponds to claim 1.

In addition, in the first embodiment, as shown in FIG.
Since the connection is made by the sub CPU 10, the request of the man-machine device 9 is also borne by the sub CPU 10, so that the burden on the main CPU 1 is reduced and the control performance by the main CPU 1 can be remarkably improved. This corresponds to claim 2.

Embodiment 2 (corresponding to claim 3). In the second embodiment, as shown in FIG.
Since the feature of the present embodiment is that the plant is multi-controlled by the reference numeral 10, the components of the controller according to the third embodiment will be described using the reference numerals in FIG.

FIG. 3 is a diagram showing a program memory used for a controller according to the second embodiment, and FIG. 4 is a diagram showing a comparative example of the second embodiment. As shown in FIG. 3, the second embodiment is different from the latter half 4A-R of the program memory 4A.
By using the structure of 2 as the control memory with the same structure as the first half 4A-F2, the main CPU 1 and the sub CPU 10 can perform multi-control of the plant. Therefore, for example, in the comparative example shown in FIG. 4, processing A-processing B-processing C-processing D-processing E-processing F is repeated, whereas in the second embodiment, as shown in FIG.
PU1 can execute the processing A-processing B-processing D-processing F, the sub CPU 10 can execute the processing C-processing E, and the main CP
The execution time of U1 can be greatly reduced, and improvement in control performance can be expected.

Embodiment 3 (corresponding to claim 4). As shown in FIG. 5, the third embodiment is characterized in that the execution time measurement program is easily measured without imposing a burden on the main CPU. This will be described using.

FIG. 5 is a diagram showing a program memory used for a controller as a third embodiment, and FIG. 6 is a diagram showing a comparative example of the third embodiment. As shown in FIG. 5, the third embodiment uses the first half 4A-F3 of the program memory 4A as a control memory, uses the second half 4A-R3 of the program memory 4A as a measurement memory, and uses this second half 4A-F3.
The sub-CP is written in R3 by writing a TS instruction 18 indicating the start of time measurement and a TE instruction 19 indicating the end of time measurement to the start position and end position of the control program to be measured.
U10 measures the execution time of the control, and the main CPU 1 can concentrate on the control only. For example, when measuring the execution times of the processes A and B, in the comparative example shown in FIG. 6, the measurement start logic 20-process A-process B-measurement end logic 2
In the third embodiment, the main CPU 1 executes processing A-processing B-processing C, and the sub CPU 10 measures the execution time of processing A and B, as shown in FIG. Thus, the execution time of the main CPU 1 can be significantly reduced, and improvement in control performance can be expected.

Embodiment 4 (corresponding to claim 5). In the fourth embodiment, as shown in FIG. 7, when the input signal group is read, when it is forcibly turned ON or OFF or when it is data, it is desired to set a numerical value. For example, when it is desired to kill the machine interlock during adjustment, Even when it is necessary to delete the instruction, the control is performed without stopping the main CPU 1, that is, without stopping the production line of the plant. The description will be made using the reference numerals.

FIG. 7 is a diagram showing a program memory used for the controller according to the fourth embodiment. As shown in FIG. 7, the fourth embodiment has a program memory 4
The first half 4A-F4 of the program memory 4A is used as a control memory, the second half 4A-R4 of the program memory 4A is used as a compulsory instruction memory when reading the input signal group 6, and the first half 4A-F4 is used.
By simply writing the KI instruction 23 indicating ON as a compulsory instruction for the process 22 in -F4, a significant reduction in the adjustment time can be expected.

Embodiment 5 (corresponding to claim 6). FIG. 8 is a configuration diagram illustrating a controller as a fifth embodiment. As shown in FIG. 8, in the fifth embodiment, the input signal time axis change data 24 is input to the data memory 13 of the sub CPU 10 and a simulation using the input signal time axis change data 24 at the time of program debugging is performed. It can be executed, and cost reduction accompanying quality improvement at the time of shipment can be expected.

Embodiment 6 (corresponding to claim 7). FIG. 9 is a configuration diagram showing a controller as a sixth embodiment. As shown in FIG. 9, the sixth embodiment is different from the main CPU 1 in FIG.
Similarly, the sub CPU 10A has a program counter 25
To connect C-BUS3 and C-BUS11
-BUS 26 is provided, and the switch 2 is connected to the C-BUS 26.
8 is provided, and a switch 29 is connected from the connection point of the C-BUS 26 to the C-BUS 11 located on the program memory 4A side.
And the main CP is connected from the connection point of P-BUS15.
A switch 27 is provided on the P-BUS5 located on the U1 side,
During normal operation when the main CPU 1 operates normally, the switch 28
And the switches 27 and 29 are closed, and the switch 28 and the switches 27 and 29 are opened when the main CPU 1 is abnormal.
By forming a bus path composed of S3, 26 and P-BUS 15, a backup system with a sub CPU 10A is configured in place of the main CPU 1 in which an abnormality has occurred. That is, the same information is inserted into the first half 4A-F and the second half 4A-R of the program memory 4A, and the sub CP is
Since the U10A is backed up, a highly reliable duplex system can be provided, which can contribute to an improvement in the reliability of the controller.

Embodiment 7 (corresponding to claim 8). FIG. 10 is a configuration diagram illustrating a controller according to a seventh embodiment. FIG.
As shown in FIG. 7, in the seventh embodiment, a tracing means 30 is provided in the sub CPU 10B, and the tracing means 30 traces the program counter value flowing from the program counter 2 of the main CPU 1 to the C-BUS 3, and traces the trace to the main CPU 1. By causing the data memory 13 of the sub CPU 10B to pause when the CPU 1 is abnormal, it is possible to troubleshoot and greatly contribute to shortening the failure recovery time.

Embodiment 8 (corresponding to claim 9). The eighth embodiment is characterized in that the latter half of the program memory is used as a control memory as shown in FIG. 11, and the main CPU and the sub CPU are operated in parallel when the main CPU program is not correct. Therefore, the components of the controller according to the eighth embodiment will be described using the reference numerals in FIG.

FIG. 11 is a diagram showing a program memory used for the controller according to the eighth embodiment. As shown in FIG. 11, in the eighth embodiment, the first half 4A-F5 of the program memory 4A is processed 31
, And the latter half 4A-R5 of the program memory 4A is used as a control memory of the process 32 indicated by A 'to D', and the process 32 is used as an alternative program of the process 31.
Are executed in parallel, and when the program of the main CPU 1 is not correct, the sub-CPU 10 is partially changed to operate in parallel.
The data is checked, and if there is no abnormality, A 'to
Since D 'can be replaced with A to D in the process 31, the program can be safely changed within a limited time during adjustment or regular maintenance.

Embodiment 9 (corresponding to claim 10). Generally, if a certain output is issued during a program simulation, a certain input is returned after a timer in many cases.
Since this input is also written in the first half 4A-F6 of the program memory 4A and executed, the effect of the test program 31 is large during the simulation, and the conditions are often different from those of the original simulation. 9, the program memory 4A as shown in FIG.
An instruction 34 called a TD input corresponding to the output at the time of the simulation is provided in the latter half of the program memory 4A.
By simply writing to the A-R 6, the test program 35 becomes unnecessary, and can be realized without affecting the operating conditions of the main CPU 1, which can greatly improve the degree of completeness of program debugging and reduce the total cost.

[0043]

As described above, according to the first aspect of the invention, the information in the program memory is doubled, and the maintenance instruction is written in half of the information. Is configured to process control instructions in parallel, so that the burden on the main CPU can be greatly reduced and the control performance of the controller can be greatly improved.

According to the second aspect of the invention, since the sub CPU is configured to bear the request from the man-machine device, it contributes to the reduction of the burden on the main CPU, and the control performance by the main CPU can be dramatically improved. effective.

According to the third aspect of the present invention, since the multi-control by the main CPU and the sub CPU is performed, the execution time of the main CPU can be greatly reduced.
There is an effect that control performance can be improved.

According to the fourth aspect, the execution time measurement program is configured to be easily measured without imposing a burden on the main CPU, so that the execution time of the main CPU can be greatly reduced, and the control performance can be improved. There is an effect that can be expected.

According to the fifth aspect of the present invention, even when an instruction needs to be deleted, the control is performed without stopping the main CPU, so that the adjustment time can be greatly reduced.

According to the sixth aspect, since a high-level simulation is executed at the time of program debugging, there is an effect that cost reduction accompanying quality improvement at the time of shipment can be expected.

According to the seventh aspect, since the sub CPU backs up when the main CPU is abnormal, a highly reliable duplex system can be provided, and the reliability of the controller can be improved. .

According to the eighth aspect, the address management data of the program memory flowing from the main CPU to the program memory is paused in the data memory of the sub CPU so that troubleshooting can be performed. This has the effect of greatly contributing to a reduction in time.

According to the ninth aspect, when the program of the main CPU is not correct, the data is confirmed by the parallel operation of the partially changed sub CPU, and if there is no abnormality, the processing of the main CPU is replaced with the processing of the sub CPU. Since the replacement is performed, there is an effect that the program can be safely changed within a limited time at the time of adjustment or regular maintenance.

According to the tenth aspect, the test program is omitted from the first half of the program memory, and the main CPU
Since the configuration is such that the simulation is realized without affecting the operating conditions of the above, there is an effect that it is possible to greatly contribute to improvement of the degree of completeness of the program debugging and reduction of the total cost.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a controller according to a first embodiment.

FIG. 2 is a diagram illustrating a program memory according to the first embodiment.

FIG. 3 is a diagram illustrating a program memory according to a second embodiment.

FIG. 4 is a diagram showing a comparative example of the second embodiment.

FIG. 5 is a diagram illustrating a program memory according to a third embodiment;

FIG. 6 is a diagram showing a comparative example of the third embodiment.

FIG. 7 is a diagram illustrating a program memory according to a fourth embodiment.

FIG. 8 is a configuration diagram illustrating a controller according to a fifth embodiment.

FIG. 9 is a configuration diagram illustrating a controller according to a sixth embodiment.

FIG. 10 is a configuration diagram illustrating a controller according to a seventh embodiment.

FIG. 11 is a diagram illustrating a program memory according to an eighth embodiment.

FIG. 12 is a diagram illustrating a program memory according to a ninth embodiment;

FIG. 13 is a configuration diagram showing a conventional controller.

FIG. 14 is a conventional flowchart.

FIG. 15 is a diagram showing one conventional instruction.

[Explanation of symbols]

1 main CPU, 4A program memory, 9 man-machine device, 10, 10A, 10B sub CPU, 13
Data memory.

Claims (10)

(57) [Claims] 1. A program memory for writing twice the amount of information for one instruction of a plant control program as a first half and a second half, and a main CPU for executing address information of the program memory and executing information of the first half.
And a sub-CPU for executing information in the second half of the program memory while synchronizing the address with the main CPU. 2. The sub-CPU has program editing,
2. The controller according to claim 1, wherein a man-machine device for performing writing, correction, monitoring, and the like is connected. 3. The controller according to claim 1, wherein the first half of the program memory is a control memory, and the second half of the program memory is a control memory similar to the first half. 4. The controller according to claim 1, wherein a first half of said program memory is a control memory, and a second half of said program memory is a measurement memory. 5. The controller according to claim 1, wherein a first half of the program memory is a control memory, and a second half of the program memory is a compulsory instruction memory for reading an input signal. 6. The controller according to claim 1, wherein a data memory is connected to said sub CPU, and input signal time axis change data is input to said data memory. 7. The controller according to claim 1, wherein an address management function of a program memory is added to the sub CPU, and the same information is inserted into a first half and a second half of the program memory. 8. A trace means for tracing address management data of a program memory flowing from the main CPU to the program memory side and pausing the data memory connected to the sub CPU when the main CPU is abnormal. The controller according to claim 1, wherein: 9. A method according to claim 1, wherein a first half and a second half of said program memory are used as control memory, and said second half is partially changed when a program of said main CPU is abnormal, so that said main CPU and sub CPU are operated in parallel. The controller according to claim 1, wherein: 10. The controller according to claim 1, wherein an instruction corresponding to an output at the time of simulation is written in a latter half of said program memory.