JP2820148B2 - Anisotropic conductive film and method for mounting semiconductor device using anisotropic conductive film - Google Patents

Anisotropic conductive film and method for mounting semiconductor device using anisotropic conductive film

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Publication number
JP2820148B2
JP2820148B2 JP9272781A JP27278197A JP2820148B2 JP 2820148 B2 JP2820148 B2 JP 2820148B2 JP 9272781 A JP9272781 A JP 9272781A JP 27278197 A JP27278197 A JP 27278197A JP 2820148 B2 JP2820148 B2 JP 2820148B2
Authority
JP
Japan
Prior art keywords
conductive film
anisotropic conductive
semiconductor element
insulating resin
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP9272781A
Other languages
Japanese (ja)
Other versions
JPH1092876A (en
Inventor
伸晃 橋元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
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Filing date
Publication date
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Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP9272781A priority Critical patent/JP2820148B2/en
Publication of JPH1092876A publication Critical patent/JPH1092876A/en
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Publication of JP2820148B2 publication Critical patent/JP2820148B2/en
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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29017Shape in side view being non uniform along the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29018Shape in side view comprising protrusions or indentations
    • H01L2224/29019Shape in side view comprising protrusions or indentations at the bonding interface of the layer connector, i.e. on the surface of the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、異方性導電膜の構
造と、この異方性導電膜を用いて絶縁基板に実装される
半導体素子の実装方法に関する。
The present invention relates to a structure of an anisotropic conductive film and a method for mounting a semiconductor element mounted on an insulating substrate using the anisotropic conductive film.

【0002】[0002]

【従来の技術】従来、半導体装置の実装構造に関して
は、例えば特公昭57ー34657号公報や特開昭61
ー194769号公報に記載され、図2に示すような構
造が知られていた。図2において、21はガラス基板で
あり、22はガラス電極でありITOで形成されること
が多い。22のガラス電極は、ICチップ27上に形成
された電極26に相対するように形成されている。電極
26上には、さらに金属突起であるバンプ25が形成さ
れており、バンプ25はAuで形成されることが多い。
ICチップ27の能動面には耐湿性を向上させるため
に、パッシベーション膜がかかっていることが多い。
2. Description of the Related Art Conventionally, a mounting structure of a semiconductor device is disclosed in, for example, Japanese Patent Publication No. 57-34657 and
No. 1-94769, a structure as shown in FIG. 2 has been known. In FIG. 2, reference numeral 21 denotes a glass substrate, and reference numeral 22 denotes a glass electrode, which is often formed of ITO. The glass electrode 22 is formed so as to face the electrode 26 formed on the IC chip 27. On the electrode 26, a bump 25 as a metal projection is further formed, and the bump 25 is often formed of Au.
The active surface of the IC chip 27 is often covered with a passivation film in order to improve moisture resistance.

【0003】ICチップ27と、ガラス基板21の間に
は導電粒子28を含んだ異方性導電膜24が充填されて
いる。ガラス基板21上のガラス電極22とICチップ
27上の電極26、さらに電極26上に形成されたバン
プ25とは、この異方性導電膜24中に含まれた導電粒
子28によって電気的に接続されている。異方性導電膜
は従来からよく知られているように、基本的には絶縁接
着剤と導電粒子とから成っている。絶縁接着剤はSBR
系や、エポキシ系であることが多く、ICチップとガラ
ス基板はこの絶縁接着剤によって接着されている。導電
粒子は、低融点ハンダ、Ni粒子、Niメッキを施した
プラスチック粒子である場合が多い。
A space between the IC chip 27 and the glass substrate 21 is filled with an anisotropic conductive film 24 containing conductive particles 28. The glass electrodes 22 on the glass substrate 21 are electrically connected to the electrodes 26 on the IC chip 27 and the bumps 25 formed on the electrodes 26 by conductive particles 28 contained in the anisotropic conductive film 24. Have been. As is well known, the anisotropic conductive film basically includes an insulating adhesive and conductive particles. Insulating adhesive is SBR
System or epoxy system in many cases, and the IC chip and the glass substrate are bonded by this insulating adhesive. The conductive particles are often low-melting solder, Ni particles, or Ni-plated plastic particles.

【0004】さらに、接続の信頼性を向上させるため
に、絶縁樹脂23でIC実装部全体を封止することが多
く、このような構造によって高い接続信頼性を得てい
た。
Further, in order to improve the connection reliability, the entire IC mounting portion is often sealed with an insulating resin 23, and such a structure has provided high connection reliability.

【0005】[0005]

【発明が解決しようとする課題】しかし、従来の半導体
装置の実装構造では以下の問題点を有していた。
However, the conventional semiconductor device mounting structure has the following problems.

【0006】異方性導電膜は、前述したように、絶縁樹
脂中に導電粒子を分散した構造であるため、部分的に導
電粒子の集中が起こってしまう。図2に示されるよう
に、異方性導電膜24がICチップ27と、ガラス基板
21に充填される構造であるために、異方性導電膜24
中に分散している導電粒子28の集中が起こってしま
い、29のガラス電極間短絡部や30のICチップ〜ガ
ラス電極間短絡部で、本来絶縁が保たれていなければな
らない、ガラス電極間同士や、ICチップの能動面〜ガ
ラス電極間で短絡が起こってしまい、ICチップが正常
に動作しなくなってしまうのである。
As described above, the anisotropic conductive film has a structure in which conductive particles are dispersed in an insulating resin, so that the conductive particles are partially concentrated. As shown in FIG. 2, the anisotropic conductive film 24 has a structure in which the IC chip 27 and the glass substrate 21 are filled.
Concentration of the conductive particles 28 dispersed therein occurs, and the insulation between the glass electrodes must be maintained at the short circuit between the glass electrodes 29 and the short circuit between the IC chip and the glass electrode 30. Also, a short circuit occurs between the active surface of the IC chip and the glass electrode, and the IC chip does not operate normally.

【0007】これは、導電粒子分散型の異方性導電膜を
用いる場合、避けては通れない本質的な問題である。す
なわち、導電粒子の分散濃度を下げると、上記の短絡現
象の確率は少なくなるものの、バンプ〜ガラス電極間に
存在する粒子の確率も少なくなるため、接続そのものの
信頼性が低下する。また、導電粒子の分散濃度を上げれ
ば、接続信頼性は向上するが、短絡現象の確率も上が
り、やはり半導体装置の実装構造として機能しなくなる
のである。一般的に導電粒子の分散濃度は上記条件を鑑
みて決定されるが、確率現象である以上、短絡現象によ
る半導体装置の実装不良は0にはなり得なかった。ま
た、導電粒子の粒子径を小さくして少しでも短絡現象の
可能性を下げる試みも公知であるが、これとて問題の本
質的解決にはなっていないのである。
[0007] This is an essential problem that cannot be avoided when using an anisotropic conductive film in which conductive particles are dispersed. That is, when the dispersion concentration of the conductive particles is reduced, the probability of the short-circuit phenomenon is reduced, but the probability of the particles existing between the bump and the glass electrode is also reduced, so that the reliability of the connection itself is reduced. In addition, if the dispersion concentration of the conductive particles is increased, the connection reliability is improved, but the probability of a short circuit phenomenon is also increased, so that the semiconductor device cannot function as a mounting structure of the semiconductor device. Generally, the dispersion concentration of the conductive particles is determined in view of the above conditions. However, since it is a stochastic phenomenon, the mounting failure of the semiconductor device due to the short circuit phenomenon cannot be zero. In addition, an attempt to reduce the possibility of a short-circuit phenomenon by reducing the particle diameter of the conductive particles to some extent is also known, but this has not been an essential solution to the problem.

【0008】このような問題点を解決するため、本発明
ではガラス電極間の短絡、半導体素子〜ガラス電極間の
短絡を本質的に防止し得る異方性導電膜および半導体素
子の実装方法を提供することを目的としている。
In order to solve such problems, the present invention provides an anisotropic conductive film and a semiconductor element mounting method capable of essentially preventing a short circuit between glass electrodes and a short circuit between a semiconductor element and a glass electrode. It is intended to be.

【0009】[0009]

【課題を解決するための手段】本発明の異方性導電膜
は、シート状の異方性導電と、前記シート状の異方性導
電膜上に設置され、前記シート状の異方性導電膜と2層
構造をなすシート状の絶縁樹脂と、から構成される。
The anisotropic conductive film of the present invention comprises a sheet-like anisotropic conductive film and the sheet-like anisotropic conductive film provided on the sheet-like anisotropic conductive film. And a sheet-like insulating resin having a two-layer structure.

【0010】そして、本発明の半導体素子の実装方法
は、異方性導電膜を半導体素子能動表面に載置する工
程、前記半導体素子と、前記半導体素子が実装される絶
縁基板とを位置合わせした後、前記半導体素子と前記絶
縁基板を圧接することにより、前記半導体素子を前記異
方性導電膜を介して前記絶縁基板に実装する工程、を有
する。
In the method of mounting a semiconductor device according to the present invention, the step of mounting an anisotropic conductive film on the active surface of the semiconductor device includes aligning the semiconductor device with an insulating substrate on which the semiconductor device is mounted. And a step of mounting the semiconductor element on the insulating substrate via the anisotropic conductive film by pressing the semiconductor element against the insulating substrate.

【0011】また、本発明の半導体素子の実装方法は、
異方性導電膜を絶縁基板に載置する工程、前記絶縁基板
と、前記絶縁基板に実装される半導体素子とを位置合わ
せした後、前記半導体素子と前記絶縁基板とを圧接する
ことにより、前記半導体素子を前記異方性導電膜を介し
て前記絶縁基板に実装する工程、を有する。
Further, the method of mounting a semiconductor device according to the present invention comprises:
Placing the anisotropic conductive film on an insulating substrate, after aligning the insulating substrate and a semiconductor element mounted on the insulating substrate, by pressing the semiconductor element and the insulating substrate, Mounting a semiconductor element on the insulating substrate via the anisotropic conductive film.

【0012】[0012]

【作用】本発明では半導体素子能動素子形成面と絶縁基
板上に形成された配線パターンの間に絶縁樹脂が存在す
る構造としたので、絶縁樹脂が電気的絶縁層になり、半
導体素子と配線パターンとの間に短絡は起こらない。
According to the present invention, the structure in which the insulating resin is present between the semiconductor element active element forming surface and the wiring pattern formed on the insulating substrate is employed. And no short circuit occurs between them.

【0013】[0013]

【発明の実施の形態】以下に、本発明の実施例を図面に
基づき、詳細に説明する。
Embodiments of the present invention will be described below in detail with reference to the drawings.

【0014】図1は、本発明の半導体素子の実装構造の
断面図である。1は基板であり、ガラス、セラミック
ス、樹脂等で形成されていることが多く、少なくとも表
面が絶縁されている。半導体素子7の電極6に、例えば
CrーCu、TiーPd等の金属を被着した後、金属突
起5を形成する。金属突起5は、Au、Cu、ハンダ等
の金属であり、電気メッキ、スパッタ、蒸着等で数μm
〜数10μmの厚さに形成されることが多い。基板1上
には、半導体素子7の金属突起5と対応した位置に配線
パターン2が形成されている。配線パターンは、金属も
しくは金属酸化物を用いるのが一般的であり、Ni、C
u、Au、Al又はITO等で形成すれば良く、必要に
応じてメッキ処理を施せば良い。それらの配線パターン
を重ねて、さらに低抵抗化しても良い。異方性導電膜1
0は、シート状または液状であり、絶縁樹脂B4と、導
電粒子9との混合物から成る。金属突起5と配線パター
ン2とは、導電粒子9を通して電気的導通が行われてい
る。絶縁樹脂Bは、SBR系樹脂、エポキシ系樹脂、ア
クリル系樹脂等である場合が多い。導電粒子は、低融点
ハンダ粒子、Ni粒子、Ni、Au等のメッキを行った
プラスチック粒子等がよく用いられる。異方性導電膜1
0は金属突起5より薄く、半導体素子7の能動素子形成
面と、配線パターン2との間には結果として空隙8が生
じ、これが絶縁層となる。さらに、耐湿環境下での接続
信頼性を向上させるために、半導体素子実装部分の周
囲、半導体素子上全面に絶縁樹脂A3が塗布されること
が多い。絶縁樹脂Aは、エポキシ系樹脂、アクリル系樹
脂、シリコーン系樹脂等であることが多く、絶縁樹脂B
と同一でも良い。半導体素子7と基板1とは、基本的に
は絶縁樹脂Bで接着している。金属突起5は、配線パタ
ーン2上に、半導体素子7の電極6の位置に相対するよ
うに形成されている場合もあり、また、前述の導電粒子
を印刷等の方法で電極6と、配線パターン2との位置に
相対するように設置するようにしても良い。
FIG. 1 is a sectional view of a mounting structure of a semiconductor device according to the present invention. Reference numeral 1 denotes a substrate, which is often formed of glass, ceramics, resin, or the like, and has at least a surface insulated. After a metal such as Cr—Cu or Ti—Pd is applied to the electrode 6 of the semiconductor element 7, the metal projection 5 is formed. The metal protrusion 5 is made of a metal such as Au, Cu, or solder, and has a thickness of several μm by electroplating, sputtering, vapor deposition, or the like.
It is often formed to a thickness of up to several tens of μm. The wiring pattern 2 is formed on the substrate 1 at a position corresponding to the metal protrusion 5 of the semiconductor element 7. Generally, a metal or metal oxide is used for the wiring pattern.
It may be made of u, Au, Al, ITO, or the like, and may be plated as needed. The resistance may be further reduced by overlapping these wiring patterns. Anisotropic conductive film 1
Numeral 0 is a sheet or liquid, and is made of a mixture of the insulating resin B4 and the conductive particles 9. The metal protrusion 5 and the wiring pattern 2 are electrically connected through the conductive particles 9. The insulating resin B is often an SBR resin, an epoxy resin, an acrylic resin, or the like. As the conductive particles, low melting point solder particles, Ni particles, plastic particles plated with Ni, Au, or the like are often used. Anisotropic conductive film 1
0 is thinner than the metal protrusion 5, and as a result, a gap 8 is formed between the active element forming surface of the semiconductor element 7 and the wiring pattern 2, and this becomes an insulating layer. Further, in order to improve the connection reliability in a moisture-resistant environment, the insulating resin A3 is often applied around the semiconductor element mounting portion and the entire surface of the semiconductor element. The insulating resin A is often an epoxy resin, an acrylic resin, a silicone resin, or the like.
May be the same as The semiconductor element 7 and the substrate 1 are basically bonded with an insulating resin B. The metal protrusion 5 may be formed on the wiring pattern 2 so as to be opposed to the position of the electrode 6 of the semiconductor element 7, and the conductive particles may be formed on the wiring pattern 2 by printing or the like. 2 may be installed so as to be opposed to the position.

【0015】図3は、本発明の半導体素子の実装構造を
基板側から見た正面図である。1の基板上に形成された
配線パターン2は、10の異方性導電膜中に含まれる導
電粒子9を通して、半導体素子7上に形成されている金
属突起5と電気的に接続している。半導体素子7と基板
1とは異方性導電膜10中の絶縁樹脂B4で接着してい
る。半導体素子7と基板1との間には、異方性導電膜1
0が金属突起5より薄いため空隙8が生じており、基板
1と半導体素子7との間の電気的絶縁は保たれている。
また、半導体素子7直下の配線パターン2の間にも異方
性導電膜10は存在せず、空隙8のため電気的絶縁が保
たれている。このため、半導体素子と配線パターン間、
配線パターン間での短絡は起こらない。3は耐湿環境下
での信頼性を向上させるための絶縁樹脂Aである。
FIG. 3 is a front view of the semiconductor device mounting structure of the present invention as viewed from the substrate side. The wiring pattern 2 formed on the substrate 1 is electrically connected to the metal protrusions 5 formed on the semiconductor element 7 through the conductive particles 9 included in the anisotropic conductive film 10. The semiconductor element 7 and the substrate 1 are bonded with an insulating resin B4 in the anisotropic conductive film 10. Anisotropic conductive film 1 is provided between semiconductor element 7 and substrate 1.
Since 0 is thinner than the metal protrusion 5, a gap 8 is formed, and electrical insulation between the substrate 1 and the semiconductor element 7 is maintained.
Further, the anisotropic conductive film 10 does not exist between the wiring patterns 2 immediately below the semiconductor element 7, and the electrical insulation is maintained because of the gap 8. Therefore, between the semiconductor element and the wiring pattern,
No short circuit occurs between the wiring patterns. Reference numeral 3 denotes an insulating resin A for improving reliability in a moisture-resistant environment.

【0016】図4は、本発明による半導体素子の実装構
造の他の実施例を示す断面図である。異方性導電膜10
が、半導体素子7の電極6上に形成された金属突起5
と、基板1上に形成されている配線パターン2との間に
選択的に存在している。このため、半導体素子7と配線
パターン2との間には図1で示される実施例よりさらに
広い空隙8が得られ、絶縁性能がさらに向上する。その
他の構造は図1の実施例と同様である。さらに選択的
に、金属突起5の直下のみに異方性導電膜10を存在さ
せても良い。
FIG. 4 is a sectional view showing another embodiment of the mounting structure of the semiconductor device according to the present invention. Anisotropic conductive film 10
Are metal protrusions 5 formed on electrodes 6 of semiconductor element 7.
And the wiring pattern 2 formed on the substrate 1. Therefore, a larger gap 8 is obtained between the semiconductor element 7 and the wiring pattern 2 than in the embodiment shown in FIG. 1, and the insulation performance is further improved. Other structures are the same as those of the embodiment of FIG. Further alternatively, the anisotropic conductive film 10 may be present only directly below the metal protrusion 5.

【0017】図1の構造を得るための半導体装置の実装
方法を図8を用いて説明する。図8(a)のように、半
導体素子7の電極6上に形成されている金属突起5側の
半導体素子表面に異方性導電膜10を仮付けする。異方
性導電膜10は金属突起5よりも薄い。次に基板1上の
配線パターン2と金属突起5とが所定の位置になるよう
に位置合わせを行い、次に半導体素子7と基板1を圧接
する。すると、金属突起5と配線パターン2によって異
方性導電膜中の絶縁樹脂が押しのけられ、導電粒子9が
金属突起5と配線パターン2とに直接接触し、電気的導
通が生じる。(図8(b))この状態で、あるいは圧接
と同時に、異方性導電膜中の絶縁樹脂が接着力を発現す
るように、熱、光等のエネルギーを加える。すると、半
導体素子と基板との間に空隙8が保たれたまま接着が完
了する。
A method for mounting a semiconductor device to obtain the structure shown in FIG. 1 will be described with reference to FIG. As shown in FIG. 8A, an anisotropic conductive film 10 is temporarily attached to the surface of the semiconductor element 7 on the side of the metal projection 5 formed on the electrode 6 of the semiconductor element 7. The anisotropic conductive film 10 is thinner than the metal protrusion 5. Next, the wiring pattern 2 on the substrate 1 and the metal protrusion 5 are aligned so as to be at predetermined positions, and then the semiconductor element 7 and the substrate 1 are pressed against each other. Then, the insulating resin in the anisotropic conductive film is displaced by the metal protrusions 5 and the wiring pattern 2, and the conductive particles 9 directly contact the metal protrusions 5 and the wiring pattern 2, thereby causing electrical conduction. (FIG. 8B) In this state or simultaneously with the pressing, energy such as heat and light is applied so that the insulating resin in the anisotropic conductive film develops adhesive strength. Then, the bonding is completed while the gap 8 is maintained between the semiconductor element and the substrate.

【0018】また、図4の構造を得るための実装方法を
図9を用いて説明する。図9(a)のように、半導体素
子7の電極6上に形成されている金属突起5上に選択的
に異方性導電膜10を載置する。載置する方法として
は、あらかじめ金属突起5に合わせて型抜きしてある異
方性導電膜を、金属突起5に位置合わせして仮圧着する
方法や、金属突起5に相対するように液状の異方性導電
膜を印刷、転写等で付着する方法などがある。その後、
図8の実施例で説明したのと同様に、基板1上の配線パ
ターン2と、半導体素子7上の金属突起5を位置合わせ
した後、圧着を行う。すると、図9(b)で示されるよ
うに、半導体素子7と、その能動面直下の基板1上の配
線パターン2との間には、空隙8のみが存在することに
なる。
A mounting method for obtaining the structure shown in FIG. 4 will be described with reference to FIG. As shown in FIG. 9A, the anisotropic conductive film 10 is selectively placed on the metal protrusion 5 formed on the electrode 6 of the semiconductor element 7. As a mounting method, an anisotropic conductive film that has been die-cut in advance in accordance with the metal protrusion 5 is aligned with the metal protrusion 5 and temporarily press-bonded. There is a method of attaching an anisotropic conductive film by printing, transfer, or the like. afterwards,
As described in the embodiment of FIG. 8, after the wiring pattern 2 on the substrate 1 and the metal protrusion 5 on the semiconductor element 7 are aligned, pressure bonding is performed. Then, as shown in FIG. 9B, only the gap 8 exists between the semiconductor element 7 and the wiring pattern 2 on the substrate 1 immediately below the active surface.

【0019】図5は、本発明の半導体素子の実装構造の
他の実施例を示す断面図である。異方性導電膜10が、
半導体素子7の電極6上に形成された金属突起5と、基
板1上に形成されている配線パターン2との間と、半導
体素子7の能動面上に存在している。異方性導電膜と配
線パターン2との間には絶縁樹脂Cが存在している。こ
の絶縁樹脂C11は、エポキシ系、アクリル系、シリコ
ーン系等絶縁性を有する樹脂であれば何でも良く、液状
又はシート状であることが多く耐湿性向上のための絶縁
樹脂A、異方性導電膜中の絶縁樹脂Bと同じでも良い。
この絶縁樹脂Cによって、半導体素子と配線パターン
間、配線パターン同士での短絡は起こらない。その他の
構成は、図1で説明したのと同一である。絶縁樹脂Aと
異方性導電膜10にかこまれた部分の絶縁樹脂C11は
存在しなくともよい。
FIG. 5 is a sectional view showing another embodiment of the mounting structure of the semiconductor device of the present invention. Anisotropic conductive film 10
It is present between the metal projection 5 formed on the electrode 6 of the semiconductor element 7 and the wiring pattern 2 formed on the substrate 1 and on the active surface of the semiconductor element 7. An insulating resin C exists between the anisotropic conductive film and the wiring pattern 2. The insulating resin C11 may be any resin having an insulating property such as an epoxy-based resin, an acrylic-based resin, or a silicone-based resin. It may be the same as the inner insulating resin B.
The insulating resin C does not cause a short circuit between the semiconductor element and the wiring pattern or between the wiring patterns. Other configurations are the same as those described in FIG. The portion of the insulating resin C11 between the insulating resin A and the anisotropic conductive film 10 may not be present.

【0020】図6は、本発明の半導体素子の実装構造を
基板側から見た正面図である。1の基板上に形成された
配線パターン2は、10の異方性導電膜中に含まれる導
電粒子9を通して、半導体素子7上に形成されている金
属突起5とは電気的に接続している。半導体素子7と基
板1とは異方性導電膜10中の絶縁樹脂B4で接着して
いる。半導体素子7と基板1との間には、絶縁樹脂C1
1が充填されており、基板1と半導体素子7との間の電
気的絶縁が保たれている。また、半導体素子7直下の配
線パターン2の間にも絶縁樹脂C11が充填されている
ため、電気的絶縁が保たれている。このため、半導体素
子と配線パターン間、配線パターン間での短絡は起こら
ない。3は、耐湿環境下での信頼性を向上させるための
絶縁樹脂Aである。
FIG. 6 is a front view of the mounting structure of the semiconductor device of the present invention as viewed from the substrate side. The wiring pattern 2 formed on the substrate 1 is electrically connected to the metal protrusions 5 formed on the semiconductor element 7 through the conductive particles 9 included in the anisotropic conductive film 10. . The semiconductor element 7 and the substrate 1 are bonded with an insulating resin B4 in the anisotropic conductive film 10. An insulating resin C1 is provided between the semiconductor element 7 and the substrate 1.
1 is filled, and electrical insulation between the substrate 1 and the semiconductor element 7 is maintained. In addition, since the insulating resin C11 is filled also between the wiring patterns 2 immediately below the semiconductor element 7, electrical insulation is maintained. Therefore, no short circuit occurs between the semiconductor element and the wiring pattern or between the wiring patterns. Reference numeral 3 denotes an insulating resin A for improving reliability in a moisture-resistant environment.

【0021】図7は、本発明による半導体素子の実装構
造の他の実施例を示す断面図である。異方性導電膜10
が、半導体素子7の電極6上に形成された金属突起5
と、基板1上に形成されている配線パターン2との間に
選択的に存在している。このため、半導体素子7と配線
パターン2との間には、図6で示される実施例よりさら
に広い絶縁樹脂C11の充填層が得られ、絶縁性能がさ
らに向上する。その他の構造は、図6の実施例と同様で
ある。さらに選択的に、金属突起5の真下のみに異方性
導電膜10を存在させても良い。
FIG. 7 is a sectional view showing another embodiment of the mounting structure of the semiconductor device according to the present invention. Anisotropic conductive film 10
Are metal protrusions 5 formed on electrodes 6 of semiconductor element 7.
And the wiring pattern 2 formed on the substrate 1. For this reason, a wider filling layer of the insulating resin C11 is obtained between the semiconductor element 7 and the wiring pattern 2 than in the embodiment shown in FIG. 6, and the insulating performance is further improved. Other structures are the same as those of the embodiment of FIG. Further alternatively, the anisotropic conductive film 10 may be present only under the metal protrusion 5.

【0022】図5の構造を得るための半導体装置の実装
方法を図10を用いて説明する。図10(a)のよう
に、半導体素子7の電極6上に形成されている金属突起
5側の半導体素子表面に異方性導電膜10を仮付けす
る。異方性導電膜10は金属突起5よりも薄い。次に、
基板1上の配線パターン上に絶縁樹脂C11を塗布又
は、設置する。さらに、基板1上の配線パターン2と金
属突起5とが所定の位置になるように位置合わせを行
い、半導体素子7と基板1を圧接する。すると、金属突
起5と配線パターン2によって異方性導電膜10中の絶
縁樹脂が押しのけられ、導電粒子9が金属突起5と配線
パターン2とに直接接触し、電気的導通が生じる。(図
10(b))この状態で、あるいは圧接と同時に、少な
くとも異方性導電膜中の絶縁樹脂が接着力を発現するよ
うに、熱・光等のエネルギーを加える。すると、半導体
素子と基板との間に絶縁樹脂C11が充填されたまま、
接着が完了する。絶縁樹脂Cは、異方性導電膜の接着力
が発現されるのと同時に接着力が発現するようにしても
良いし、最初に基板上に塗布、又は設置する時に基板と
の接着を行っておいても良い。
A method of mounting a semiconductor device to obtain the structure shown in FIG. 5 will be described with reference to FIG. As shown in FIG. 10A, an anisotropic conductive film 10 is temporarily attached to the surface of the semiconductor element 7 on the side of the metal projection 5 formed on the electrode 6 of the semiconductor element 7. The anisotropic conductive film 10 is thinner than the metal protrusion 5. next,
An insulating resin C11 is applied or placed on the wiring pattern on the substrate 1. Further, the wiring pattern 2 on the substrate 1 and the metal protrusion 5 are aligned so as to be at predetermined positions, and the semiconductor element 7 and the substrate 1 are pressed against each other. Then, the insulating resin in the anisotropic conductive film 10 is displaced by the metal protrusions 5 and the wiring pattern 2, and the conductive particles 9 come into direct contact with the metal protrusions 5 and the wiring pattern 2, thereby causing electrical conduction. (FIG. 10B) In this state or simultaneously with the pressure welding, energy such as heat and light is applied so that at least the insulating resin in the anisotropic conductive film develops an adhesive force. Then, while the insulating resin C11 is filled between the semiconductor element and the substrate,
The bonding is completed. The insulating resin C may be designed so that the adhesive force is developed at the same time as the adhesive force of the anisotropic conductive film is developed. You can leave it.

【0023】また、図5の構造を得るための半導体装置
の他の実装方法を図14を用いて説明する。図14
(a)のように、半導体素子7の電極6上に形成されて
いる金属突起5側の半導体素子表面に異方性導電膜10
を仮付けする。異方性導電膜10は、半導体素子7の金
属突起5よりも薄い。異方性導電膜10は、はじめから
絶縁樹脂C11と2層の構造となっていても良いし、異
方性導電膜10を半導体素子表面に仮付けした後、絶縁
樹脂C11をその上に塗布又は、設置しても良い。ま
た、金属突起5に相対するようなマスク・版で、導電粒
子9のみを絶縁樹脂C11上に付着させ、異方性導電膜
の絶縁樹脂を絶縁樹脂C11で兼ねても良い。次に、基
板1上の配線パターン2と金属突起5とが所定の位置に
来るように位置合わせを行い、半導体素子7と基板1を
圧接する。すると、金属突起5と配線パターン2によっ
て、まず絶縁樹脂C11が押しのけられ、続いて異方性
導電膜10中の絶縁樹脂が押しのけられ、導電粒子9が
金属突起5と配線パターン2とに直接接触し、電気的導
通が生じる。(図14(b))以後の実装の手順・メカ
ニズムは、図10の実施例中で説明したのとまったく同
様である。
Another mounting method of the semiconductor device for obtaining the structure of FIG. 5 will be described with reference to FIG. FIG.
As shown in (a), the anisotropic conductive film 10 is formed on the surface of the semiconductor element 7 on the side of the metal projection 5 formed on the electrode 6 of the semiconductor element 7.
Temporarily attach. The anisotropic conductive film 10 is thinner than the metal protrusion 5 of the semiconductor element 7. The anisotropic conductive film 10 may have a two-layer structure with the insulating resin C11 from the beginning. Alternatively, after the anisotropic conductive film 10 is temporarily attached to the surface of the semiconductor element, the insulating resin C11 is applied thereon. Or you may install. Alternatively, only the conductive particles 9 may be adhered to the insulating resin C11 with a mask / plate facing the metal protrusion 5, and the insulating resin of the anisotropic conductive film may also serve as the insulating resin C11. Next, positioning is performed so that the wiring pattern 2 and the metal protrusion 5 on the substrate 1 are at predetermined positions, and the semiconductor element 7 and the substrate 1 are pressed against each other. Then, the insulating resin C11 is firstly displaced by the metal protrusion 5 and the wiring pattern 2, then the insulating resin in the anisotropic conductive film 10 is displaced, and the conductive particles 9 directly contact the metal protrusion 5 and the wiring pattern 2. As a result, electrical conduction occurs. (FIG. 14 (b)) The mounting procedure and mechanism thereafter are exactly the same as those described in the embodiment of FIG.

【0024】次に、図7の構造を得るための半導体装置
の実装方法を図11を用いて説明する。図11(a)の
ように、半導体素子7の電極6上に形成されている金属
突起5付近、あるいは金属突起5の側面を除く先端部の
みに選択的に異方性導電膜10を仮付けする。選択的に
仮付する方法は、図9の実施例中で説明した方法と同様
である。基板1上には、半導体素子7の金属突起5に少
なくとも相対するように配線パターン2が形成されてい
るが、基板1上で、前述の金属突起5とは相対せず、半
導体素子7の能動面に相対する部分に、絶縁樹脂C11
を塗布又は設置する。次に金属突起5と配線パターン2
とを位置合わせし、半導体素子7と基板1を圧接する。
すると、金属突起5と配線パターン2によって、異方性
導電膜10中の絶縁樹脂が押しのけられ、導電粒子9が
金属突起5と配線パターン2とに直接接触し、電気的導
通が生じる。(図11(b))以後の実装の手順・メカ
ニズムは、図10の実施例中で説明したのとまったく同
様である。
Next, a method of mounting a semiconductor device for obtaining the structure of FIG. 7 will be described with reference to FIG. As shown in FIG. 11A, the anisotropic conductive film 10 is temporarily attached selectively only to the vicinity of the metal projection 5 formed on the electrode 6 of the semiconductor element 7 or only to the tip excluding the side surface of the metal projection 5. I do. The method of selective provision is the same as the method described in the embodiment of FIG. The wiring pattern 2 is formed on the substrate 1 so as to be at least opposed to the metal protrusion 5 of the semiconductor element 7. Insulation resin C11
Is applied or installed. Next, the metal protrusion 5 and the wiring pattern 2
And the semiconductor element 7 and the substrate 1 are pressed against each other.
Then, the insulating resin in the anisotropic conductive film 10 is displaced by the metal protrusion 5 and the wiring pattern 2, and the conductive particles 9 come into direct contact with the metal protrusion 5 and the wiring pattern 2, thereby causing electrical conduction. (FIG. 11 (b)) The mounting procedure and mechanism thereafter are exactly the same as those described in the embodiment of FIG.

【0025】さらに、図7の構造を得るための半導体装
置の別の実装方法を図12を用いて説明する。図12
(a)のように、半導体素子7の電極6上に形成されて
いる金属突起5に相対する、基板1上に形成された配線
パターン2の部分に選択的に異方性導電膜10を、基板
1上のその他の半導体素子能動面直下に相対する部分に
は絶縁樹脂C11を設置又は塗布して仮付けする。異方
性導電膜10と絶縁樹脂C11はあらかじめ、前述のよ
うな位置関係になっているシート状一体のものでも良い
し、絶縁樹脂C11をあらかじめ基板1上に載置しその
後異方性導電膜10を前述の位置に載置しても良いし、
逆に異方性導電膜10を載置した後絶縁樹脂C11を載
置しても良い。異方性導電膜10を選択的に仮付けする
方法としては、図9の実施例中で説明した方法と同様で
ある。次に金属突起5と配線パターン2を位置合わせす
るが、これ以後の実装の手順・メカニズムは図11の実
施例中で説明した方法と同様である。
Further, another mounting method of the semiconductor device for obtaining the structure of FIG. 7 will be described with reference to FIG. FIG.
As shown in (a), an anisotropic conductive film 10 is selectively applied to a portion of the wiring pattern 2 formed on the substrate 1, which is opposed to the metal protrusion 5 formed on the electrode 6 of the semiconductor element 7. An insulating resin C11 is provided or applied to a portion of the substrate 1 facing directly below the other active surface of the semiconductor element, and is temporarily attached. The anisotropic conductive film 10 and the insulating resin C11 may be a sheet-shaped integral member having the above-described positional relationship in advance, or the insulating resin C11 may be placed on the substrate 1 in advance, and then the anisotropic conductive film C11 may be used. 10 may be placed in the position described above,
Conversely, the insulating resin C11 may be placed after the anisotropic conductive film 10 is placed. The method of selectively temporarily attaching the anisotropic conductive film 10 is the same as the method described in the embodiment of FIG. Next, the metal protrusion 5 and the wiring pattern 2 are aligned. The mounting procedure and mechanism thereafter are the same as those described in the embodiment of FIG.

【0026】次に、図7の構造を得るための半導体装置
の別の実装方法を図13を用いて説明する。図13
(a)のように、半導体素子7の電極6上に形成されて
いる金属突起5付近、あるいは金属突起5の側面を除く
先端部のみに選択的に異方性導電膜10を仮付けする。
選択的に仮付けする方法は図9の実施例中で説明したの
と同様である。異方性導電膜10を仮付けした部分以外
の半導体素子7の能動素子形成面上には絶縁樹脂C11
を塗布又は設置して仮付けする。異方性導電膜10と絶
縁樹脂C11はあらかじめ前述のような位置関係になっ
ているようなシート状一体のものでも良いし、絶縁樹脂
Cをあらかじめ半導体素子7の能動素子形成面上に載置
しその後異方性導電膜10を前述の位置に裁置しても良
いし、逆に異方性導電膜10を載置した後絶縁樹脂C1
1を載置しても良い。次に、金属突起5と配線パターン
2とを位置合わせするが、これ以後の実装の手順・メカ
ニズムは図11の実施例中で説明した方法と同様であ
る。
Next, another mounting method of the semiconductor device for obtaining the structure of FIG. 7 will be described with reference to FIG. FIG.
As shown in FIG. 3A, the anisotropic conductive film 10 is temporarily attached selectively to the vicinity of the metal projection 5 formed on the electrode 6 of the semiconductor element 7 or only to the tip excluding the side surface of the metal projection 5.
The method of selectively tacking is the same as that described in the embodiment of FIG. An insulating resin C11 is provided on the active element forming surface of the semiconductor element 7 other than the portion where the anisotropic conductive film 10 is temporarily attached.
Is applied or installed and temporarily attached. The anisotropic conductive film 10 and the insulating resin C11 may be a sheet-shaped integral member having the above-described positional relationship in advance, or the insulating resin C may be placed on the active element forming surface of the semiconductor element 7 in advance. Thereafter, the anisotropic conductive film 10 may be placed at the above-described position, or conversely, after the anisotropic conductive film 10 is placed, the insulating resin C1 may be placed.
1 may be placed. Next, the metal projection 5 and the wiring pattern 2 are aligned. The mounting procedure and mechanism thereafter are the same as those described in the embodiment of FIG.

【0027】また、図7の構造を得るための半導体装置
のさらに他の実装方法を図15を用いて説明する。図1
5(a)のように、半導体素子7の電極6上に形成され
ている金属突起5付近、あるいは金属突起5の側面を除
く先端部のみに選択的に異方性導電膜10が載置されて
いる。半導体素子7の能動素子形成面上と、前述の異方
性導電膜10上全面には絶縁樹脂C11が載置されてい
る。異方性導電膜10を選択的に載置、仮付けするため
には、図9の実施例中で説明した方法と同じ方法を用い
れば良く、その後、絶縁樹脂C11を全面に塗布又は設
置すれば良い。もしくは、絶縁樹脂C11上に前述の位
置関係になるようにあらかじめ異方性導電膜10を載置
した2層シート状物質を、半導体素子7上の金属突起5
と異方性導電膜10の存在場所とを位置合わせした後、
半導体素子7と2層シート状物質を仮付けしても良い。
異方性導電膜10を選択的な位置に存在させ2層シート
状物質とするためには、あらかじめ金属突起5に合わせ
て型抜きしてある異方性導電膜をその位置関係を保った
まま、絶縁樹脂C11上に設置する方法や、金属突起5
に相対するように液状の異方性導電膜を印刷、転写等で
絶縁樹脂C11上に付着させる方法、あるいは、導電粒
子9のみを金属突起5に相対するようなマスク、版等で
絶縁樹脂C11上に付着させ、異方性導電膜の絶縁樹脂
を絶縁樹脂C11で兼ねてしまう方法等がある。次に、
金属突起5と配線パターン2とを位置合わせするが、こ
れ以後の実装の手順・メカニズムは図14の実施例中で
説明した方法と同様である。
Another method of mounting the semiconductor device for obtaining the structure shown in FIG. 7 will be described with reference to FIG. FIG.
As shown in FIG. 5A, the anisotropic conductive film 10 is selectively placed in the vicinity of the metal protrusion 5 formed on the electrode 6 of the semiconductor element 7 or only at the tip excluding the side surface of the metal protrusion 5. ing. An insulating resin C11 is mounted on the active element forming surface of the semiconductor element 7 and on the entire surface of the anisotropic conductive film 10 described above. In order to selectively place and temporarily attach the anisotropic conductive film 10, the same method as that described in the embodiment of FIG. 9 may be used, and thereafter, the insulating resin C11 is applied or placed on the entire surface. Good. Alternatively, a two-layer sheet-like substance on which the anisotropic conductive film 10 is previously placed on the insulating resin C11 so as to have the above-described positional relationship is placed on the metal protrusion 5 on the semiconductor element 7.
After aligning the location of the anisotropic conductive film 10 with
The semiconductor element 7 and the two-layer sheet material may be temporarily attached.
In order for the anisotropic conductive film 10 to be present at a selective position to form a two-layer sheet-like material, the anisotropic conductive film that has been die-cut in advance in accordance with the metal protrusions 5 is maintained while maintaining its positional relationship. , The method of installing on the insulating resin C11, the metal protrusion 5
A method in which a liquid anisotropic conductive film is attached to the insulating resin C11 by printing, transfer, or the like, or a method in which only the conductive particles 9 are opposed to the metal protrusions 5 by a mask, a plate, or the like. There is a method in which the insulating resin of the anisotropic conductive film is used as the insulating resin C11 so that the insulating resin is used as the insulating resin. next,
The metal projection 5 and the wiring pattern 2 are aligned, and the mounting procedure and mechanism thereafter are the same as those described in the embodiment of FIG.

【0028】次に、図5の構造を得るための別の実装方
法を図16を用いて説明する。図16(a)のように、
基板1上の配線パターン2上、少なくとも半導体素子3
に相対する部分全面に絶縁樹脂3が載置され、さらにそ
の上に異方性導電膜10を載置する。異方性導電膜10
と絶縁樹脂C11はあらかじめ2層の構造をなすシート
状一体のものでも良いし、絶縁樹脂C11をあらかじめ
配線パターン2側へ塗布又は設置した後、異方性導電膜
10をその上に塗布又は設置しても良い。また、導電粒
子9のみを絶縁樹脂C11上に付着させ、異方性導電膜
の絶縁樹脂を絶縁樹脂C11で兼ねても良い。次に、基
板1上の配線パターン2と金属突起5とが所定の位置に
来るように位置合わせを行い、半導体素子7と基板1を
圧接する(図16(b))が、以後の実装の手順・メカ
ニズムは、図14の実施例中で説明したものとまったく
同様である。
Next, another mounting method for obtaining the structure of FIG. 5 will be described with reference to FIG. As shown in FIG.
On the wiring pattern 2 on the substrate 1, at least the semiconductor element 3
The insulating resin 3 is mounted on the entire surface opposite to the above, and the anisotropic conductive film 10 is further mounted thereon. Anisotropic conductive film 10
And the insulating resin C11 may be a sheet-like integral member having a two-layer structure in advance, or the insulating resin C11 may be applied or set in advance on the wiring pattern 2 side, and then the anisotropic conductive film 10 may be applied or set thereon. You may. Alternatively, only the conductive particles 9 may be attached to the insulating resin C11, and the insulating resin of the anisotropic conductive film may also serve as the insulating resin C11. Next, positioning is performed so that the wiring pattern 2 on the substrate 1 and the metal protrusion 5 are at predetermined positions, and the semiconductor element 7 and the substrate 1 are pressed into contact with each other (FIG. 16B). The procedure and mechanism are exactly the same as those described in the embodiment of FIG.

【0029】また、図7の構造を得るための半導体装置
の他の実装方法を図17を用いて説明する。図17
(a)のように、基板1上の配線パターン2上、少なく
とも半導体素子3に相対する部分全面に絶縁樹脂3が載
置され、さらにその上、半導体素子7の電極6上に形成
されている金属突起5に相対する部分に異方性導電膜1
0を載置する。異方性導電膜10と絶縁樹脂C11は、
絶縁樹脂C11上に金属突起5に相対する部分にのみに
異方性導電膜10が存在する2層構造のシート状一体の
ものでも良いし、絶縁樹脂C11をあらかじめ配線パタ
ーン2側へ塗布、又は設置した後、異方性導電膜10を
金属突起5に相対する部分のみに印刷、転写、転着等の
方法で絶縁樹脂C11上へ塗布、又は設置しても良い。
また、金属突起5に相対するようなマスク、版で導電粒
子9のみを絶縁樹脂C11上に付着させ、異方性導電膜
の絶縁樹脂を絶縁樹脂C11で兼ねても良い。次に、基
板1上の配線パターン2と金属突起5とが所定の位置に
来るように位置合わせを行い、半導体素子7と基板1を
圧接する(図17(b))が、以後の実装の手順・メカ
ニズムは、図15の実施例中で説明したものとまったく
同様である。
Another method of mounting the semiconductor device to obtain the structure shown in FIG. 7 will be described with reference to FIG. FIG.
As shown in (a), the insulating resin 3 is placed on at least the entire surface of the wiring pattern 2 on the substrate 1 facing the semiconductor element 3, and is formed on the electrode 6 of the semiconductor element 7. Anisotropic conductive film 1 is provided at a portion facing metal protrusion 5.
Place 0. The anisotropic conductive film 10 and the insulating resin C11
The anisotropic conductive film 10 may be present only in the portion facing the metal protrusion 5 on the insulating resin C11. The insulating resin C11 may be a two-layer integrated sheet-like material, or the insulating resin C11 may be applied to the wiring pattern 2 side in advance, or After the installation, the anisotropic conductive film 10 may be applied or installed on the insulating resin C11 only by printing, transferring, transferring, or the like on the portion facing the metal protrusion 5.
Alternatively, only the conductive particles 9 may be adhered to the insulating resin C11 using a mask or a plate facing the metal protrusion 5, and the insulating resin of the anisotropic conductive film may also serve as the insulating resin C11. Next, positioning is performed so that the wiring pattern 2 on the substrate 1 and the metal protrusion 5 are at predetermined positions, and the semiconductor element 7 and the substrate 1 are pressed into contact with each other (FIG. 17B). The procedure and mechanism are exactly the same as those described in the embodiment of FIG.

【0030】以上の実装方法で実装を行った後、半導体
素子の外周部、あるいは半導体素子すべてをさらに絶縁
樹脂で覆い、通電耐湿性を向上させることが多い。
After mounting by the above mounting method, the outer peripheral portion of the semiconductor element or the entire semiconductor element is often further covered with an insulating resin to improve the resistance to current and moisture.

【0031】以上、述べてきたように、本発明の実施例
による半導体装置の実装構造では、半導体素子の能動素
子形成面と配線パターンの間に少なくとも空隙を設ける
構造としたため、以下の効果を有する。
As described above, the mounting structure of the semiconductor device according to the embodiment of the present invention has a structure in which at least a gap is provided between the active element forming surface of the semiconductor element and the wiring pattern. .

【0032】(1)半導体素子能動面とその直下の配線
パターンの間には空隙があり、そこが電気的絶縁層とな
るため、半導体素子能動面とその直下の配線パターンと
の間で電気的短絡は起こらない。
(1) There is a gap between the active surface of the semiconductor element and the wiring pattern immediately therebelow, which serves as an electrical insulating layer. No short circuit occurs.

【0033】(2)半導体素子能動面直下の配線パター
ンの間にも空隙があり、そこが電気的絶縁層となるた
め、配線パターン同士で電気的短絡は起こらない。
(2) There is also a gap between the wiring patterns immediately below the active surface of the semiconductor element, which serves as an electrical insulating layer, so that no electrical short circuit occurs between the wiring patterns.

【0034】上記(1)、(2)の相乗効果により実装
時の電気的短絡が防止できるため、実装歩留まりは向上
する。
Since the electrical short circuit at the time of mounting can be prevented by the synergistic effect of (1) and (2), the mounting yield is improved.

【0035】(3)金属突起部のみに異方性導電膜を存
在させるか、半導体素子能動面全面に薄い異方性導電膜
を存在させる構造としたため、異方性導電膜を仮付けし
た後の位置合わせ時に、半導体素子の位置認識が行いや
すくなる(半導体素子が見やすくなる)ので、位置合わ
せ作業の能率が向上する。
(3) Since the structure is such that the anisotropic conductive film is present only on the metal protrusions or the thin anisotropic conductive film is present on the entire active surface of the semiconductor element, At the time of alignment, the position of the semiconductor element can be easily recognized (the semiconductor element can be easily seen), so that the efficiency of the alignment operation can be improved.

【0036】(4)上記(3)で述べた様に異方性導電
膜の実体積が少なくてすむため、異方性導電膜の接着力
発現に必要なエネルギー量も少なくてすむ。そのため、
半導体素子、基板等には、悪影響を及ぼさない。また、
同上の理由によって、半導体素子と基板にエネルギーを
加える装置も小型化することができ、装置への投資を少
なくすることもできる。
(4) As described in (3) above, since the actual volume of the anisotropic conductive film is small, the amount of energy required for developing the adhesive force of the anisotropic conductive film is also small. for that reason,
It does not adversely affect semiconductor elements, substrates, and the like. Also,
For the same reason, a device for applying energy to a semiconductor element and a substrate can be reduced in size, and investment in the device can be reduced.

【0037】(5)異方性導電膜を半導体素子側へ仮付
けすれば、基板側配線パターンへの異方性導電膜の付着
は最少限で済む。一般的に半導体素子の能動素子形成面
にはパッシベーション膜が形成されており問題は無い
が、配線パターン側にはパッシベーション膜が形成され
ておらず、異方性導電膜中に含まれる不純物イオンによ
る腐蝕が問題となる。しかし、本発明によれば、配線パ
ターンの腐蝕の問題は、実用上問題なくなる。
(5) If the anisotropic conductive film is temporarily attached to the semiconductor element side, adhesion of the anisotropic conductive film to the wiring pattern on the substrate side can be minimized. In general, a passivation film is formed on the active element forming surface of a semiconductor element, and there is no problem. However, no passivation film is formed on the wiring pattern side and the passivation film is formed by impurity ions contained in the anisotropic conductive film. Corrosion is a problem. However, according to the present invention, the problem of corrosion of the wiring pattern is practically no problem.

【0038】さらに本願実施例による半導体素子の実装
構造では、金属突起と配線パターンの部分のみに異方性
導電膜を存在させる構造としたので、次の効果を有す
る。
Further, the mounting structure of the semiconductor element according to the embodiment of the present invention has the following effects because the structure in which the anisotropic conductive film is present only in the portions of the metal protrusions and the wiring patterns.

【0039】(6)導電粒子が、金属突起と配線パター
ンの部分のみに存在するため、半導体素子の能動素子形
成面と配線パターン間、配線パターン同士の電気的短絡
の可能性は、さらに減少する。
(6) Since the conductive particles are present only in the portions of the metal protrusions and the wiring patterns, the possibility of an electrical short circuit between the active element forming surface of the semiconductor element and the wiring patterns and between the wiring patterns is further reduced. .

【0040】(7)半導体素子の能動素子形成面が基板
側から直接見ることができるため、半導体素子と基板と
の位置合わせ作業の能率はさらに向上する。
(7) Since the active element formation surface of the semiconductor element can be directly viewed from the substrate side, the efficiency of the alignment operation between the semiconductor element and the substrate is further improved.

【0041】さらに本発明による半導体素子の実装構造
では、半導体素子の能動素子形成面側全面に金属突起よ
り薄い異方性導電膜を設置する構造としたので、以下の
効果を有する。
Further, in the mounting structure of the semiconductor device according to the present invention, the structure in which the anisotropic conductive film thinner than the metal projection is provided on the entire surface of the semiconductor device on the active device forming surface, has the following effects.

【0042】(8)半導体素子の能動素子形成面へ異方
性導電膜を仮付けする際、位置をあまり気にする必要な
く仮付けできるため、仮付け作業の効率が著しく向上す
る。
(8) When the anisotropic conductive film is temporarily attached to the active element forming surface of the semiconductor element, it is possible to temporarily attach the anisotropic conductive film without paying much attention to the position, so that the efficiency of the temporary attaching operation is significantly improved.

【0043】(9)半導体素子の能動素子形成面全面に
異方性導電膜が存在するため、半導体素子の耐湿性が向
上する。
(9) Since the anisotropic conductive film is present on the entire active element formation surface of the semiconductor element, the moisture resistance of the semiconductor element is improved.

【0044】また、本実施例による半導体素子の実装構
造では、半導体素子の能動素子形成面と配線パターンの
間に少なくとも前述の空隙の代わりに絶縁樹脂を設ける
構造としたため、前述の(1)、(2)と同様の効果を
有するとともに、さらに以下の効果を有する。
In the mounting structure of the semiconductor device according to the present embodiment, at least an insulating resin is provided between the active element forming surface of the semiconductor device and the wiring pattern in place of the above-mentioned gap. It has the same effect as (2) and also has the following effect.

【0045】(10)半導体素子能動素子形成面と、基
板上配線パターンとの間は樹脂の完全な充填構造となる
ため、湿度環境下で湿度の侵入を極端に押さえることが
できる。このため、耐湿環境下での信頼性を向上するこ
とができる。
(10) Since the structure between the active element forming surface of the semiconductor element and the wiring pattern on the substrate is completely filled with resin, it is possible to extremely suppress the invasion of humidity in a humidity environment. For this reason, reliability in a moisture-resistant environment can be improved.

【0046】(11)半導体素子の金属突起と配線パタ
ーンの部分だけではなく、半導体素子能動面とそれに相
対する基板とも、半導体素子と基板の接着に寄与し、接
着面積を増加することができる。このため、半導体素子
と基板との接続信頼性はさらに向上する。
(11) Not only the metal projections and wiring patterns of the semiconductor element but also the active surface of the semiconductor element and the substrate opposed thereto contribute to the adhesion between the semiconductor element and the substrate, and the adhesion area can be increased. Therefore, the connection reliability between the semiconductor element and the substrate is further improved.

【0047】さらに本発明による半導体素子の実装構造
では、半導体素子の金属突起と配線パターンの部分のみ
に異方性導電膜を存在させる構造としたので、次の効果
を有する。
Further, the mounting structure of the semiconductor device according to the present invention has the following effects because the structure in which the anisotropic conductive film is present only in the metal projection and the wiring pattern of the semiconductor device.

【0048】(12)圧接時に、導電粒子が半導体素子
の金属突起と配線パターン部分以外の部分へは、絶縁樹
脂が存在するため、動きにくくなり、より半導体素子の
能動素子形成面と配線パターン間、配線パターン間同士
での電気的短絡の可能性はさらに低下する。
(12) At the time of pressing, the conductive particles are difficult to move due to the presence of the insulating resin in the portions other than the metal protrusions and the wiring pattern portion of the semiconductor element, and the conductive particles are more difficult to move between the active element forming surface of the semiconductor element and the wiring pattern. In addition, the possibility of an electrical short circuit between the wiring patterns is further reduced.

【0049】(13)半導体素子の能動素子形成面とそ
れに対向する基板との間には絶縁樹脂という1材料のみ
しか存在しないため、半導体素子実装の際問題になる材
料の熱膨張係数の差による信頼性低下について、絶縁樹
脂材料の材料特性さえ考えれば良いので、材料選定が容
易に行える。
(13) Since only one material, an insulating resin, exists between the active element forming surface of the semiconductor element and the substrate facing the active element forming surface, the difference in thermal expansion coefficient of the material, which is a problem when mounting the semiconductor element, Since it is only necessary to consider the material characteristics of the insulating resin material with respect to the reduction in reliability, the material can be easily selected.

【0050】さらに、本発明による半導体素子の実装構
造では、半導体素子能動素子形成面全面に異方性導電膜
を存在させ、さらに絶縁樹脂を存在させる構造としたの
で、次の効果を有する。
Further, the mounting structure of the semiconductor element according to the present invention has the following effects because the anisotropic conductive film is present on the entire surface of the active element forming surface of the semiconductor element and the insulating resin is further present.

【0051】(14)異方性導電膜及び絶縁樹脂を仮付
けする際、位置合わせをあまり気にする必要がなく、仮
付け作業の効率が向上する。
(14) When temporarily attaching the anisotropic conductive film and the insulating resin, it is not necessary to pay much attention to the alignment, and the efficiency of the attaching work is improved.

【0052】[0052]

【発明の効果】本願発明の構成によれば、半導体素子能
動面とその直下の配線パターンの間には絶縁性樹脂があ
り、そこが電気的絶縁層となるため、半導体素子能動面
とその直下の配線パターンとの間で電気的短絡は起こら
ない。
According to the structure of the present invention, there is an insulating resin between the active surface of the semiconductor element and the wiring pattern immediately therebelow, which serves as an electrical insulating layer. No electrical short circuit occurs between the wiring patterns.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による半導体装置の実装構造を示す断面
図。
FIG. 1 is a sectional view showing a mounting structure of a semiconductor device according to the present invention.

【図2】従来の半導体装置の実装構造を示す断面図。FIG. 2 is a cross-sectional view showing a mounting structure of a conventional semiconductor device.

【図3】本発明による半導体装置の実装構造を基板側か
ら見た正面図。
FIG. 3 is a front view of the mounting structure of the semiconductor device according to the present invention as viewed from the substrate side.

【図4】本発明による半導体装置の実装構造を示す断面
図。
FIG. 4 is a cross-sectional view showing a mounting structure of a semiconductor device according to the present invention.

【図5】本発明による半導体装置の実装構造を示す断面
図。
FIG. 5 is a cross-sectional view showing a mounting structure of a semiconductor device according to the present invention.

【図6】本発明による半導体装置の実装構造を基板側か
ら見た正面図。
FIG. 6 is a front view of the mounting structure of the semiconductor device according to the present invention as viewed from the substrate side.

【図7】本発明による半導体装置の実装構造を示す断面
図。
FIG. 7 is a sectional view showing a mounting structure of a semiconductor device according to the present invention.

【図8】(a),(b)本発明による半導体装置の実装
方法を示す断面模式図。
8A and 8B are schematic cross-sectional views illustrating a method for mounting a semiconductor device according to the present invention.

【図9】(a),(b)本発明による半導体装置の実装
方法を示す断面模式図。
9A and 9B are schematic cross-sectional views illustrating a method for mounting a semiconductor device according to the present invention.

【図10】(a),(b)本発明による半導体装置の実
装方法を示す断面模式図。
10A and 10B are schematic cross-sectional views illustrating a method for mounting a semiconductor device according to the present invention.

【図11】(a),(b)本発明による半導体装置の実
装方法を示す断面模式図。
11A and 11B are schematic cross-sectional views illustrating a method for mounting a semiconductor device according to the present invention.

【図12】(a),(b)本発明による半導体装置の実
装方法を示す断面模式図。
12A and 12B are schematic cross-sectional views illustrating a method for mounting a semiconductor device according to the present invention.

【図13】(a),(b)本発明による半導体装置の実
装方法を示す断面模式図。
13A and 13B are schematic cross-sectional views illustrating a method for mounting a semiconductor device according to the present invention.

【図14】(a),(b)本発明による半導体装置の実
装方法を示す断面模式図。
14A and 14B are schematic cross-sectional views illustrating a method for mounting a semiconductor device according to the present invention.

【図15】(a),(b)本発明による半導体装置の実
装方法を示す断面模式図。
15A and 15B are schematic cross-sectional views illustrating a method for mounting a semiconductor device according to the present invention.

【図16】(a),(b)本発明による半導体装置の実
装方法を示す断面模式図。
16A and 16B are schematic cross-sectional views illustrating a method for mounting a semiconductor device according to the present invention.

【図17】(a),(b)本発明による半導体装置の実
装方法を示す断面模式図。
17A and 17B are schematic cross-sectional views illustrating a method for mounting a semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

1…基板 2…配線パターン 3…絶縁樹脂A 4…絶縁樹脂B 5…金属突起 6…電極 7…半導体素子 8…空隙 9…導電粒子 10…異方性導電膜 11…絶縁樹脂C 21…ガラス基板 22…ガラス電極 23…絶縁樹脂 24…異方性導電膜 25…バンプ 26…電極 27…ICチップ 28…導電粒子 29…ガラス電極間短絡部 30…ICチップ〜ガラス電極間短絡部 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Wiring pattern 3 ... Insulating resin A 4 ... Insulating resin B 5 ... Metal protrusion 6 ... Electrode 7 ... Semiconductor element 8 ... Void 9 ... Conductive particle 10 ... Anisotropic conductive film 11 ... Insulating resin C21 ... Glass Substrate 22 ... Glass electrode 23 ... Insulating resin 24 ... Anisotropic conductive film 25 ... Bump 26 ... Electrode 27 ... IC chip 28 ... Conductive particle 29 ... Short circuit between glass electrodes 30 ... Short circuit between IC chip and glass electrode

フロントページの続き (56)参考文献 特開 昭60−116157(JP,A) 特開 平1−135344(JP,A) 実開 昭57−35051(JP,U) 実開 昭62−107443(JP,U) 実開 昭62−118266(JP,U) 実開 昭61−156239(JP,U) 実開 昭57−61835(JP,U) 実開 昭63−80844(JP,U) 実開 昭62−47128(JP,U) 実開 昭61−166534(JP,U) (58)調査した分野(Int.Cl.6,DB名) H01L 21/60 311Continuation of front page (56) References JP-A-60-116157 (JP, A) JP-A-1-135344 (JP, A) JP-A 57-35051 (JP, U) JP-A 62-107443 (JP) , U) Actually open 1987-118266 (JP, U) Actually open 1986-156239 (JP, U) Actually open 1987-61835 (JP, U) Actually open 1988-1988 (JP, U) Actually open 62-47128 (JP, U) Japanese Utility Model Showa 61-166534 (JP, U) (58) Field surveyed (Int. Cl. 6 , DB name) H01L 21/60 311

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】シート状の異方性導電と、前記シート状の
異方性導電膜上に設置され、前記シート状の異方性導電
膜と2層構造をなすシート状の絶縁樹脂と、から構成さ
れる異方性導電膜。
1. A sheet-like anisotropic conductive film, and a sheet-like insulating resin provided on the sheet-like anisotropic conductive film and having a two-layer structure with the sheet-like anisotropic conductive film; An anisotropic conductive film composed of:
【請求項2】請求項1記載の異方性導電膜を半導体素子
能動表面に載置する工程、前記半導体素子と、前記半導
体素子が実装される絶縁基板とを位置合わせした後、前
記半導体素子と前記絶縁基板を圧接することにより、前
記半導体素子を前記異方性導電膜を介して前記絶縁基板
に実装する工程、を有する半導体素子の実装方法。
2. A step of placing the anisotropic conductive film according to claim 1 on an active surface of a semiconductor device, and after positioning the semiconductor device and an insulating substrate on which the semiconductor device is mounted, the semiconductor device And mounting the semiconductor element on the insulating substrate via the anisotropic conductive film by press-contacting the insulating substrate with the insulating substrate.
【請求項3】請求項1記載の異方性導電膜を絶縁基板に
載置する工程、 前記絶縁基板と、前記絶縁基板に実装される半導体素子
とを位置合わせした後、前記半導体素子と前記絶縁基板
とを圧接することにより、前記半導体素子を前記異方性
導電膜を介して前記絶縁基板に実装する工程、を有する
半導体素子の実装方法。
3. The step of mounting the anisotropic conductive film according to claim 1, on an insulating substrate, after aligning the insulating substrate and a semiconductor element mounted on the insulating substrate, A method of mounting the semiconductor element on the insulating substrate via the anisotropic conductive film by pressing the insulating element against the insulating substrate.
JP9272781A 1988-04-20 1997-10-06 Anisotropic conductive film and method for mounting semiconductor device using anisotropic conductive film Expired - Lifetime JP2820148B2 (en)

Priority Applications (1)

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JP9272781A JP2820148B2 (en) 1988-04-20 1997-10-06 Anisotropic conductive film and method for mounting semiconductor device using anisotropic conductive film

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP9763588 1988-04-20
JP63-97635 1988-04-20
JP9272781A JP2820148B2 (en) 1988-04-20 1997-10-06 Anisotropic conductive film and method for mounting semiconductor device using anisotropic conductive film

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP1011613A Division JPH0234951A (en) 1988-04-20 1989-01-20 Mounting structure for semiconductor device

Publications (2)

Publication Number Publication Date
JPH1092876A JPH1092876A (en) 1998-04-10
JP2820148B2 true JP2820148B2 (en) 1998-11-05

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Publication number Priority date Publication date Assignee Title
JP5310252B2 (en) * 2009-05-19 2013-10-09 パナソニック株式会社 Electronic component mounting method and electronic component mounting structure

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