JP2807714B2 - Memory-type liquid crystal electro-optical device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a memory-type electro-optical conversion device using a bistable state of a ferroelectric liquid crystal. [Summary of the Invention] The present invention relates to a memory electrode liquid crystal electro-optical device of a matrix electrode arrangement type utilizing a bistable state of a ferroelectric liquid crystal,
After writing the bistable state line-sequentially by using the AC bias averaging method, the signal level and the scanning electrode are maintained at the same potential by using the voltage level used for writing, and the memory function is provided by the logic circuit control. Therefore, an extremely compact drive circuit configuration could be obtained. [Prior art] Conventionally, in a memory-type liquid crystal electro-optical device using a bistable alignment of a ferroelectric liquid crystal (for example, a chiral smectic C liquid crystal, hereinafter referred to as SmC ^* ), a pair of electrodes sandwiching an SmC ^* thin film are placed at the same potential. A driving method for maintaining the memory state by holding the data in a memory has been known. For example, JP-A-61-
No. 18931. FIG. 2 shows the structure of a panel (hereinafter referred to as a liquid crystal panel) of a conventional memory-type liquid crystal electro-optical device. Reference numerals 1 and 1 denote a pair of substrates arranged to face each other. 2 is S sandwiched between substrates 1 and 1
mC ^* Thin film. Reference numerals 3 and 3 denote uniaxial and random horizontal alignment films existing at the interface between the substrate 1 and the SmC ^* thin film 2, and realize a bistable state of liquid crystal molecules. The major axis of the liquid crystal molecules (hereinafter referred to as molecular axis) is oriented horizontally with respect to the substrate and forms a layer.
When this is observed from above, the liquid crystal molecules are divided into two domains. In the first domain, the molecular axis is inclined by + θ with respect to the normal 4 of the layer. This is the first stable state 5. The spontaneous polarization 7 of the liquid crystal molecules points upward. In the second domain, the molecular axis is inclined by -θ with respect to the normal 4 of the layer. This is the second stable state 6. Spontaneous polarization 7 points downward. Using the fact that the directions of the spontaneous polarization 7 are opposite to each other, one of the bistable states is selected by positive and negative DC pulses. Reference numerals 8 and 8 denote a pair of polarizing plates which are opposed to each other with their polarization axes orthogonal to each other, and optically distinguish between a first stable state and a second stable state by birefringence. For example, the first stable state is converted to a light passing state (hereinafter, referred to as white), and the second stable state is converted to a light blocking state (hereinafter, referred to as black). Reference numerals 9 and 10 denote matrix electrodes for applying a driving voltage to the SmC ^* thin film 2, and 9 denotes a scanning electrode and 10 denotes a signal electrode as shown in FIG. FIG. 4 shows a driving waveform applied to one matrix pixel (hereinafter, referred to as a dot) in line-sequential driving using the AC bias averaging method. Positive / negative having a peak value equal to or greater than a threshold value during the selection period in the first frame (reference to signal electrode 9)
Are continuously applied. The liquid crystal molecules are aligned in the second stable state by the positive pulse, and are switched by the subsequent negative pulse to align in the first stable state. This state is maintained during the non-selection period. This is because the peak value of the pulse applied during the non-selection period is equal to or less than the threshold. Therefore, white in the first stable state is written in the first frame. Subsequently, black is written in the second frame because the polarity of the pulse is reversed. After writing in white or black based on the video data, both electrodes are kept at the same potential, and the written state is preserved. This is because it has memory properties. [Problems to be Solved by the Invention] However, the above-mentioned prior art document does not show a specific circuit configuration for controlling the matrix electrodes to the same potential during the memory period, and thus has been simple and effective until now. Memory drive was not performed. [Means for Solving the Problems] It is an object of the present invention to provide a specific circuit configuration for controlling the above-mentioned matrix electrodes at the same potential. That is, in a matrix-type liquid crystal electro-optical device in which white and black are written line-sequentially using the bistable state of SmC ^* liquid crystal, writing of the bistable state is performed by using an AC bias averaging method, and writing is performed. A part of the applied voltage is used as it is, and the matrix electrode is set to the same potential only by the gate control by the logic circuit, thereby realizing the memory state. [Example] Hereinafter, a specific driving circuit will be described in detail with reference to the drawings. FIG. 5 shows an example of a waveform applied to a matrix electrode when white writing is performed by line-sequential driving using the 1/5 bias averaging method. φ _X is the selection signal electrode waveform in the first half V _S ,
The latter half V _DD is applied. _X is a non-selection signal electrode waveform to which the first half V ₂ and the second half V ₃ are applied. phi _Y first half V _DD, late V ₅ is applied in the waveforms applied to the selected scanning electrodes. _Y is half V ₄ in the waveforms applied to the non-selected scanning electrode, the second half V ₁ is applied. This is shown in the output truth table of the signal electrode (hereinafter, referred to as a segment) and the output truth table of the scan electrode (hereinafter, referred to as a common) as follows. Here, DATA is a video signal input to the drive circuit, H indicates segment selection, and L indicates segment non-selection. FLM
Is the scanning signal input to the drive circuit, H is the common selection,
L indicates common non-selection. DF is an alternating signal input to the drive circuit, H is the first half of the applied voltage waveform basic unit,
L also indicates the latter half. In example segment output truth table, DATA is the first half of V ₅ in other words selected segment at the H late V _DD is applied. This is the phi _X of Figure 5. Looking at both truth tables, the V _DD potential is commonly used for segment and common. Therefore, the DATA signal input to the segment driver is forcibly set to H by logic control,
Let the DF signal be L. Then all segments have V _DD
Is applied. FLM input to common driver at the same time
The signal is forcibly set to H by logic control, and the DF signal is set to H. Then, V _DD is applied to all the segments.
As a result, both electrodes are forcibly connected to the V _DD potential. FIG. 1A shows a drive circuit for forcibly connecting the above-mentioned matrix electrode to _VDD , which will be described in conjunction with the time chart of FIG. Reference numeral 11 denotes a segment driver for driving the segments of the LC panel 12. Inputs the potential level V _DD ~V ₅ necessary, synthetic and outputs the phi _X and _X on the basis of the DATA and DF signal. CL ₂ is a high-speed clock, CL ₁ to fix serial DATA in parallel DATA is a clock that controls the sequential timing line. Latching outputs parallel DATA in synchronization with the CL _1. Reference numeral 13 denotes a common driver that drives the common of the LC panel 12. Inputs the potential level V _DD ~V ₅ necessary, phi _Y and _Y on the basis of the FLM and DF signal
And output. CL ₁ is a clock that controls the sequential timing line. Now, it is assumed that the OPEN signal has changed from L to H. The OPEN signal is a signal for controlling the drive circuit to shift from a write operation to a memory operation. When the signal OPEN becomes H, the segment driver 11 is inputted via the OR gate 14.
DATA becomes H forcibly. DF is forcibly set to L via the inverter 15 and the AND gate 16. Therefore, as is apparent from the segment output truth table, all the segments of the LC panel 12 are at the V _DD level. When the OPEN signal goes high, FLM input to the common driver 13 via the OR gate 17 is forced high. DF is forcibly set to H via the OR gate 18. Therefore, as is apparent from the common output truth table, all the commons of the LC panel 12 are at the V _DD level. Segment and common is the memory state is maintained to V _DD same potential is maintained as described above. The circuit shown in FIG. 1 (B) is another embodiment. As is apparent from both the truth table mentioned above, V ₅ potential is also used commonly in the segment and common. Therefore, in the present embodiment, the DATA that OPEN is input to the segment driver 11 When turned H H, the DF as H, to output a V _5, V ₅ and the FLM to be input to the common driver 13 H, the DF to L Is output. Other operations are the same as those of the circuit shown in FIG. [Effects of the Invention] According to the present invention, in a matrix-type memory-type electro-optical converter using a bistable state of SmC ^* , after writing a bistable state line-sequentially using an AC bias averaging method, With the circuit control, the potential applied to the segment electrode and the common electrode used for writing was applied to the other electrode, and the potential applied to the other electrode was used as the potential for holding writing. There was no need to prepare a new power supply for the device, and an extremely compact drive circuit could be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (A) and (B) are LC panel drive circuit diagrams, FIG. 2 is a perspective view of a conventional liquid crystal panel, FIG. 4 is a conventional driving waveform diagram, FIG. 5 is a waveform diagram applied to a segment and a common, and FIG.
FIG. 4 is a time chart of the drive circuit shown in FIGS. 11 Segment driver 12 LC panel 13 Common driver 14, 15, 16, 17, 18 Logic circuit

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kokichi Ito 6-31-1, Kameido, Koto-ku, Tokyo Seiko Electronic Industry Co., Ltd. (56) References JP-A-62-218944 (JP, A) 59-121391 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/133 G09G 3/36 G09G 3/18

Claims (1)

(57) [Claims] A ferroelectric liquid crystal thin film, an alignment film in contact with the thin film and realizing bistable alignment of liquid crystal molecules, a member for converting the bistable alignment state to optically bright and dark, and a voltage for switching the bistable state to the thin film. A memory liquid crystal electro-optical device comprising a liquid crystal panel comprising electrodes arranged in a matrix to be applied and a drive circuit for writing a bistable state line-sequentially by an AC bias averaging method. The writing state is maintained by applying a common potential to the scanning electrode and the signal electrode among the potentials applied to the scanning electrode and the signal electrode for the writing. A liquid crystal electro-optical device having a memory function.