JPH0553537A - Ferroelectric liquid crystal display device and driving method thereof - Google Patents

Abstract

PURPOSE:To allow the partial erasing or writing display of ferroelectric liquid crystal display picture elements by discriminating the erasing, holding or writing of the display picture elements, thereby supplying an erasing, holding or writing driving voltage to the corresponding display picture elements. CONSTITUTION:A discriminating circuit 4 for comparing and discriminating the display data of a 1st memory circuit 1 and a 2nd memory circuit 2 is provided. The erasing data E which is the output signal of the discriminating circuit and the writing data W are inputted to an erasing data processing circuit 5 and a writing data processing circuit 6. The signals of the erasing data processing circuit 5 and the writing data processing circuit are alternately switched and outputted, by which the erasing and writing display operations can be alternately executed. Then, the partial erasing and writing display is made possible and, therefore, a current consumption decreases. Further, the generation of flickers in the large-sized display device is obviated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a flat type electro-optical display device, in particular, a matrix type ferroelectric liquid crystal (for example, smectic liquid crystal) or a short pitch bistable ferroelectric liquid crystal (SBF) material. The present invention relates to a liquid crystal display device.

[0002]

2. Description of the Related Art FIG. 5 is a diagram for explaining the structure of a ferroelectric liquid crystal panel. FIG. 6 shows an example of drive waveforms for ON / OFF display of the ferroelectric liquid crystal panel of FIG.
In FIG. 5, 51a and 51b are a pair of transparent glass substrates. Reference numerals 52a and 52b are rubbing films of a uniaxial horizontal alignment film (for example, a polyimide material) provided on the inner surfaces of the substrates 51a and 51b. The rubbing directions of the pair of alignment films are substantially parallel. Reference numeral 53 denotes a ferroelectric liquid crystal, which has spontaneous polarization in a direction orthogonal to the long axis of liquid crystal molecules (hereinafter referred to as molecular axis). Further, a material having a negative dielectric anisotropy Δε at a certain frequency or higher is selected. The fact that Δε <0 means that induced polarization is generated in a direction orthogonal to the molecular axis by an external electric field in a constant frequency region. The molecules of the ferroelectric liquid crystal 53 are sandwiched between the substrates 51a and 51b, and are horizontally aligned as shown in the figure due to the influence of the alignment films 52a and 52b, and form a layer. 54 and 55
Is a pair of electrodes sandwiching the ferroelectric liquid crystal 53 thin film and facing each other for applying a drive voltage.

In the drive waveform shown in FIG. 6, the electrode 54
A first DC pulse having a positive polarity and having a ground potential is applied between the electrodes 54 and 55. As a result, the molecules are oriented so that the spontaneous polarization 56 of the liquid crystal molecules is aligned in a vertical position toward the electrode 54. This is the first stable state 57, whose molecular axis is tilted by + θ with respect to the normal line 58 of the ferroelectric liquid crystal layer. Next, when an AC pulse is applied, dielectric polarization occurs in the direction orthogonal to the molecular axis due to the negative dielectric anisotropy, and the first stable state is maintained and fixed by the dielectric torque. When a second DC pulse having a further negative polarity is applied between the electrodes 54 and 55, the liquid crystal molecules respond and the spontaneous polarization 56 is vertically aligned with the electrode 55. This is the second stable state 59, which is the position where the molecular axis is tilted by −θ with respect to the normal line 58 of the ferroelectric liquid crystal layer. After that, the second stable state is maintained by the application of the AC pulse. That is, the first stable state is written by the positive DC pulse exceeding the threshold value, and thereafter, the first stable state is maintained by the memory property of the ferroelectric liquid crystal.

Next, the second stable state is written by the negative DC pulse exceeding the threshold value, and thereafter, the second stable state is held. In FIG. 5, reference numerals 60a and 60b denote a pair of polarizing plates whose polarization axes direct light to each other. The birefringence is used to optically divide the liquid crystal domain in the first stable state and the liquid crystal domain in the second stable state. To distinguish. For example, the first stable state 57 is identified as a light blocking state (writing state, hereinafter black display) and the second stable state 59 is identified as a light transmitting state (erasing state, hereinafter white display).

FIG. 4 is a diagram for explaining an example of a conventional drive waveform when the ferroelectric liquid crystal is formed in a matrix structure. In FIG. 4, LP is a timing signal for scanning the common electrode (scanning electrode), and this cycle indicates one common electrode scanning drive time. M is a polarity reversal signal for reversing the polarity of the drive voltage for AC driving the ferroelectric liquid crystal. Y is a common electrode drive voltage applied to the common electrode. XE is a segment electrode drive voltage when the display is erased (white display). XW is
This is the segment electrode drive voltage when writing a display (black display). (Y-XW) is a drive voltage waveform applied between the ferroelectric liquid crystals in the case of erase display. In addition, (Y-
XW) is a drive voltage waveform applied between the ferroelectric liquid crystals in the writing display. As described above, in the case of the ferroelectric liquid crystal having the matrix structure, the period of one horizontal scanning period is divided into substantially equal parts, and the erasing voltage is applied to the first half of the period to set the second stable state. Then, in the case of erasing display, as shown in (Y-XE), a driving voltage that is equal to or less than the threshold voltage of the ferroelectric liquid crystal is applied during the latter half period to a degree that does not change the second stable state. Suppress to. Also, when rewriting and displaying,
As shown in (Y-XW), in the latter half period, a driving voltage having a polarity opposite to the threshold voltage of the ferroelectric liquid crystal is applied and the second voltage is applied.
From the stable state of No. 1 to the first stable state.

[0006]

However, in the case of the conventional driving method, the erase driving voltage is uniformly applied to the ferroelectric liquid crystal in the region where the stable state of display does not change in the first half of the horizontal scanning period. It is performed over the entire number of scan lines. Therefore, all display pixels should be at least 1 for each frame.
The turn is a method in which an erase drive voltage is applied. Therefore, the consumption current consumed by the ferroelectric liquid crystal becomes so large that it cannot be ignored, which has been a great obstacle to application as a portable information device. Further, in the case of displaying on a large screen, erasing and writing times are shortened, and it becomes impossible to operate unless the driving voltage is set high, and there are problems such as flicker becoming conspicuous. Therefore, an object of the present invention is to provide an erasing drive voltage or a write drive voltage only to display pixels whose display changes, and to use only a holding voltage when the display does not change, in order to solve such a conventional problem. By doing so, it is intended to reduce the current consumption, extend the battery life of the portable information device, and obtain stable display quality without flicker even in a large-scale display device.

[0007]

In order to solve the above-mentioned problems, the present invention has a first memory circuit for storing display data processed by a computer, which has two memory circuits for storing display data. And the output signal of the second storage circuit for storing new display data newly processed at the next timing are input to the determination circuit for comparing / determining each other. Then, it is determined whether the corresponding display pixel is turned on / off or the previous display state is retained, and the write data process and the erase data process are performed, and the output signal is input to the drive circuit of the display device. Then, a writing drive voltage, an erasing drive voltage or a holding voltage is applied to the ferroelectric liquid crystal to cause the corresponding display pixel to display.

[0008]

As described above, the ferroelectric liquid crystal display device having the control circuit of the present invention is limited to the display pixels which are currently changing with respect to the past (for example, one frame before) display data. It becomes possible to execute partial writing and erasing display of display pixels.

[0009]

EXAMPLES The present invention will be described below based on examples. FIG. 1 is a circuit diagram showing an embodiment of the present invention. Figure 1
, 1 and 2 are first and second storage circuits (RA) for storing display data processed by the computer.
M1, 2). Reference numeral 4 is a discriminating circuit for comparing and discriminating the outputs of the first and second storage circuits 1 and 2.
Reference numeral 5 is an erase data processing circuit and a write data processing circuit for processing the output signals E and W of the discrimination circuit and outputting erase data and write data.
3 is the first and second memory circuits 1 and 2, the discrimination circuit 4,
Timing signal for generating a timing signal required for operating the erase data processing circuit 5 and the write data processing circuit 6 and a timing signal required for operating a drive circuit incorporated in the ferroelectric liquid crystal display device. It is a generation circuit. DIN is a computer processed display data signal. Vsync is a vertical synchronizing signal. Hs
yc is a horizontal synchronizing signal. CLK is a clock signal. It is configured as described above.

Next, the operation of the present invention will be described. Computer-processed display data DIN for the Nth frame
Are stored in the first storage circuit 1 at the timing of the write signal W1 of the timing signal generation circuit 3. next,
The computer-processed display data DIN of the (N + 1) th frame is stored in the second storage circuit 2 at the timing of the write signal W2 of the timing signal generation circuit 3. Furthermore, the (N + 2) th frame is stored in the first storage circuit 1, so that new display data is always stored in the storage circuits 1 and 2 in order. The memory circuits 1 and 2 are sequentially read from the same address by the read signal R from the timing signal generating circuit 3 which is output after the timing of the write signal W1 or W2.

Then, the respective output signals A and B are inputted to the discrimination circuit 4. The discrimination circuit 4 includes the storage circuits 1, 2
Of the output signals A and B are compared to detect the difference between the display data of the past and the present (for example, N frame and N + 1 frame), and whether the difference is the data for erasing the display pixel or the data to be written. To determine. In the case of data to be erased, the erase data signal E is output to the erase data processing circuit 5. In the case of data to be written, the write data signal W is output to the write data processing circuit 6. The gate signal G, which is a timing signal from the timing signal generation circuit 3, is switched between the parallel output signals (8 bits) A and B of the storage circuits 1 and 2 alternately for each frame and is input to the determination circuit. The erase data processing circuit 5 and the write data processing circuit 6 alternately output their respective output signals through the OR circuit in response to the timing signal generated by the output enable signal OE of the timing signal generating circuit 3 to output the erase / write data signal EWD. Output to the drive circuit built in the dielectric liquid crystal display device.

Because the output enable signal OE
Is inverted by the inverter circuit 7 to control the write data processing circuit, so that the outputs of the erase data processing circuit 5 and the write data processing circuit 6 alternately activate the output operation. When the output enable signal OE uses an output signal obtained by dividing the vertical synchronizing signal Vsyc by 1/2 by a flip-flop circuit, the outputs of the erase data processing circuit 5 and the write data processing circuit 6 are alternated for each frame. It is switched to and output. When a pulse output with a duty ratio of 50% is used by using a monostable multivibrator circuit with the vertical synchronizing signal Hsyc as an input, the outputs of the erase data processing circuit 5 and the write data processing circuit 6 are one horizontal scanning period. The output is switched alternately every half period. The timing signal generating circuit 3 also includes a frame signal FLM necessary for operating the drive circuit of the ferroelectric liquid crystal display device, an AC control signal M for inverting the polarity of the drive voltage and AC drive, and a scanning operation. Then, a latch signal LP for latching data for one line and a shift clock signal SK for shifting the erase / write data are output to perform a display operation.

FIG. 2 is a circuit diagram showing an embodiment of a 1-bit discrimination circuit of parallel data in order to briefly explain the operation of the discrimination circuit. In FIG. 2, 21-2
Reference numeral 4 is a 1-transmission gate circuit for switching the input signals A1 and B1 by a gate signal G and outputting the same. Two
Reference numerals 6 and 27 denote AND circuits that output the erase data E1 and the write data W1, respectively. Reference numerals 28 and 29 are an erase data processing circuit and a write data processing circuit for latching the erase data E1 and the write data W1 and outputting display data by the output enable signal OE.

Next, the operation of FIG. 2 will be described. If the data of the corresponding display pixel is "1, 0, 0, 1," for each frame.
Consider the case where it changes to 0, 1, 1, 0 ...
It is assumed that the corresponding display pixel performs an erase display, an erase display (holding operation), a write display, an erase display, a write display, a write display (holding operation), an erase display. The data shown in Table 1 is stored in each of the storage circuits 1 and 2.

[0015]

[Table 1]

The write data of the memory circuit in Table 1 is read by the read signal R and input to FIGS. 2A1 and 2A1. The transmission signals 21 to 24 are controlled by the gate signal G, and the signals at the P and Q terminals are the signals shown in Table 2.

[0017]

[Table 2]

The display data of Table 2 is the AND circuit 2
6, 27 are input to the inverter circuit, and the output erase data E1 and write data W1 thereof become the output signals shown in Table 3 to execute the erase, hold and write display operations.

[0019]

[Table 3]

Erase data E1 and write data W1
Are respectively input to the latch circuits 28 and 29 and temporarily latched. It can be understood that the display operation shown in Table 3 is executed by switching the output enable signal OE alternately and outputting the erase / write signal EWD1 via the OR circuit 30. FIG. 3 is a drive waveform diagram showing an embodiment of 1/5 bias drive for executing an erase or write operation for each frame as the drive system of the present invention. In FIG. 3, FLM is a frame signal of a timing signal for driving the display device. LP is a latch signal for shifting the scan line. M is 1
This is an alternating current control signal for inverting the polarity of the drive signal for each scanning line. C1 is a common electrode drive voltage. SE
Is a segment drive voltage for erasing the corresponding display pixel. SW is a write drive voltage for writing the corresponding display pixel. From the above-mentioned drive voltage waveforms, (C1-SE) is the erase voltage waveform applied between the ferroelectric liquid crystals. Further, (C1-SW) is a write voltage waveform applied between the ferroelectric liquid crystals.

When the display pixel is erased (C1-E1)
In the first frame, a selection voltage in the − direction exceeding the threshold value is applied between the ferroelectric liquid crystals in the first frame, and only a voltage in the + direction below the threshold value is applied in the next frame, so that the erased state is maintained. .. Also, when writing a display pixel (C1
-W1) holds the previous state because a voltage below the threshold value in the-direction is applied between the ferroelectric liquid crystals in the first frame, but the selection voltage in the + direction is maintained in the next frame. Since the voltage is applied between the ferroelectric liquid crystals, the writing display is executed.

FIG. 7 shows, as another driving method, 1 / for executing an erasing or writing operation within one scanning period.
It is a drive waveform diagram showing an example of 5-bias drive. Figure 7
In the above, LP is a latch signal for shifting the scan line. M is an AC control signal for inverting the polarity of the drive signal within one scanning period. C1 is a common electrode drive voltage. SE is a segment drive voltage for erasing the corresponding display pixel. SW is a write drive voltage for writing the corresponding display pixel.

From the drive voltage waveforms described above,
(C1-SE) is an erase voltage waveform applied between the ferroelectric liquid crystals. Further, (C1-SW) is a write voltage waveform applied between the ferroelectric liquid crystals. In the case of erasing the display pixel (C1-E1), a negative-direction selection voltage exceeding the threshold value is applied between the ferroelectric liquid crystals in the first half period of one scanning period, and the threshold voltage is applied in the second half period of the scanning period. Since only the voltage in the + direction below the value is applied, the display pixel is erased and its state is maintained. In addition, in the case of writing the display pixel (C1-W1), since the voltage equal to or lower than the threshold value in the-direction is applied between the ferroelectric liquid crystals in the first half period of one scanning period, the previous state is maintained. However, since the + direction selection voltage is applied between the ferroelectric liquid crystals in the latter half of the scanning period, the writing display is executed.

In the description of FIGS. 1 and 2 of the present invention, one bit of display data has been described for simplification of description, but the discrimination circuit 5 and the erased data processing circuit 5,
Even if the write data processing circuit 6 has a parallel configuration, it goes without saying that it is included in the technical scope of the present invention. Further, the liquid crystal material is not limited to the smectic liquid crystal material, but is applied to other ferroelectric liquid crystal materials having bistability.

[0025]

As described above, the present invention describes the control circuit and the driving system of the ferroelectric liquid crystal display device. According to the present invention, the partial change is achieved by detecting and judging the change of the display pixel. Therefore, erase and write display can be performed extremely easily. Therefore, regardless of the change in the display pixel, which has been a problem in the past, the method of once deleting all the display pixels and then writing only the necessary display pixels is not used. It has become possible to use it for information devices for business. Further, according to the present invention, since the erasing / writing operation is partially executed and the rest is displayed by utilizing the memory property which is the characteristic of the ferroelectric liquid crystal, the frame frequency is set high as in the conventional case. Even if it does not exist, flicker does not occur, and moreover, it has a great effect that stable display quality can be obtained even in a large-scale display device larger than the conventional one.

[Brief description of drawings]

FIG. 1 is a control circuit diagram showing an embodiment of the present invention.

FIG. 2 is a discrimination circuit diagram showing an embodiment of the present invention.

FIG. 3 is a drive waveform diagram for explaining an example of a drive system of the present invention.

FIG. 4 is a drive waveform diagram of a conventional drive method.

FIG. 5 is a diagram showing a structure of a ferroelectric liquid crystal display device.

FIG. 6 is a drive waveform diagram for explaining a display operation.

FIG. 7 is a drive waveform chart for explaining another embodiment of the drive system of the present invention.

[Explanation of symbols]

1, 2 Memory circuit 1, Memory circuit 2 (RAM1, RAM
2) 3 Timing signal generating circuit 4 Discrimination circuit 5 Erase data processing circuit 6 Write data processing circuit 21-24 Transmission gate circuit 26, 27 AND circuit 28, 29 Latch circuit

Claims (6)

[Claims] 1. A ferroelectric liquid crystal is interposed in a gap between a first electrode group and a second electrode group, and their intersections are arranged in a matrix.
In a ferroelectric liquid crystal display device including a drive circuit for driving the first electrode group and the second electrode group, at least a first storage circuit for storing display data of the Nth frame and the Nth frame. Storage means having a second storage circuit for storing display data of different frames; a determination circuit for determining that the read outputs of the first and second storage circuits have changed; Erase data processing circuit for processing a first output, write data processing circuit for processing a second output of the discrimination circuit, the first and second memory circuits, erase data processing circuit, write data processing It is composed of a timing signal generation circuit for supplying a timing signal to the circuit, and the output of the erase data processing circuit and the write data processing circuit is alternately switched to display data. Ferroelectric liquid crystal display device characterized by having a control circuit for outputting to said driving circuit. 2. The ferroelectric liquid crystal display device according to claim 1, wherein the outputs of the erase data processing circuit and the write data processing circuit are alternately switched for each display frame and output to the drive circuit. Ferroelectric liquid crystal display device having a control circuit. 3. The ferroelectric liquid crystal display device according to claim 1, wherein the outputs of the erase data processing circuit and the write data processing circuit alternate during one horizontal drive electrode period of display divided into a first half and a second half. A ferroelectric liquid crystal display device comprising a control circuit which is switched and outputs to the drive circuit. 4. The switching circuit and the switching circuit for switching the output signals of the first and second storage circuits at least every frame cycle in the determination circuit of the ferroelectric liquid crystal display device according to claim 1. 2. A ferroelectric liquid crystal display device comprising a comparison circuit for comparing the output signals of. 5. A first electrode group for scanning display and a second electrode group for driving according to display data are arranged in a matrix form, and the intersections thereof are used as display pixels, and the first electrode group and the second electrode group are arranged.
In a driving method of a ferroelectric liquid crystal display device, a ferroelectric liquid crystal is interposed in a gap between electrode groups, and a driving circuit for supplying a driving voltage to the first and second electrode groups to display an intersection thereof is provided. The driving circuit includes an erasing frame period for supplying an erasing driving voltage for erasing the ferroelectric liquid crystal or a holding voltage for holding, and a writing driving voltage for writing the ferroelectric liquid crystal or a holding voltage for holding. A driving method of a ferroelectric liquid crystal display device, comprising: a write frame period for supplying a voltage, and supplying a drive voltage for partially erasing, holding or writing the corresponding display pixel in the corresponding frame period. 6. A first electrode group for scanning display and a second electrode group for driving according to display data are arranged in a matrix form, and the intersections thereof are used as display pixels, and the first electrode group and the second electrode group are arranged.
In a driving method of a ferroelectric liquid crystal display device, a ferroelectric liquid crystal is interposed in a gap between electrode groups, and a driving circuit for supplying a driving voltage to the first and second electrode groups to display an intersection thereof is provided. The driving circuit has an erasing period for supplying an erasing driving voltage and a holding voltage for erasing the ferroelectric liquid crystal, and a writing period for supplying a writing driving voltage and a holding voltage for writing the ferroelectric liquid crystal, The erase period, and
A driving method of a ferroelectric liquid crystal display device, characterized in that at least one corresponding horizontal drive period is performed during a write period, and a corresponding display pixel is partially erased, held or supplied with a write drive voltage.