JP2806729B2 - Package for storing semiconductor elements - Google Patents
Package for storing semiconductor elementsInfo
- Publication number
- JP2806729B2 JP2806729B2 JP5068100A JP6810093A JP2806729B2 JP 2806729 B2 JP2806729 B2 JP 2806729B2 JP 5068100 A JP5068100 A JP 5068100A JP 6810093 A JP6810093 A JP 6810093A JP 2806729 B2 JP2806729 B2 JP 2806729B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- power supply
- lead terminal
- resin
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device.
【０００２】[0002]
【従来の技術】従来、コンピューター等の情報処理装置
には半導体素子収納用パッケージ内に半導体素子を気密
に収容して成る半導体装置が実装されている。2. Description of the Related Art Conventionally, a semiconductor device having a semiconductor element hermetically housed in a semiconductor element housing package is mounted on an information processing apparatus such as a computer.
【０００３】かかる従来の半導体装置に使用される半導
体素子収納用パッケージは、図２に示すように上面に半
導体素子11が搭載される搭載部12a を有するコバール金
属(鉄ーニッケルーコバルト合金) や42アロイ( 鉄ーニ
ッケル合金) 等の金属材料から成る基体12と、半導体素
子11の電源電極、接地電極、信号電極が接続される複数
個の外部リード端子13と、エポキシ樹脂等の熱硬化樹脂
から成る被覆材14とから構成されており、基体12の半導
体素子搭載部12a 上に半導体素子11を銀ペースト等のロ
ウ材を介して搭載固定するとともに半導体素子11の各電
極( 電源電極、接地電極及び信号電極) を外部リード端
子13にボンディングワイヤ15を介して電気的に接続し、
しかる後、前記半導体素子11、基体12及び外部リード端
子13の一部を被覆材14で被覆することによって製品とし
ての半導体装置となる。[0003] As shown in FIG. 2, a package for accommodating a semiconductor element used in such a conventional semiconductor device includes a Kovar metal (iron-nickel-cobalt alloy) having a mounting portion 12a on which a semiconductor element 11 is mounted. 42 A base 12 made of a metal material such as an alloy (iron-nickel alloy), a plurality of external lead terminals 13 to which a power electrode, a ground electrode, and a signal electrode of the semiconductor element 11 are connected, and a thermosetting resin such as an epoxy resin. The semiconductor element 11 is mounted and fixed on the semiconductor element mounting portion 12a of the base 12 via a brazing material such as silver paste, and each electrode of the semiconductor element 11 (power supply electrode, ground electrode). And the signal electrodes) are electrically connected to the external lead terminals 13 via the bonding wires 15,
Thereafter, a part of the semiconductor element 11, the base 12, and the external lead terminals 13 is covered with a covering material 14, thereby obtaining a semiconductor device as a product.
【０００４】しかしながら、この従来の半導体素子収納
用パッケージは半導体素子11の固定される基体12がコバ
ール金属や42アロイ等から成り、その熱伝導率が約18W/
m ・K 程度と低いこと及び半導体素子11を被覆する被覆
材14がエポキシ樹脂等の熱硬化樹脂から成り、その熱伝
導率が0.4W/m・K 程度と低いこと等から半導体素子11が
作動時に多量の熱を発生した場合、前記半導体素子11の
発する熱は該半導体素子11の周辺に蓄積され、その結
果、半導体素子11は該半導体素子11自身の発する熱によ
って高温となり、半導体素子11に熱破壊を起こしたり、
特性に変化をきたし、誤動作したりするという欠点を有
していた。However, in this conventional package for housing a semiconductor element, the base 12 to which the semiconductor element 11 is fixed is made of Kovar metal or 42 alloy, and has a thermal conductivity of about 18 W /
The semiconductor element 11 is activated because the coating material 14 covering the semiconductor element 11 is made of a thermosetting resin such as an epoxy resin and its thermal conductivity is as low as about 0.4 W / mK. When a large amount of heat is sometimes generated, the heat generated by the semiconductor element 11 is accumulated around the semiconductor element 11, and as a result, the temperature of the semiconductor element 11 becomes high due to the heat generated by the semiconductor element 11 itself. Causing thermal destruction,
It has the disadvantage that the characteristics change and malfunctions occur.
【０００５】また近時、半導体素子11は高密度化、高集
積化が急激に進み、電極の数が大幅に増大してきてお
り、該半導体素子11の各電極( 電源電極、接地電極及び
信号電極) に接続される外部リード端子13の数も急激に
増大し、各外部リード端子13はその線幅が極めて細く、
インダクタンスが15nH程度の高いものとなってきてい
る。そのためこの外部リード端子13を介して半導体素子
11に駆動のための電力及び電気信号を供給した場合、外
部リード端子13のインダクタンスが高いことに起因して
半導体素子11への供給電源電圧に変動が生じると大きな
ノイズが発生し、これが電気信号とともに半導体素子11
に供給されて半導体装置に誤動作を起こさせるという重
大な欠点も有していた。In recent years, the density and integration of the semiconductor element 11 have been rapidly increased, and the number of electrodes has been greatly increased. Each electrode of the semiconductor element 11 (power supply electrode, ground electrode, signal electrode ), The number of external lead terminals 13 to be connected also increases rapidly, and the line width of each external lead terminal 13 is extremely thin.
Inductance is getting higher, about 15nH. Therefore, the semiconductor element is connected via this external lead terminal 13.
When power and an electric signal for driving are supplied to the semiconductor device 11, a large noise is generated when a fluctuation occurs in a power supply voltage supplied to the semiconductor element 11 due to a high inductance of the external lead terminal 13. With semiconductor element 11
To cause a malfunction in the semiconductor device.
【０００６】[0006]
【発明の目的】本発明は上記諸欠点に鑑み案出されたも
ので、その目的は半導体素子が発する熱によって半導体
素子自身を高温となすのを有効に防止し、且つ半導体素
子への供給電源電圧の変動に伴うノイズを有効に吸収
し、半導体素子を長期間にわたり正常、且つ安定に作動
させることができる半導体素子収納用パッケージを提供
することにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to effectively prevent the temperature of the semiconductor element itself from being raised to a high temperature by the heat generated by the semiconductor element, and to supply power to the semiconductor element. An object of the present invention is to provide a semiconductor element storage package that can effectively absorb noise caused by voltage fluctuations and operate the semiconductor element normally and stably for a long period of time.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体素子収納
用パッケージは、上面に半導体素子が搭載される搭載部
を有し、半導体素子の接地電極及び接地リード端子が接
続される銅製基体と、前記銅製基体の上面外周部に高誘
電率樹脂を介して取着され、半導体素子の電源電極及び
電源リード端子が接続される電源板と、前記電源板上に
低誘電率樹脂を介して取着される接地リード端子、電源
リード端子及び半導体素子の信号電極が接続される信号
リード端子と、前記銅製基体、電源リード端子、接地リ
ード端子及び信号リード端子の一部を被覆し、半導体素
子を収容するための空所を形成する樹脂製枠部材とから
成ることを特徴とするものである。According to the present invention, there is provided a semiconductor element housing package having a mounting portion for mounting a semiconductor element on an upper surface, a copper base to which a ground electrode and a ground lead terminal of the semiconductor element are connected; A power supply plate attached to the outer peripheral portion of the upper surface of the copper base via a high dielectric constant resin, to which a power supply electrode and a power supply lead terminal of a semiconductor element are connected; and a power supply plate attached to the power supply plate via a low dielectric constant resin. A ground lead terminal, a power lead terminal, and a signal lead terminal to which the signal electrode of the semiconductor element is connected, and a part of the copper base, the power lead terminal, the ground lead terminal, and the signal lead terminal, and accommodate the semiconductor element. And a resin-made frame member forming a space for forming the space.
【０００８】[0008]
【作用】本発明の半導体素子収納用パッケージによれ
ば、半導体素子が搭載される基体を熱伝導率が200W/m・
K の熱を伝え易い銅で形成したことから、半導体素子が
作動時に多量の熱を発したとしてもその熱は銅製基体に
良好に吸収拡散され、その結果、半導体素子は常に低温
となり、長期間にわたって正常、且つ安定に作動させる
ことが可能となる。According to the semiconductor device housing package of the present invention, the base on which the semiconductor device is mounted has a thermal conductivity of 200 W / m ·
Since it is made of copper, which easily conducts the heat of K, even if the semiconductor element generates a large amount of heat during operation, the heat is well absorbed and diffused into the copper base, and as a result, the semiconductor element always has a low temperature, For normal and stable operation.
【０００９】また本発明の半導体素子収納用パッケージ
によれば、半導体素子の電源電極及び接地電極が接続さ
れる銅製基体と電源板との間に高誘電率樹脂が挟まれて
おり、半導体素子の電源電極と接地電極との間に3nF 以
上の大きな静電容量が接続されていることから半導体素
子への供給電源電圧の変動に伴ってノイズが発生したと
しても該ノイズは前記大きな静電容量によって有効に吸
収され、その結果、半導体素子にノイズが入り込むのが
皆無となって半導体素子を長期間にわたり正常、且つ安
定に作動させることもできる。According to the semiconductor device housing package of the present invention, the high dielectric resin is sandwiched between the power supply plate and the copper base to which the power supply electrode and the ground electrode of the semiconductor device are connected. Since a large capacitance of 3 nF or more is connected between the power supply electrode and the ground electrode, even if noise occurs due to the fluctuation of the power supply voltage supplied to the semiconductor element, the noise is generated by the large capacitance. The semiconductor device is effectively absorbed, and as a result, no noise enters the semiconductor device, and the semiconductor device can be operated normally and stably for a long period of time.
【００１０】[0010]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1 は本発明の半導体素子収納用パッケージの一実
施例を示し、1 は基体、２は電源板である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows an embodiment of a package for housing a semiconductor element according to the present invention, wherein 1 is a base, and 2 is a power supply plate.
【００１１】前記基体1 は銅(Cu)から成り、その上面の
略中央部に半導体素子3 を搭載するための搭載部1aを有
し、該搭載部1aには半導体素子3 がロウ材等の接着材を
介して接着固定される。The base 1 is made of copper (Cu), and has a mounting portion 1a for mounting the semiconductor element 3 at a substantially central portion of the upper surface thereof, and the semiconductor element 3 is provided with a brazing material or the like on the mounting portion 1a. It is bonded and fixed via an adhesive.
【００１２】前記基体1 は半導体素子3 を支持するため
の支持部材として作用するとともに半導体素子3 の接地
電極と後述する接地リード端子4aとを電気的に接続する
接続部材として作用し、基体1 には半導体素子3 の接地
電極及び接地リード端子4aがボンディングワイヤ5aを介
して各々、電気的に接続される。The base 1 functions as a support member for supporting the semiconductor element 3 and also as a connecting member for electrically connecting a ground electrode of the semiconductor element 3 and a ground lead terminal 4a described later. The ground electrode and the ground lead terminal 4a of the semiconductor element 3 are electrically connected to each other via a bonding wire 5a.
【００１３】また前記銅から成る基体1 はそれを構成す
る銅の熱伝導率が200W/m・K と高く、熱を伝え易いた
め、半導体素子3 が作動時に多量の熱を発生したとして
もその熱は基体1 に良好に伝達吸収され、その結果、半
導体素子3 が該素子3 自身の発する熱によって高温とな
ることはなく、半導体素子3 に熱破壊や特性に変化をき
たし、誤動作を起こさせることは皆無となる。The base 1 made of copper has a high thermal conductivity of copper of 200 W / m · K and is easy to conduct heat. Therefore, even when the semiconductor element 3 generates a large amount of heat during operation, the heat is generated. The heat is transmitted and absorbed well by the base 1, so that the semiconductor element 3 does not become hot due to the heat generated by the element 3 itself, causing the semiconductor element 3 to undergo thermal destruction or change in characteristics, causing malfunction. There is nothing at all.
【００１４】尚、前記銅から成る基体1 は銅(Cu)のイン
ゴット( 塊) に圧延加工法や打ち抜き加工法等、従来周
知の金属加工法を施すことによって所定の板状に形成さ
れる。The substrate 1 made of copper is formed in a predetermined plate shape by subjecting a copper (Cu) ingot to a conventionally known metal working method such as a rolling method or a punching method.
【００１５】更に前記基体1 はその上面外周部に電源板
2 が誘電率を60以上とした高誘電率樹脂6 を挟んで取着
されており、該電源板2 には半導体素子3 の電源電極及
び後述する電源リード端子4bがそれぞれボンディングワ
イヤ5bを介して接続されている。Further, the base 1 has a power supply plate
2 are attached with a high dielectric constant resin 6 having a dielectric constant of 60 or more interposed therebetween, and a power supply electrode of the semiconductor element 3 and a power supply lead terminal 4b described later are respectively connected to the power supply plate 2 through bonding wires 5b. It is connected.
【００１６】前記電源板2 は半導体素子3 の電源電極と
電源リード端子4bとを電気的に接続するとともに電源板
2 と基体1 との間に高誘電率樹脂6 を誘電体とした所定
値の静電容量を形成し、これを半導体素子3 の接地電極
と電源電極との間に接続する作用を為す。The power supply plate 2 electrically connects the power supply electrode of the semiconductor element 3 and the power supply lead terminal 4b, and
A predetermined value of capacitance is formed between the substrate 2 and the base 1 using the high dielectric resin 6 as a dielectric, and the capacitance is connected between the ground electrode and the power supply electrode of the semiconductor element 3.
【００１７】前記電源板2 は銅(Cu)等の厚さ0.15mm程度
の金属板から成り、基体1 と同様の方法によって所定の
板状に形成される。The power supply plate 2 is made of a metal plate having a thickness of about 0.15 mm, such as copper (Cu), and is formed in a predetermined plate shape in the same manner as the base 1.
【００１８】また前記電源板2 は基体1 との間に誘電率
を60以上とした高誘電率樹脂6 が挟まれていることから
電源板2 と基体1 との間に形成され、半導体素子3 の接
地電極と電源電極との間に接続される静電容量の値を3n
F 程度の大きなものとなすことができ、その結果、半導
体素子3 に駆動のための電力及び電気信号を供給した
際、半導体素子3 への供給電源電圧に変動が生じて大き
なノイズが発生したとしても該ノイズは前記大きな静電
容量によって有効に吸収され、半導体素子3 にノイズが
入り込むことは無く、半導体素子3 に誤動作を招来する
ことも一切なくなる。Since the high-permittivity resin 6 having a dielectric constant of 60 or more is sandwiched between the power supply plate 2 and the base 1, the power supply plate 2 is formed between the power supply plate 2 and the base 1, The value of the capacitance connected between the ground electrode and the power
As a result, when power and electric signals for driving are supplied to the semiconductor element 3, the power supply voltage supplied to the semiconductor element 3 fluctuates and large noise occurs. However, the noise is effectively absorbed by the large capacitance, the noise does not enter the semiconductor element 3, and the semiconductor element 3 does not malfunction at all.
【００１９】前記電源板2 と基体1 との間に挟まれる誘
電率を60以上とした高誘電率樹脂6は例えば、エポキシ
樹脂やポリイミド樹脂にチタン酸バリウムやチタン酸ス
トロンチウム等の高誘電体粉末を含有させて成り、基体
1 の上面外周部に高誘電率樹脂6 と電源板2 とを順次載
置させ、しかる後、前記高誘電率樹脂6 を熱硬化させる
ことによって基体1 の上面外周部に取着される。The high dielectric resin 6 having a dielectric constant of 60 or more sandwiched between the power supply plate 2 and the base 1 is made of, for example, an epoxy resin or a polyimide resin or a high dielectric powder such as barium titanate or strontium titanate. And a substrate
The high-permittivity resin 6 and the power supply plate 2 are sequentially placed on the outer periphery of the upper surface of the substrate 1, and then the high-permittivity resin 6 is thermally cured to be attached to the outer periphery of the upper surface of the base 1.
【００２０】更に前記電源板2 上には誘電率を4 以下と
した低誘電率樹脂7 を介して接地リード端子4a、電源リ
ード端子4b及び半導体素子3 の信号電極が接続される信
号リード端子( 不図示) が取着されており、該接地リー
ド端子4a、電源リード端子4b及び信号リード端子には半
導体素子3 の接地電極、電源電極及び信号電極が各々、
ボンディングワイヤ5a、5b等を介して電気的に接続され
る。Further, on the power supply plate 2, a ground lead terminal 4 a, a power supply lead terminal 4 b, and a signal lead terminal (to be connected to a signal electrode of the semiconductor element 3) via a low dielectric constant resin 7 having a dielectric constant of 4 or less. (Not shown) are attached, and the ground electrode, the power electrode and the signal electrode of the semiconductor element 3 are respectively provided on the ground lead terminal 4a, the power
They are electrically connected via bonding wires 5a, 5b and the like.
【００２１】前記接地リード端子4aや電源リード端子4b
等は半導体素子3 の各電極( 接地電極、電源電極、信号
電極) を外部電気回路に接続する作用を為し、コバール
金属( 鉄ーニッケルーコバルト合金) や42アロイ( 鉄ー
ニッケルーコバルト合金) 、銅 等の金属材料によって
形成されている。The ground lead terminal 4a and the power supply lead terminal 4b
Works to connect each electrode (ground electrode, power electrode, signal electrode) of the semiconductor element 3 to an external electric circuit, and uses Kovar metal (iron-nickel-cobalt alloy) and 42 alloy (iron-nickel-cobalt alloy). ), Copper and other metal materials.
【００２２】尚、前記接地リード端子4aや電源リード端
子4b等はコバール金属等のインゴット( 塊) に圧延加工
法や打ち抜き加工法等、従来周知の金属加工法を施すこ
とによって所定の板状に形成される。The ground lead terminals 4a and the power supply lead terminals 4b are formed into a predetermined plate shape by applying a conventionally known metal working method such as a rolling method or a punching method to an ingot made of Kovar metal or the like. It is formed.
【００２３】また前記接地リード端子4aや電源リード端
子4b等を電源板2 上に取着する低誘電率樹脂7 は例えば
ポリイミド樹脂から成り、接地リード端子4aや電源リー
ド端子4bと電源板2 との間に前記ポリイミド樹脂から成
るテープの両面にエポキシ樹脂から成る接着剤を塗布し
たものを挟み、しかる後、前記エポキシ樹脂から成る接
着剤を熱硬化させることによって電源板2 と接地リード
端子4aや電源リード端子4b等との間に配される。The low dielectric constant resin 7 for attaching the ground lead terminals 4a and the power supply lead terminals 4b and the like on the power supply plate 2 is made of, for example, a polyimide resin. The adhesive made of epoxy resin is applied to both sides of the tape made of the polyimide resin, and the power supply plate 2 and the ground lead terminals 4a and the like are then cured by thermosetting the adhesive made of the epoxy resin. It is arranged between the power supply lead terminal 4b and the like.
【００２４】更に前記基体1 の半導体素子搭載部1aを除
く表面及び接地リード端子4aや電源リード端子4b等の一
部が樹脂製枠部材8 によって被覆されており、該樹脂製
枠部材8 によって半導体素子3 を収容するための空所が
形成されている。Further, the surface of the base 1 excluding the semiconductor element mounting portion 1a and a part of the ground lead terminal 4a and the power supply lead terminal 4b are covered with a resin frame member 8, and the semiconductor frame member 8 A space for accommodating the element 3 is formed.
【００２５】前記樹脂製枠部材8 は例えば、エポキシ樹
脂から成り、上面に接地リード端子4aや電源リード端子
4b等が取着された基体1 を所定型内にセットするととも
に該所定型内に液状のエポキシ樹脂を充填し、これを約
150 ℃の温度で熱硬化させることによって所定形状に形
成される。The resin frame member 8 is made of, for example, epoxy resin, and has a ground lead terminal 4a and a power lead terminal on the upper surface.
The substrate 1 to which 4b and the like are attached is set in a predetermined mold, and the predetermined mold is filled with a liquid epoxy resin.
It is formed into a predetermined shape by thermosetting at a temperature of 150 ° C.
【００２６】前記樹脂製枠部材8 は基体1 の半導体素子
搭載部1aに半導体素子3 を接着固定した後、その内側に
樹脂製充填剤9 が充填され、該樹脂製充填剤9 で半導体
素子3 を気密に封止することによって製品としての半導
体装置が完成する。After the semiconductor element 3 is bonded and fixed to the semiconductor element mounting portion 1a of the base 1, the resin filler 9 is filled inside the resin frame member 8, and the resin element 9 is filled with the resin filler 9. Is hermetically sealed to complete a semiconductor device as a product.
【００２７】前記樹脂製充填剤9 は例えばエポキシ樹
脂、ポリイミド樹脂、フェノール樹脂等から成り、例え
ばエポキシ樹脂となる液状の樹脂を半導体素子3 が接着
固定されている樹脂製枠部材8 の内側に半導体素子3 が
完全に埋まるように充填させるとともにこれを約150 ℃
の温度で熱硬化させることによって樹脂製枠部材8 の内
側に半導体素子3 を気密に封止するようにして配され
る。The resin filler 9 is made of, for example, an epoxy resin, a polyimide resin, a phenol resin, or the like. For example, a liquid resin to be an epoxy resin is applied to the inside of the resin frame member 8 to which the semiconductor element 3 is adhered and fixed. Element 3 is filled so that it is completely filled, and this is
The semiconductor element 3 is disposed inside the resin-made frame member 8 so as to hermetically seal it by thermosetting at the above temperature.
【００２８】かくして本発明の半導体素子収納用パッケ
ージによれば、基体1 の半導体素子搭載部1aに半導体素
子3 を接着固定するとともに半導体素子3 の各電極を基
体1、電源板2 及び接地リード端子4aや電源リード端子4
b等にボンディングワイヤ5a、5b等を介して接続し、最
後に樹脂製枠部材8 の内側に樹脂製充填剤9 を充填し、
半導体素子3 を気密に封止することによって製品として
の半導体装置となる。Thus, according to the semiconductor element housing package of the present invention, the semiconductor element 3 is bonded and fixed to the semiconductor element mounting portion 1a of the base 1, and each electrode of the semiconductor element 3 is connected to the base 1, the power supply plate 2, and the ground lead terminal. 4a and power lead terminal 4
b, etc. via bonding wires 5a, 5b, etc., and finally, a resin filler 9 is filled inside the resin frame member 8,
A semiconductor device as a product is obtained by hermetically sealing the semiconductor element 3.
【００２９】尚、本発明の半導体素子収納用パッケージ
は上述の実施例に限定されるものではなく、本発明の要
旨を逸脱しない範囲であれば種々の変更は可能である。The package for accommodating a semiconductor device of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.
【００３０】[0030]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば、半導体素子が搭載される基体を熱伝導率が200W
/m・K の熱を伝え易い銅で形成したことから、半導体素
子が作動時に多量の熱を発したとしてもその熱は銅製基
体に良好に吸収拡散され、その結果、半導体素子は常に
低温となり、長期間にわたって正常、且つ安定に作動さ
せることが可能となる。According to the semiconductor device housing package of the present invention, the substrate on which the semiconductor device is mounted has a thermal conductivity of 200 W.
/ m ・ K, which is easy to transmit heat, even if a semiconductor device generates a large amount of heat during operation, the heat is well absorbed and diffused into the copper base, and as a result, the semiconductor device is always kept at a low temperature. It is possible to operate normally and stably for a long period of time.
【００３１】また本発明の半導体素子収納用パッケージ
によれば、半導体素子の電源電極及び接地電極が接続さ
れる銅製基体と電源板との間に高誘電率樹脂が挟まれて
おり、半導体素子の電源電極と接地電極との間に3nF 以
上の大きな静電容量が接続されていることから半導体素
子への供給電源電圧の変動に伴ってノイズが発生したと
しても該ノイズは前記大きな静電容量によって有効に吸
収され、その結果、半導体素子にノイズが入り込むのが
皆無となって半導体素子を長期間にわたり正常、且つ安
定に作動させることもできる。According to the semiconductor device housing package of the present invention, the high dielectric resin is sandwiched between the power supply plate and the copper base to which the power supply electrode and the ground electrode of the semiconductor device are connected. Since a large capacitance of 3 nF or more is connected between the power supply electrode and the ground electrode, even if noise occurs due to the fluctuation of the power supply voltage supplied to the semiconductor element, the noise is generated by the large capacitance. The semiconductor device is effectively absorbed, and as a result, no noise enters the semiconductor device, and the semiconductor device can be operated normally and stably for a long period of time.
【図１】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.
【図２】従来の半導体素子収納用パッケージの断面図で
ある。FIG. 2 is a cross-sectional view of a conventional semiconductor element storage package.
１・・・・基体 ２・・・・電源板 ３・・・・半導体素子 ４ａ・・・接地リード端子 ４ｂ・・・電源リード端子 ６・・・・高誘電率樹脂 ７・・・・低誘電率樹脂 ８・・・・樹脂製枠部材 DESCRIPTION OF SYMBOLS 1 ... Base 2 ... Power supply plate 3 ... Semiconductor element 4a ... Ground lead terminal 4b ... Power supply lead terminal 6 ... High permittivity resin 7 ... Low dielectric Resin 8 ... Resin frame member
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/50,23/36──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 23 / 50,23 / 36
Claims (1)
し、半導体素子の接地電極及び接地リード端子が接続さ
れる銅製基体と、前記銅製基体の上面外周部に誘電率が
６０以上の高誘電率樹脂を介して取着され、半導体素子
の電源電極及び電源リード端子が接続される電源板と、
前記電源板上に誘電率が４以下の低誘電率樹脂を介して
取着される接地リード端子、電源リード端子及び半導体
素子の信号電極が接続される信号リード端子と、前記銅
製基体、電源リード端子、接地リード端子及び信号リー
ド端子の一部を被覆し、半導体素子を収容するための空
所を形成する樹脂製枠部材とから成り、電源リード端子
と接地リード端子との間に３ｎＦ以上の静電容量が接続
されている半導体素子収納用パッケージ。1. A has a mounting portion on which the semiconductor element on the upper surface are mounted, a copper substrate ground electrode and the ground lead terminal of the semiconductor element is connected, the dielectric constant on the upper surface outer peripheral portion of the copper substrate
A power supply plate attached via a high dielectric constant resin of 60 or more, to which a power supply electrode and a power supply lead terminal of the semiconductor element are connected;
A ground lead terminal, a power lead terminal, and a signal lead terminal to which a signal electrode of a semiconductor device is connected via a low dielectric constant resin having a dielectric constant of 4 or less on the power supply plate; terminals, and covers a part of the ground lead terminal and the signal lead terminal, Ri consists a resin frame member to form a cavity for housing a semiconductor element, a power supply lead terminals
3nF or more capacitance is connected between the ground lead terminal
By semiconductor device package for housing it is.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5068100A JP2806729B2 (en) | 1993-03-26 | 1993-03-26 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5068100A JP2806729B2 (en) | 1993-03-26 | 1993-03-26 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06283655A JPH06283655A (en) | 1994-10-07 |
| JP2806729B2 true JP2806729B2 (en) | 1998-09-30 |
Family
ID=13363990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5068100A Expired - Fee Related JP2806729B2 (en) | 1993-03-26 | 1993-03-26 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2806729B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19931694B4 (en) * | 1999-07-08 | 2006-05-24 | Curamik Electronics Gmbh | Method for producing electrical circuits or modules and electrical circuit or electrical module produced by this method |
| JP2007042669A (en) * | 2005-07-29 | 2007-02-15 | Toyoda Gosei Co Ltd | Light source apparatus |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5917274A (en) * | 1982-07-21 | 1984-01-28 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS5943529A (en) * | 1982-09-03 | 1984-03-10 | Matsushita Electric Works Ltd | Manufacture of resin sealed type electronic part |
| JP2740977B2 (en) * | 1990-03-30 | 1998-04-15 | 株式会社三井ハイテック | Semiconductor device |
| JP2828326B2 (en) * | 1990-07-12 | 1998-11-25 | 新光電気工業株式会社 | Multilayer lead frame and manufacturing method thereof |
| JPH04119659A (en) * | 1990-09-10 | 1992-04-21 | Sumitomo Electric Ind Ltd | Lead frame |
| JPH04254363A (en) * | 1991-02-06 | 1992-09-09 | Hitachi Ltd | Lead frame and semiconductor integrated circuit device utilizing the same |
-
1993
- 1993-03-26 JP JP5068100A patent/JP2806729B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06283655A (en) | 1994-10-07 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |