JP2823758B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2823758B2
JP2823758B2 JP4334131A JP33413192A JP2823758B2 JP 2823758 B2 JP2823758 B2 JP 2823758B2 JP 4334131 A JP4334131 A JP 4334131A JP 33413192 A JP33413192 A JP 33413192A JP 2823758 B2 JP2823758 B2 JP 2823758B2
Authority
JP
Japan
Prior art keywords
lead terminal
semiconductor element
ground
ground lead
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4334131A
Other languages
Japanese (ja)
Other versions
JPH06181285A (en
Inventor
洋一 関岡
清志 冨田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP4334131A priority Critical patent/JP2823758B2/en
Publication of JPH06181285A publication Critical patent/JPH06181285A/en
Application granted granted Critical
Publication of JP2823758B2 publication Critical patent/JP2823758B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はコンピュータ等の情報処
理装置に実装される半導体装置の改良に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor device mounted on an information processing device such as a computer.

【0002】[0002]

【従来の技術】従来、コンピュータ等の情報処理装置に
実装される半導体装置は半導体素子を金属板上に接着剤
を介して接着固定するとともに該半導体素子の各電極(
電源電極、接地電極及び信号電極) を外部リード端子に
ボンディングワイヤを介して電気的に接続し、しかる
後、金属板上に固定された半導体素子と外部リード端子
の一部を樹脂でモールド被覆し、半導体素子を気密に封
止することによって製作されている。
2. Description of the Related Art Conventionally, in a semiconductor device mounted on an information processing apparatus such as a computer, a semiconductor element is bonded and fixed on a metal plate via an adhesive, and each electrode (
The power supply electrode, the ground electrode, and the signal electrode) are electrically connected to the external lead terminals via bonding wires.After that, the semiconductor element fixed on the metal plate and a part of the external lead terminals are molded and covered with resin. Are manufactured by hermetically sealing a semiconductor element.

【0003】しかしながら、近時、半導体素子は高密度
化、高集積化が急激に進み、電極の数が大幅に増大して
きており、該半導体素子の各電極に接続される外部リー
ド端子の数も急激に増大し、各外部リード端子はその線
幅が極めて細く、インダクタンスが20nH程度の高いもの
となってきている。そのためこの外部リード端子を介し
て半導体素子に駆動のための電力及び電気信号を供給し
た場合、外部リード端子のインダクタンスが高いことに
起因して半導体素子への供給電源電圧に変動が生じると
大きなノイズが発生し、これが電気信号とともに半導体
素子に供給されて半導体素子に誤動作を起こさせるとい
う重大な欠点を有していた。
In recent years, however, the density and integration of semiconductor devices have been rapidly increasing, and the number of electrodes has been greatly increased. The number of external lead terminals connected to each electrode of the semiconductor device has also been increasing. The line width of each external lead terminal is extremely small, and the inductance is as high as about 20 nH. Therefore, when power and an electric signal for driving are supplied to the semiconductor element through the external lead terminal, a large noise is generated when the supply power supply voltage to the semiconductor element fluctuates due to a high inductance of the external lead terminal. This has a serious drawback in that this is supplied to the semiconductor element together with the electric signal and causes the semiconductor element to malfunction.

【0004】そこで上記欠点を解消するために外部リー
ド端子のうち半導体素子の電源電極及び接地電極が接続
される電源リード端子と接地リード端子とを間にポリイ
ミド樹脂から成る樹脂誘電層を挟んで対向配置させ、電
源リード端子と接地リード端子の間にポリイミド樹脂を
誘電体とした一定の静電容量をもたせ、半導体素子への
供給電源電圧の変動により生じるノイズを前記静電容量
に吸収させて半導体素子の誤動作を防止することが提案
されている。
In order to solve the above-mentioned drawbacks, of the external lead terminals, a power lead terminal to which a power electrode and a ground electrode of a semiconductor element are connected and a ground lead terminal are opposed to each other with a resin dielectric layer made of a polyimide resin interposed therebetween. A constant capacitance having a polyimide resin as a dielectric material is provided between a power supply lead terminal and a ground lead terminal, and a noise generated due to a fluctuation of a power supply voltage supplied to the semiconductor element is absorbed by the capacitance. It has been proposed to prevent malfunction of the device.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、この半
導体装置では電源リード端子と接地リード端子との対向
面積が約 400mm 2と狭いこと、電源リード端子と接地リ
ード端子との間に挟まれるポリイミド樹脂の誘電率が3.
5 程度と低い値であること等から電源リード端子と接地
リード端子間に形成される静電容量は0.2nF 程度と小さ
く、その結果、前記静電容量で半導体素子への供給電源
電圧の変動により生じるノイズを完全に吸収することが
できず、いまだ半導体素子に誤動作を起こさせるという
欠点を有していた。
However, in this semiconductor device, the facing area between the power supply lead terminal and the ground lead terminal is as small as about 400 mm 2, and the polyimide resin sandwiched between the power supply lead terminal and the ground lead terminal. Dielectric constant 3.
The capacitance formed between the power supply lead terminal and the ground lead terminal is as small as about 0.2 nF due to the low value of about 5 and the like. As a result, the capacitance causes the fluctuation of the power supply voltage supplied to the semiconductor element. The generated noise cannot be completely absorbed, and still has a drawback that a semiconductor element malfunctions.

【0006】[0006]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は半導体素子への供給電源電圧の変動に伴
うノイズを有効に吸収し、半導体素子を長期間にわたり
正常、且つ安定に作動させることができる半導体装置を
提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and an object of the present invention is to effectively absorb noise caused by fluctuations in a power supply voltage to a semiconductor element and to make the semiconductor element normal and stable for a long period of time. It is an object of the present invention to provide a semiconductor device which can be operated at a low speed.

【0007】[0007]

【課題を解決するための手段】本発明は半導体素子と、
前記半導体素子の電源電極、接地電極、信号電極が接続
される電源リード端子、接地リード端子及び信号リード
端子と、前記半導体素子及び各リード端子の一部を被覆
する樹脂被覆材とから成る半導体装置であって、前記電
源リード端子と接地リード端子との間に誘電率が500 以
上の高誘電率磁器を介在させたことを特徴とするもので
ある。
SUMMARY OF THE INVENTION The present invention provides a semiconductor device,
A semiconductor device comprising a power lead terminal, a ground lead terminal, and a signal lead terminal to which a power electrode, a ground electrode, and a signal electrode of the semiconductor element are connected, and a resin coating material that partially covers the semiconductor element and each of the lead terminals. Wherein a high dielectric constant ceramic having a dielectric constant of 500 or more is interposed between the power supply lead terminal and the ground lead terminal.

【0008】また本発明は半導体素子が接地リード端子
の上面に載置され、且つ該接地リード端子の半導体素子
が載置される領域の下方に突出部を形成することを特徴
とするものである。
Further, the invention is characterized in that the semiconductor element is mounted on the upper surface of the ground lead terminal, and a projection is formed below a region where the semiconductor element of the ground lead terminal is mounted. .

【0009】更に本発明は前記接地リード端子の突出部
に放熱フィンを接合させることを特徴とするものであ
る。
Further, the present invention is characterized in that a radiation fin is joined to the protruding portion of the ground lead terminal.

【0010】[0010]

【作用】本発明によれば半導体素子の電源電極及び接地
電極が接続される電源リード端子と接地リード端子の間
に誘電率が500 以上の高誘電率磁器を介在させたことか
ら電源リード端子と接地リード端子間には10.0nF以上の
大きな静電容量が接続されることとなり、その結果、半
導体素子への供給電源電圧の変動に伴ってノイズが発生
したとしても該ノイズは前記大きな静電容量によって有
効に吸収され、半導体素子にノイズが入り込むのが皆無
となって半導体素子を長期間にわたり正常、且つ安定に
作動させることが可能となる。
According to the present invention, a high dielectric constant ceramic having a dielectric constant of 500 or more is interposed between a power supply lead terminal to which a power supply electrode and a ground electrode of a semiconductor element are connected and a ground lead terminal. As a result, a large capacitance of 10.0 nF or more is connected between the ground lead terminals. As a result, even if noise occurs due to the fluctuation of the power supply voltage supplied to the semiconductor element, the noise remains at the large capacitance. Accordingly, the semiconductor device is effectively absorbed, and no noise enters the semiconductor device, and the semiconductor device can be operated normally and stably for a long period of time.

【0011】また半導体素子を接地リード端子の上面に
載置させるとともに該接地リード端子の半導体素子が載
置される領域の下方に突出部を形成し、更に必要に応じ
て前記接地リード端子の突出部に放熱フィンを接合させ
たことから半導体素子が作動時に熱を多量に発生したと
してもその熱は接地リード端子及び放熱フィンを介して
大気中に良好に放散され、その結果、半導体素子は常に
低温となって長期間にわたり正常、且つ安定に作動させ
ることができる。
The semiconductor element is mounted on the upper surface of the ground lead terminal, and a projection is formed below a region of the ground lead terminal on which the semiconductor element is mounted. Even if the semiconductor device generates a large amount of heat during operation because the heat dissipation fins are joined to the part, the heat is satisfactorily dissipated into the atmosphere via the ground lead terminal and the heat dissipation fins. It can be operated normally and stably for a long time at a low temperature.

【0012】[0012]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。
BRIEF DESCRIPTION OF THE DRAWINGS FIG.

【0013】図1 は本発明の半導体装置の一実施例を示
し、図中、半導体装置1 は半導体素子2 と、電源リード
端子3a、接地リード端子3b、信号リード端子3cと、樹脂
被覆材4 とから構成されている。
FIG. 1 shows an embodiment of a semiconductor device according to the present invention. In the drawing, a semiconductor device 1 includes a semiconductor element 2, a power supply lead terminal 3 a, a ground lead terminal 3 b, a signal lead terminal 3 c, and a resin coating material 4. It is composed of

【0014】前記電源リード端子3a、接地リード端子3
b、信号リード端子3cは半導体素子2の電源電極、接地電
極及び信号電極を外部電気回路に電気的に接続する作用
を為し、電源リード端子3aには半導体素子2 の電源電極
が、接地リード端子3bには接地電極が、信号リード端子
3cには信号電極が各々、ボンディングワイヤ5 を介して
電気的に接続される。
The power supply lead terminal 3a, the ground lead terminal 3
b, the signal lead terminal 3c functions to electrically connect the power electrode, the ground electrode, and the signal electrode of the semiconductor element 2 to an external electric circuit, and the power electrode of the semiconductor element 2 is connected to the power lead terminal 3a by the ground lead. Terminal 3b has a ground electrode and signal lead terminal
The signal electrodes 3c are electrically connected to each other via bonding wires 5.

【0015】また前記接地リード端子3bの上部には半導
体素子2 が搭載されており、該半導体素子2 はガラス、
樹脂、ロウ材等の接着剤を介し接地リード端子3bの上面
に接着固定されている。
A semiconductor element 2 is mounted on the ground lead terminal 3b. The semiconductor element 2 is made of glass,
It is bonded and fixed to the upper surface of the ground lead terminal 3b via an adhesive such as resin or brazing material.

【0016】前記各リード端子3a、3b、3cは銅(Cu)、銅
ージルコニウム合金(Cu-Zr合金) 、コバール合金(Fe-Ni
-Co 合金) 、42アロイ(Fe-Ni合金) 等の金属材料から成
り、コバール金属等のインゴット( 塊) を従来周知の圧
延加工法を採用することによって薄板状に形成するとと
もにこれを打ち抜き加工法やエッチング加工法により所
定形状に打ち抜くことによって形成される。
The lead terminals 3a, 3b, 3c are made of copper (Cu), copper-zirconium alloy (Cu-Zr alloy), Kovar alloy (Fe-Ni
-Co alloy), 42 alloy (Fe-Ni alloy) and other metal materials, and ingots (lumps) of Kovar metal etc. are formed into a thin plate by using the conventionally known rolling method, and are punched. It is formed by punching into a predetermined shape by a method or an etching method.

【0017】また前記電源リード端子3aと接地リード端
子3bの対向する領域には高誘電率磁器6 が挟まれてお
り、電源リード端子3aと接地リード端子3bとの間には前
記高誘電率磁器6 を誘電体とした一定の大きさの静電容
量が形成される。この場合、高誘電率磁器6 の誘電率が
500 以上であることから電源リード端子3aと接地リード
端子3bとの間に形成される静電容量はその値が10.0nF以
上の大きなものとなり、その結果、半導体素子2 への供
給電源電圧の変動に伴って発生するノイズは前記大きな
静電容量によって効果的に吸収され、該ノイズが電気信
号とともに半導体素子2 に印加され、半導体素子2 に誤
動作を起こさせることは皆無となる。
A high-permittivity ceramic 6 is sandwiched between the power lead terminal 3a and the ground lead terminal 3b, and a high dielectric ceramic is placed between the power lead terminal 3a and the ground lead terminal 3b. A constant capacitance is formed with 6 as a dielectric. In this case, the dielectric constant of the high dielectric ceramic 6 is
Since it is 500 or more, the capacitance formed between the power supply lead terminal 3a and the ground lead terminal 3b has a large value of 10.0 nF or more, and as a result, the fluctuation of the power supply voltage supplied to the semiconductor element 2 Is effectively absorbed by the large capacitance, and the noise is applied to the semiconductor element 2 together with the electric signal, so that the semiconductor element 2 does not malfunction.

【0018】前記電源リード端子3aと接地リード端子3b
との間に挟まれる高誘電率磁器6 はチタン酸バリウム磁
器や酸化チタン磁器が好適に使用され、例えばチタン酸
バリウム磁器から成る場合、まず炭酸バリウム、酸化チ
タン、チタン酸マグネシウム等の原料粉末を焼成し反応
させてチタン酸バリウムを得るとともにこれを微粉に粉
砕してチタン酸バリウム粉末を得、次に前記チタン酸バ
リウム粉末に適当な溶剤、溶媒を添加混合して泥漿状と
なすとともにこれをドクターブレード法等を採用しシー
ト状に成形することによって生シートを得、最後に前記
生シートを複数枚積層するとともに約1300℃の温度で焼
成することによって製作される。
The power lead terminal 3a and the ground lead terminal 3b
Barium titanate porcelain or titanium oxide porcelain is preferably used as the high dielectric constant ceramic 6 sandwiched between the above.For example, in the case of barium titanate porcelain, raw powder such as barium carbonate, titanium oxide, magnesium titanate, etc. Baking and reacting to obtain barium titanate and pulverizing it into fine powder to obtain barium titanate powder, and then adding a suitable solvent and solvent to the barium titanate powder to form a slurry, A raw sheet is obtained by forming into a sheet shape by employing a doctor blade method or the like, and finally, a plurality of the raw sheets are laminated and fired at a temperature of about 1300 ° C.

【0019】尚、前記高誘電率磁器6 はその誘電率が50
0 未満となると電源リード端子3aと接地リード端子3bと
の間に形成される静電容量が小さくなり、半導体素子2
への供給電源電圧の変動に伴って発生するノイズを前記
静電容量によって効果的に吸収することができなくな
る。従って、前記高誘電率磁器6 はその誘電率が500 以
上のものに特定される。
The high dielectric constant ceramic 6 has a dielectric constant of 50.
When the value is less than 0, the capacitance formed between the power supply lead terminal 3a and the ground lead terminal 3b decreases, and the semiconductor element 2
The noise generated due to the fluctuation of the power supply voltage to the power supply cannot be effectively absorbed by the capacitance. Therefore, the high dielectric constant ceramic 6 is specified to have a dielectric constant of 500 or more.

【0020】また前記高誘電率磁器6 はその上下面に予
めモリブデンーマンガンから成るメタライズ金属層を被
着させておき、該メタライズ金属層を電源リード端子3a
と接地リード端子3bに半田等のロウ材を介し接合させる
ことによって電源リード端子3aと接地リード端子3bとの
間に固定される。
The high dielectric constant ceramic 6 has a metallized metal layer made of molybdenum-manganese previously deposited on the upper and lower surfaces thereof, and the metallized metal layer is connected to the power supply lead terminal 3a.
Is fixed between the power supply lead terminal 3a and the ground lead terminal 3b by bonding to the ground lead terminal 3b and a brazing material such as solder.

【0021】前記半導体素子2 及び該半導体素子2 の電
源電極、接地電極、信号電極が接続される電源リード端
子3a、接地リード端子3b、信号リード端子3cの一部はま
たエポキシ樹脂等から成る樹脂被覆材4 によって覆わ
れ、半導体素子2 を気密に封止することによって最終製
品としての半導体装置となる。
The semiconductor element 2 and a part of the power supply lead terminal 3a, the ground lead terminal 3b, and the signal lead terminal 3c to which the power supply electrode, the ground electrode, and the signal electrode of the semiconductor element 2 are connected are also made of resin such as epoxy resin. The semiconductor device as a final product is obtained by being covered with the coating material 4 and hermetically sealing the semiconductor element 2.

【0022】前記半導体素子2 等の樹脂被覆材4 による
被覆は所定治具内に半導体素子2 と電源リード端子3a、
接地リード端子3b、信号リード端子3c及び高誘電率磁器
6 を配し、しかる後、前記治具内に液状のエポキシ樹脂
を滴下充填させ、該充填した液状樹脂を150 〜170 ℃の
温度で熱硬化させることによって行われる。
The semiconductor element 2 and the like are covered with a resin coating material 4 in a predetermined jig.
Ground lead terminal 3b, signal lead terminal 3c and high dielectric constant porcelain
After that, a liquid epoxy resin is dropped and filled in the jig, and the filled liquid resin is thermally cured at a temperature of 150 to 170 ° C.

【0023】かくして本発明の半導体装置は各リード端
子を外部電気回路に接続させ、半導体素子の各電極を外
部電気回路に接続することによってコンピュータ等の情
報処理装置に実装されることとなる。
Thus, the semiconductor device of the present invention is mounted on an information processing device such as a computer by connecting each lead terminal to an external electric circuit and connecting each electrode of the semiconductor element to the external electric circuit.

【0024】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば図2 に示す如く、半導体
素子2 が載置される接地リード端子3bの半導体素子2 が
載置される領域の下方に突出部7 を形成しておくと接地
リード端子3bの突出部7 が半導体素子2 の作動時に発す
る熱を吸収するとともに該吸収した熱を大気中に放散さ
せて半導体素子2 の温度を低温となし、その結果、半導
体素子2 に熱破壊や特性に熱変化を来し、誤動作させる
のを有効に防止することが可能となって半導体素子2 を
長期間にわたり正常、且つ安定に作動させることができ
る。
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, as shown in FIG. If a projection 7 is formed below the region of the ground lead terminal 3b on which the semiconductor element 2 is mounted, the projection 7 of the ground lead terminal 3b absorbs heat generated when the semiconductor element 2 operates. At the same time, the absorbed heat is dissipated into the air to lower the temperature of the semiconductor element 2 to a low temperature. As a result, it is possible to effectively prevent the semiconductor element 2 from being thermally destructed or thermally changed in characteristics, thereby causing malfunction. This allows the semiconductor element 2 to operate normally and stably for a long period of time.

【0025】前記接地リード端子3bの突出部7 は接地リ
ード端子3bと同質の材料、具体的には銅(Cu)、銅ージル
コニウム合金(Cu-Zr合金) 、コバール合金(Fe-Ni-Co 合
金)、42アロイ(Fe-Ni合金) 等の金属材料から成り、コ
バール金属等のインゴット(塊) に従来周知の圧延加工
法等を施し接地リード端子3bを得る際に同時に接地リー
ド端子3bの下方に形成される。
The protruding portion 7 of the ground lead terminal 3b is made of the same material as the ground lead terminal 3b, specifically, copper (Cu), copper-zirconium alloy (Cu-Zr alloy), Kovar alloy (Fe-Ni-Co alloy). ), 42 alloy (Fe-Ni alloy), etc., and a conventional well-known rolling method is applied to an ingot (lumps) of Kovar metal or the like to obtain the ground lead terminal 3b and at the same time to obtain the ground lead terminal 3b. Formed.

【0026】また前記半導体素子2 が作動時に極めて多
量の熱を発生する場合には、図3 に示す如く、接地リー
ド端子3bの下方に設けた突出部7 に放熱フィン8 を接合
させておけば、その熱を突出部7 及び放熱フィン8 を介
して大気中により効率的に放散させることが可能とな
り、半導体素子2 が多量の熱を発生したとしても半導体
素子2 を常に低温とし、長期間にわたり正常、且つ安定
に作動させることができる。
When the semiconductor element 2 generates an extremely large amount of heat during operation, as shown in FIG. 3, a radiating fin 8 is joined to a projection 7 provided below the ground lead terminal 3b. However, the heat can be more efficiently dissipated in the atmosphere through the protruding portions 7 and the radiating fins 8, so that even if the semiconductor element 2 generates a large amount of heat, the semiconductor element 2 is kept at a low temperature for a long time. It can operate normally and stably.

【0027】前記接地リード端子3bに設けた突出部7 に
接合される放熱フィン8 としてはアルミニウムや銅等の
熱伝導率が150W/m・K 以上の金属が好適に使用され、例
えばアルミニウム等から成る板状体の一主面に機械研削
等の金属加工を施し、多数の溝を形成することによって
形成される。
As the radiating fin 8 joined to the protruding portion 7 provided on the ground lead terminal 3b, a metal having a thermal conductivity of 150 W / m · K or more such as aluminum or copper is preferably used. It is formed by performing metal working such as mechanical grinding on one main surface of the plate-like body thus formed to form a large number of grooves.

【0028】また前記放熱フィン8 は銀ーエポキシ樹脂
などの接着剤により接地リード端子3bに設けた突出部7
に接合される。
The radiating fins 8 are provided on the grounding lead terminals 3b with an adhesive such as silver-epoxy resin.
Joined to.

【0029】[0029]

【発明の効果】本発明の半導体装置によれば、半導体素
子の電源電極及び接地電極が接続される電源リード端子
と接地リード端子の間に誘電率が500 以上の高誘電率磁
器を介在させたことから電源リード端子と接地リード端
子間には10.0nF以上の大きな静電容量が接続されること
となり、その結果、半導体素子への供給電源電圧の変動
に伴ってノイズが発生したとしても該ノイズは前記大き
な静電容量によって有効に吸収され、半導体素子にノイ
ズが入り込むのが皆無となって半導体素子を長期間にわ
たり正常、且つ安定に作動させることが可能となる。
According to the semiconductor device of the present invention, a high dielectric constant ceramic having a dielectric constant of 500 or more is interposed between a power supply lead terminal and a ground lead terminal to which a power supply electrode and a ground electrode of a semiconductor element are connected. As a result, a large capacitance of 10.0 nF or more is connected between the power supply lead terminal and the ground lead terminal.As a result, even if noise occurs due to fluctuations in the power supply voltage supplied to the semiconductor element, the noise is not affected. Is effectively absorbed by the large capacitance, so that no noise enters the semiconductor element, and the semiconductor element can be operated normally and stably for a long period of time.

【0030】また本発明の半導体装置では接地リード端
子の上面に半導体素子を載置させるとともに接地リード
端子の半導体素子が載置される領域の下方に突出部を形
成せれば、更に必要に応じて前記突出部に放熱フィンを
接合させれば半導体素子の作動時に発する熱が前記突出
部及び放熱フィンに吸収されるとともに大気中に効率良
く放散され、その結果、半導体素子の温度は常に低温と
なり、半導体素子を長期間にわたり正常、且つ安定に作
動させることもできる。
Further, in the semiconductor device of the present invention, if a semiconductor element is mounted on the upper surface of the ground lead terminal and a protruding portion is formed below a region where the semiconductor element of the ground lead terminal is mounted, the semiconductor device may be further required. If a radiation fin is joined to the projection, heat generated during operation of the semiconductor element is absorbed by the projection and the radiation fin and efficiently radiated into the atmosphere.As a result, the temperature of the semiconductor element is always low, The semiconductor element can be normally and stably operated for a long time.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の一実施例を示す断面図で
ある。
FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention.

【図2】本発明の他の実施例を示す断面図である。FIG. 2 is a sectional view showing another embodiment of the present invention.

【図3】本発明の他の実施例を示す断面図である。FIG. 3 is a sectional view showing another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・半導体装置 2・・・・・半導体素子 3a・・・・電源リード端子 3b・・・・接地リード端子 3c・・・・信号リード端子 4・・・・・樹脂被覆材 6・・・・・高誘電率磁器 7・・・・・突出部 8・・・・・放熱フィン 1 ... Semiconductor device 2 ... Semiconductor element 3a ... Power supply lead terminal 3b ... Ground lead terminal 3c ... Signal lead terminal 4 ... Resin coating material 6 ···· High-permittivity porcelain 7 ···· Protrusion 8 ··· Radiating fins

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体素子と、前記半導体素子の電源電
極、接地電極、信号電極が接続される電源リード端子、
接地リード端子及び信号リード端子と、前記半導体素子
及び各リード端子の一部を被覆する樹脂被覆材とから成
る半導体装置であって、前記電源リード端子と接地リー
ド端子との間に誘電率が500以上の高誘電率磁器を介
在させるとともに、前記接地リード端子の上面に半導体
素子を載置させ、かつ該接地リード端子の前記半導体素
子が載置される領域の下方に突出部を設けたことを特徴
とする半導体装置。
A power lead terminal to which a power supply electrode, a ground electrode, and a signal electrode of the semiconductor element are connected;
A semiconductor device comprising a ground lead terminal and a signal lead terminal, and a resin coating material for covering a part of the semiconductor element and each lead terminal, wherein a dielectric constant between the power lead terminal and the ground lead terminal is 500. semiconductor Rutotomoni, the upper surface of the ground lead terminal is interposed a high dielectric constant ceramics of higher
An element mounted thereon, and the semiconductor element of the ground lead terminal.
A semiconductor device, wherein a protruding portion is provided below a region where a child is mounted .
【請求項2】前記接地リード端子の突出部に放熱フィン
が接合されていることを特徴とする請求項1に記載の半
導体装置。
2. The semiconductor device according to claim 1, wherein a radiation fin is joined to the projection of said ground lead terminal.
JP4334131A 1992-12-15 1992-12-15 Semiconductor device Expired - Fee Related JP2823758B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4334131A JP2823758B2 (en) 1992-12-15 1992-12-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4334131A JP2823758B2 (en) 1992-12-15 1992-12-15 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH06181285A JPH06181285A (en) 1994-06-28
JP2823758B2 true JP2823758B2 (en) 1998-11-11

Family

ID=18273873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4334131A Expired - Fee Related JP2823758B2 (en) 1992-12-15 1992-12-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2823758B2 (en)

Also Published As

Publication number Publication date
JPH06181285A (en) 1994-06-28

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