JP2805078B2 - Bit reduction device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit reduction device for reducing the number of bits of a PCM signal obtained by digitizing an analog signal and transmitting the PCM signal.

[Summary of the Invention]

A bit reduction device according to the present invention is a bit reduction device that performs range processing and quantizes data based on a representative value of input digital data.In a bit reduction device, a representative value of input digital data is quantized in advance, and the quantized representative value is By performing ranging processing on input digital data based on the above, the ranging processing time is reduced, and the price and power consumption of the system are reduced.

[Conventional technology]

In recent years, analog audio signals and video signals have been sampled (sampled), quantized and coded, and recorded and reproduced as so-called PCM (pulse code modulation) signals.

Such PCM signals can be used to compress the amount of information by utilizing the fact that the statistical properties are biased and that there are parts whose importance is low in terms of audiovisual phenomena. It is known that even if bit reduction (bit reduction) is performed by compression / expansion processing (companding processing), signal quality degradation is extremely small.

In consideration of such points, the applicant of the present application has also
JP-A-61-158217, JP-A-61-158218, JP-A-61-158218
No. 158219, the signal transmission device disclosed in Japanese Patent Application Laid-Open No. 61-158220, and the digital signal transmission device disclosed in Japanese Patent Application Laid-Open No. doing.

Here, a signal transmission device using the bit reduction technology disclosed in these publications will be described with reference to FIG. In FIG. 4, the signal transmission device comprises an encoder 50 on the transmission side (or recording side) and a decoder 70 on the reception side (or reproduction side).

The input terminal 51 of the encoder 50, for example, an analog audio signal is sampled at a frequency f _S, the audio PCM signal obtained by performing quantization and coding x (n) is supplied. The input signal x (n) is sent to the predictor 52 and the adder 53, respectively.

Therefore, in the adder 53, the input signal x (n)
By subtracting the prediction signal (n) from
A prediction error signal or a difference output d (n) (in a broad sense), that is, d (n) = x (n)-(n) (1) is output.

Here, the predictor 52 generally has the past p inputs x (n−
p), x (n-p + 1) ‥‥ x (n-1) is used to calculate a predicted value (n) by a linear combination. Becomes Here, α _k (k = 1, 2 ‥‥ p) is a coefficient. Therefore, the prediction error output or the difference output d (n) in a broad sense is It is expressed as

Also, in this signal transmission device, the input digital signal is divided into data within a predetermined time, that is, the input data is divided into blocks each having a fixed number of words l, and the above coefficient is set so that an optimum prediction filter characteristic is obtained for each block. The set of α _k has been selected. This is the difference output (prediction error output) including predictors with different characteristics or adders.
It can be considered that there are a plurality of filters for obtaining the filter, and an optimum filter among the plurality of difference processing filters is selected for each of the blocks. The selection of the optimum filter is performed by calculating the maximum absolute value (peak value) in the block of the output from each of the plurality of difference processing filters or the value obtained by multiplying the maximum absolute value (peak value) by a coefficient. Are performed by comparing with each other, and specifically, each maximum absolute value (or its coefficient multiplied value)
Is selected as an optimal filter for the block. The optimum filter selection information at this time is output from the prediction / range adaptation circuit 61 as mode selection information and sent to the predictor 52.

Next, the difference output d (n) as the prediction error is sent via an adder 54 to bit compression means (ranging processing circuit or floating processing circuit) comprising a shifter (or ranging amplifier) 55 for gain G and a quantizer 56. ), And undergoes a compression process or a ranging process in which the exponent part in the floating point (floating point) display form corresponds to the gain G and the mantissa part corresponds to the output from the quantizer 56, respectively. That is, the ranging amplifier (bit shifter) 55 switches the so-called range by shifting (arithmetic shift) the digital binary data by the number of bits according to the gain G, and the quantizer 56 performs the bit shift. Re-quantization is performed to extract a certain number of bits of the data. Next, the noise shaping circuit (noise shaper) 57
An error between the output and the input of the quantizer 56, that is, a so-called quantization error is obtained by the adder 58, and this quantization error is sent to the predictor 60 via an amplifier (or shifter) 59 having a gain G- ¹ . A so-called error feedback is performed in which a prediction signal of the quantization error is fed back to the adder 54 as a subtraction signal.

Next, the prediction / range adaptation circuit 61 outputs range information based on the maximum absolute value of the difference output from the filter in the selected mode in the block, and sends this range information to the amplifiers (shifters) 55 and 59. Thus, the gains G and G ^-1 are determined for each block.

The prediction / range adaptation circuit 61 sends the mode information to the predictor 60 to select an optimum filter characteristic. The range information from the prediction / range adaptation circuit 61 is extracted from an output terminal 63, and the mode selection information is extracted from an output terminal 64.

Next, the basic operation of the noise prediction processing after the adder 54 will be described. The output d '(n) from the adder 54 is obtained from the difference output d (n) based on the prediction signal of the quantization error (from the noise shaper 57). n), d ′ (n) = d (n) − (n) (4), and the output d ″ (n) from the shifter of the gain G is d ″ (n) = G · d '(N) (5) The output (n) from the quantizer 56 is given by (n) = d '(n) + e (n) where e (n) is a quantization error in the quantization process. The quantizing error e (n) is taken out by an adder 58 of the noise shaper 57, and the quantized error e (n) is obtained through a shifter 59 having a gain of G ^{−1 and} a predictor 60 that obtains a linear combination of past r inputs. The prediction signal (n) of the conversion error is Becomes This equation (7) has the same form as the above equation (2), and the predictors 52 and 60 each have a system function FIR (finite impulse response) filter.

From these equations (4) to (7), the output d (n) from the quantizer 56 is Substituting equation (3) into d (n) of equation (9), The output (n) is taken out via the output terminal 62. Here, z of the above x (n), e (n), (n)
Let X (z) and E (z) (z) be the transformations, respectively. Becomes

Next, the input terminal of the decoder 70 on the receiving or reproducing side
An output (n) from the output terminal 62 of the encoder 50 is transmitted to the 71, or a signal '(n) obtained by recording and reproducing is supplied to the 71. This input signal '(n) is sent to an adder 73 via an amplifier (shifter) 72 having a gain G- ¹ . Output from adder 73 '
(N) is sent to a predictor 74 to become a prediction signal '(n), and this prediction signal' (n) is sent to an adder 73 and added to the output "(n) from the amplifier (shifter) 72. The added output is output from output terminal 75 as decoded output '(n).

The range information and mode selection information output from the output terminals 63 and 64 of the encoder 50 and transmitted or recorded / reproduced are input to the input terminals 76 and 77 of the decoder 70, respectively. Then, the range information from the input terminal 76 is sent to the amplifier (shifter) 72 to determine the gain G- ¹ , and the mode selection information from the input terminal 77 is sent to the predictor 74 to determine the prediction characteristics. The prediction characteristic of the predictor 74 is selected to be equal to the characteristic of the predictor 52 of the encoder 50.

In the decoder 70 having such a configuration, the output “(n) from the amplifier (shifter) 72 is“ (n) = ′ (n) · G ⁻¹ (12), and the output from the adder 73 is ′ (N) is: ′ (n) = ″ (n) + ′ (n) (1
3) Here, the predictor 74 is the predictor 52 of the encoder 50.
By selecting a characteristic equal to Therefore, from equations (12) and (13), Becomes Next, assuming that the z-transforms of '(n) and' (n) are '(z) and' (z), respectively, Becomes Here, assuming that there are no errors in the transmission path and the recording medium, and assuming that '(z) = (z), from the above equations (11) and (16), Becomes

From equation (17), it is clear that a noise reduction effect of G ⁻¹ can be obtained for the quantization error E (z).
(Z) Becomes

[Problems to be solved by the invention]

Here, a specific example of the encoder device 50 in the signal transmission device as described above is shown in FIG. This FIG.
This shows an example of an encoder-side configuration of a system using the above-described prediction filter and block floating (ranging in units of blocks) as a band compression technique of audio signals in so-called CDI and CDROM XA. In FIG. 5, the simplest example is straight
Select either PCM or primary difference PCM in block units,
A case where 16-bit data is compressed to 8 bits (bit reduction) is shown.

In FIG. 5, an audio PCM signal of, for example, 16 bits per word input through the input terminal 51 is converted into a predetermined 1 word (eg, 28 words) in the prediction filter unit.
Straight PCM value and its primary difference P for each unit block
The maximum absolute value of the CM value in each block is obtained. This is because the input PCM signal is supplied to the 1-word delay circuit 81 and is delayed by 1 word, so that the maximum absolute value of the straight PCM value in one block is obtained. And a first-order difference PCM (DPCM) value from a first-order difference processing filter comprising an adder 53 and a first-order difference PCM (DPCM) value.
The maximum absolute value of the DPCM value is obtained. Note that the predictor 52 is 1
It comprises a word delay circuit 52a and an amplifier 52b having a predetermined coefficient. The input PCM signal is delayed by one word in the one-word delay circuit 52a, and a predetermined negative coefficient (for example, -0.9
375) to obtain an inverted predicted output. The inverted predicted output is sent to the adder 53 and added to (substantially subtracted from) the input PCM signal.
I want a DPCM signal.

Absolute maximum PCM value in block and DPCM
The smaller of the maximum absolute values of the values in the block is set as the peak value, and the prediction filter output from which the peak value is obtained is selected as the optimum filter output. This is performed by connecting the selected terminals 83a and 83b of the changeover selection switch (selector) 83 to the selected prediction filter side, and the output from the common terminal 83C of the selector 83 is either block floating or block blocking. It is sent to the cleansing processing unit.

In the ranging process in this processing unit, the peak value is 16
The maximum positive value in the two's complement representation of a bit (+32767)
Is obtained in 6 dB steps, and a ranging amplifier (shifter) 55 selects one word (28 words) in the same block.
The word is amplified by the obtained gain and rounded to a desired value of, for example, 8 bits by the quantizer 56.
Note that the rounding noise (quantization error) generated at the time of quantization is fed back to the adder 54 via a so-called noise shaper 57 to perform noise shaping as described above.

That is, the 16-bit data signal input from the ranging amplifier 55 to the quantizer 56 is divided into upper 8 bits and lower 8 bits, and only the upper 8 bits are taken out and subjected to a so-called rounding process. , And is fed back to the input side adder 54 of the ranging amplifier 55 via the noise shaper 57. Noise shaper 57
Consists of an amplifier 65, an adder 58, an amplifier 59, and a predictor 60 connected in series. The adder 58 subtracts the 16-bit signal from the 16-bit input of the quantizer 56 by shifting the 8-bit output of the quantizer 56 leftward by 8 bits (256 times) by the amplifier 65. Thus, the rounding error (quantization noise) in the quantizer 56 is extracted. This quantization error is
Is amplified by an amplifier 59 having a gain inverse gain (coefficient 2 ^G) (coefficient 2 ^-G) of the ranging amplifier 55 and supplies to the predictor 60. The predictor 60 is a one-word delay circuit 60
The input signal from the amplifier 59 is delayed by one word, amplified and supplied to the adder 54.

By the way, the encoder as shown in FIG. 5 is usually realized by software using a so-called DSP (digital signal processor). In this case, in order to require the longest execution time among the algorithms of the software program for realizing the encoder configuration,
Table 1 shows an example of a general program for determining the gain of the ranging amplifier 55, which is obtained by a general-purpose DSP.

Using the above Table 1 and FIG.
The operation of determining the gain of 55 will be described. First, in step 101, the peak value (peak) which is the smaller value selected by comparing the maximum absolute value of the straight PCM with the maximum absolute value of the primary DPCM. Is determined to be 0 or not, and if Yes, it is determined that there is no signal and the process proceeds to the next process. If No, the process proceeds to Step 102.

In step 102, the selected peak value is doubled (shifted one bit to the left), and the process proceeds to step 103.

In step 103, it is determined whether or not the peak value (peak) shifted to the left by one bit (doubled) is equal to or larger than a maximum absolute value MAX (= 32767) in a 16-bit two's complement expression. Goes to the next process, if No, step 1
Proceed to 04.

In step 104, the output data of the selected prediction filter is doubled (shifted one bit to the left), and the process returns to step 102.

By repeating such a loop, the gain of the ranging amplifier 55 (coefficient = 2 ^G : G is the number of shifts) is obtained.

In this ranging processing routine, the peak value, which is the maximum absolute value in the smaller block, is doubled (shifted to the left by one bit), and then compared with the positive maximum value (+32767) in the 16-bit two's complement representation. And a left shift of up to 15 bits is performed. Therefore, the above-described loop operation is performed 15 times at the longest, and if all instructions are executed in an instruction cycle of 100 ns, a maximum time of about 10.5 μsec is required.

Here, in general, in a software program for processing a PCM signal as described above, one complete process is performed within an allotted time for one sample word in consideration of simplification of hardware, reduction of software burden, and the like. In many cases, a program is designed so as to be simply executed repeatedly for each word. Therefore, for example, when the sampling frequency is 37.8 kHz, it becomes necessary to complete the execution of all the routines for the encoding process within the sampling period (about 26.5 μsec). In the processing algorithm, it consumes a maximum of about 10.5 μsec,
Since this corresponds to about 40% of the sampling period of about 26.5 μsec, it is difficult to complete the execution of all routines within the sampling period.

Further, it is impossible to execute the time-division stereo channel processing within the sampling period because only 80% of the entirety is used only by the ranging processing routine.

On the other hand, general-purpose DSPs that can execute 100 ns instruction cycles are expensive for consumer use, and low-priced, for example, 20 instruction cycles.
It is almost impossible to execute the above algorithm with a DSP of about 0 ns.

Therefore, an object of the present invention is to provide a bit reduction device that can shorten the time of the ranging process with a simple configuration in view of the above-described problem.

[Means for solving the problem]

According to the bit reduction device according to the present invention, a bit reduction device that performs range processing based on a representative value (such as a peak value in a block) of input digital data and then performs quantization to reduce bits is shown in FIG. In this way, the quantizer 7 pre-quantizes the representative value (such as the peak value in a block) of the input digital data, and the ranging amplifier 10 performs a data ranging process based on the quantized representative value. This solves the above-mentioned problem.

[Action]

Range information (bit shift amount) at the time of ranging processing
Is a representative value quantized in advance (such as a peak value in a block)
, The maximum bit shift amount is halved and the ranging processing time can be shortened.

〔Example〕

FIG. 1 is a block circuit diagram showing an embodiment of a bit reduction device according to the present invention, and shows an encoder provided on a transmission side (or a recording side).

An input terminal 1 of the encoder is supplied with an audio PCM signal of a predetermined number of bits (for example, 16 bits) obtained by sampling an analog audio signal at a frequency f _S (for example, 37.8 kHz), and performing quantization and encoding. ing. The input PCM signal is divided into blocks each having a predetermined number of words 1 (for example, every 28 words), and is subjected to prediction filter processing and bit compression processing (ranging or floating processing) in block units. This is done to compress 16 bits to 8 bits.

That is, the input signal is sent as it is to the one-word delay circuit 2 as a straight PCM signal, and at the same time, a prediction error (difference) is obtained by the predictor 3 and the adder (subtractor) 22 to become a differential PCM signal. It is sent to the 1-word delay circuit 4. The straight PCM signal and the differential PCM signal sent to these 1-word delay circuits 2 and 4, respectively, are
While the word (one block) is delayed, each maximum absolute value in one block is detected. The signal from which the smaller one of these maximum absolute values is obtained is selected by the changeover selection switch (selector) 5 and sent to the next ranging processing unit.

Here, the predictor 3 comprises a one-word delay circuit 3a and a coefficient multiplier 3b having a predetermined coefficient (for example, -0.9375), and outputs a so-called primary predicted value (a polarity inversion value thereof). The primary prediction output from the predictor 3 is input to the adder 22
By adding (substantially subtracting) to the PCM signal, a primary differential PCM signal (primary DPCM signal) is obtained.
The signal is sent to the one-word delay circuit 4. Accordingly, the selector 5 selects a signal of the straight PCM signal and the primary DPCM signal, for which the maximum absolute value in the block is smaller, for each block, and sends the selected signal to the adder 6 of the next-stage ranging processing unit. ing. The smaller of the maximum absolute values in the block is hereinafter referred to as a peak value.

The ranging processing unit has a configuration in which a ranging amplifier 10 is arranged at a stage subsequent to the quantizer 7, and this indicates that a ranging process is performed based on a value obtained by previously quantizing the peak value. As described above, the peak value (for example, 16 bits) obtained at the time of the prediction filter processing is quantized in the same range (for example, the 8 bits are extracted).
Then, by performing the ranging process based on the quantized peak value, the maximum value of the shift amount in the ranging process is reduced to, for example, 7 bits, and the above-described loop operation of the ranging process by the left shift of the data is performed. It is reduced to 7 times at the longest. However, when the peak value is equal to or less than the positive maximum value (127) represented by 8 bits in 2's complement representation, it is not necessary to perform the ranging process, so the input data is output as it is via the switch 9. When the value is larger than the positive maximum value (127), the switch 8 is turned on to quantize the peak value to 8 bits, and then the ranging process is performed.

FIG. 2 is a flowchart showing a specific example of the ranging processing routine in the present embodiment corresponding to FIG. 6 described above.

In FIG. 2, in the first step 30, it is determined whether or not the peak value peak is larger than the maximum positive value (127) in the 8-bit two's complement expression (peak> 127). Proceeding to 31, the current PCM data is shifted left by 8 bits. The processing at step 31 is equivalent to the gain ranging amplifier 10 closes the switch 9 of FIG. 1 and 2 ^8.

When YES is determined in the step 30, the process proceeds to the next step 32, where the quantizer 7 extracts the upper 8 bits of the peak value peak. Based on the quantized 8-bit peak value peak, ranging processing similar to steps 102 to 104 in FIG. 6 described above is performed in steps 33 to 35. However, in steps 33 to 35 in FIG. 2, since the peak value peak has been quantized to 8 bits in advance, the left shift for each bit can be a maximum of 7 bits (seven loop operations). (Up to 15-bit left shift), which is almost half, and the processing time can be reduced.

Also in the embodiment of the present invention, so-called error feedback is performed similarly to the example of FIG. 6 described above, and errors before and after quantization are detected by the noise shaper 13 and the quantizer is added via the adder 6. It has returned to 7.

The noise shaper 13 includes a switch 19 connected in parallel to a series circuit of an amplifier 14 and a switch 15, an amplifier 16 and an adder 11 connected in series to the parallel circuit, and a one-word delay circuit 17 and an amplifier 18 connected to the series circuit. It consists of predictors 20 connected in series. The output data from the ranging amplifier 10 is subtracted from the upper 8 bits of the data input to the quantizer 7 in the adder 11 via the amplifier 14, the switch 15 and the amplifier 16 of the noise shaper 13, and the quantization error component Is detected. The amplifiers 14 and 16 are provided to match the order between input and output data of the serial circuit of the quantizer 7 and the ranging amplifier 10, and when the switch 9 is turned on, The switch 15 is turned off and the switch 19 is turned on to bypass the amplifier 14.

The quantization error from the adder 11 is supplied to the adder 6 inserted and connected to the input side of the quantizer 7 via the predictor 20 to perform error feedback. Predictor
The 20 prediction characteristics may match the prediction characteristics (for example, the characteristics of the predictor 3) in the prediction filter unit.

By performing the noise shaping process in this way, the effective bit number of the 16-bit data input to the quantizer 7 is about 9 or 10 bits, and the effective bit number is obtained when the upper 8 bits are extracted by requantization. Is about 1 bit or 2 bits, the lower 8 bits are taken out of the adder 11 as a quantization error and fed back to the adder 6 on the input side of the quantizer 7 to reduce the signal degradation. Can be suppressed.

FIG. 3 shows a characteristic diagram of data distortion rate and output when quantization is performed from 16 bits to 8 bits.

In FIG. 3, a characteristic line (a) shows 16-bit data, a characteristic line (b) shows data obtained by re-quantizing 8 bits when emphasis is applied, and a characteristic line (c) shows emphasis. The figure shows 8-bit requantized data when not applied.

As can be seen from this graph, even if requantization is performed from 16 bits to 8 bits, a dynamic range of approximately 16 bits is secured.

Although some noise is confirmed in the high frequency band, this high frequency data is a band that is hard to recognize perceptually. By applying emphasis (high frequency enhancement), the noise is reduced to a level that does not cause a problem in hearing. can do.

As is clear from the above description, the bit reduction device according to the above-described embodiment, after quantizing the peak value as a representative value of the data in the ranging processing block to a desired bit length in advance in the quantizer 7, Since the ranging process for obtaining the gain of the ranging amplifier 10 is performed using the quantized representative value (peak value), the time spent for the ranging process can be significantly reduced as compared with the related art, and the surplus time can be reduced. Since the time can be allocated to another process, it is possible to improve the audibility, for example. In addition, it is possible to realize bit compression processing including ranging processing with a low-speed DSP without using an expensive high-speed DSP, thereby achieving lower cost and lower power consumption of the system.
Note that, for a low-level signal in which the number of effective bits is equal to or less than the number of bits after quantization, expansion of the dynamic range can be ensured by not performing quantization.

In the above-described embodiment, an example of the bit reduction of 16 bits to 8 bits has been described.
Of course, changes such as bit compression can be made.

〔The invention's effect〕

ADVANTAGE OF THE INVENTION According to the bit reduction apparatus which concerns on this invention, the maximum value of the frequency | count of a bit shift is reduced by performing the ranging process which requires a processing time based on the representative value (peak value in a block etc.) quantized beforehand. , Shortening the processing time. As a result, the surplus time can be allocated to another processing to improve the characteristics. Also, low speed DS
By using P, it is possible to reduce the cost and power consumption of the system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a bit reduction device according to the present invention, FIG. 2 is a flowchart for explaining a ranging processing operation in the embodiment, and FIG. FIG. 4 is a graph showing output characteristics when bit compression is performed on 8 bits. FIG. 4 is a block diagram showing a basic configuration of a conventional bit reduction device.
FIG. 1 is a block diagram showing a specific example on the encoder side of a conventional bit reduction device, and FIG. 6 is a flowchart for explaining a conventional ranging processing operation. 1 input terminal 2,4 l-word delay circuit 3,20 predictor 5 selector 6,11,22 adder 7 quantizer 8,9,15,19 switch 10 Ranging amplifier 12 Output terminal 13 Noise shaper

Claims (3)

(57) [Claims] An input digital signal having a predetermined sampling frequency and a predetermined number of quantization bits is divided into blocks for each predetermined number of words, and a prediction filter means for performing a prediction filter process on a block-by-block basis, and an output from the prediction filter means Quantizing means for requantizing the digital signal into a predetermined number of bits, and ranging processing means for performing floating processing on the requantized digital signal from the quantizing means. A bit reduction device that performs a ranging process based on a requantized digital signal having a bit length from a digital camera. 2. The bit reduction apparatus according to claim 1, wherein an error before and after the quantization by said quantization means is fed back to an input side of said quantization means to perform noise shaping. 3. The re-quantization is not performed on a low-level signal in which the input digital signal has an effective number of bits less than the number of quantization bits by the quantization means. Bit reduction device.