JP2975764B2 - Signal encoding / decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to adaptive differential pulse code modulation used for band compression of audio signals.
The present invention relates to an improvement of a ferential pulse code modulation-ADPCM) system.

For example , Japanese Patent Publication No. 63-5926 (H03)
M 3/04) is a subtractor that calculates the difference between the input signal x _j and the predicted value, and an adaptive type that inputs the output of the subtracter, divides it by an adaptively changing normalization coefficient Δ, and encodes and outputs. A quantizer,
After inputting the output of this quantizer and decoding by the decoder ,
An adaptive inverse quantizer that multiplies by a normalization coefficient and a filter that obtains a prediction value by inputting the result of multiplying the normalization coefficient by the inverse quantizer and obtains a prediction value by using the input or output of the decoder. An adaptive predictive DPCM device having an adaptive predictor for modifying coefficients is disclosed.

Such a technique has an advantage that it is resistant to errors in a transmission line or a storage medium, has good band compression characteristics, and has an extremely small apparatus size.

However, in the technique disclosed in the above publication, the input signal
Value (X _j-X_j-1) Is large
The prediction error e_jBecomes larger and the quantization width (normalization
Number) Δ also increases, so the quantization error increases.
there were.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the prior art, and has as its object to provide means for suppressing an increase in quantization error when encoding an input signal. .

[0006]

In order to solve the above problems, the present invention provides an integrator (1), an adaptive differential pulse code modulation encoder (2), and an adaptive differential pulse modulation decoder (3).
And a differentiator (4), wherein the integrator (1) integrates an input signal and outputs an integrated signal, and the adaptive differential pulse code modulation encoder ( 2) encodes the integrated signal and outputs a coded signal. The adaptive differential pulse modulation decoder (3) decodes the coded signal and outputs a decoded signal. ) Is characterized by adding the inverse filter characteristic of the integrator (1) to the decoded signal and outputting it. Further, according to the present invention, the integrator (1) includes a first multiplier (11),
Adder (12) and feedback means (13, 14)
The first multiplier (11) reduces the magnitude of the input signal to １ ／, and the adder (12) includes the first multiplier (11) and feedback means (13, 14). And outputs an integrated signal by adding the outputs of the first and second outputs, and the feedback means (13, 14) delays the integrated signal and reduces the magnitude to 1/2. Furthermore, the present invention
The first multiplier (11) or the feedback means (13, 14) is configured using a bit shifter.

[0007] Then, the integrator, in order to suppress the overflowing in integrator, a first multiplier for the magnitude of the input signal to 1/2, the size of the output signal of the first multiplier a second multiplier for 1/2, and by feeding back the output of the second <br/> multiplier adder for adding the <br/> output of the first multiplier is It is desirable.

[0008]

According to the above configuration, the value that fluctuates between samples of the input signal is reduced by the integrator placed before the ADPCM encoder, and the prediction error is reduced. Therefore, the value of the quantization width is reduced, and the quantization error can be reduced.

In the integrator, a multiplier or a bit shifter suppresses an overflow of the output of the integrator.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a signal encoding / decoding apparatus according to the present invention;

FIG. 1 shows the schematic diagram of an encoding / decoding device.
1 is an integrator for reducing the variation range of an input signal so that high-frequency components of the signal are hard to pass through, 2 is an ADPCM encoding unit to which the output of the integrator 1 is input, and 3 is the encoding unit 2
A decoding unit 4 for restoring the coded signal to the original signal is a differentiator that allows a large amount of high-frequency components that have passed only a little by the integrator 1 to pass through and restores the original frequency characteristics.

The integrator 1 includes a first multiplier (bit shifter) 11 for reducing the signal input thereto to a half, an adder 12, and an output of the adder 12. It comprises a second multiplier (bit shifter) that feeds back the data to the adder 12 via the delay unit 14 with the size of 1/2, and adds it to the output of the first multiplier 11.

On the other hand, the differentiator 4 includes a third multiplier 41 for doubling the output from the decoding unit 3, a second adder 42 receiving the output of the multiplier 41 as an input, The delay unit 43 delays the output of the conversion unit 3 and outputs the output to the adder 42, and adds the output to the output of the multiplier 41.

In such a configuration, an input signal first passes through the integrator 1 on the encoding side. Thereby, even if the value of the input signal fluctuates greatly between the unit samples, the value fluctuating between the unit samples by the integrator 1 becomes small.

The output of the integrator 1 does not overflow by halving the signal value by the first and second multipliers 11 and 13.

With this configuration, even when a maximum value of, for example, 16 bits is input, the output of the first multiplier 11 becomes 15 bits, and the signal fed back to the first adder 12 is output.
Is also bit-shifted by the second multiplier 13 and the first multiplier 1
1, the output of the integrator 1 does not exceed 16 bits.

Next, the output signal of the integrator 1 is ADPCM.
Encoded by the encoding unit 2. At this time, the input signal to the encoding unit 2 has a small value that fluctuates between unit samples by the integrator 1, so that the encoding unit 2 encodes the signal with high accuracy and a small quantization error. It has become something.

On one decoding side, the data is first decoded by the ADPCM decoding unit 3. And the decoded signal is
The signal is output through a differentiator 4 which is an inverse filter of the integrator 1.

FIG. 2 is a block diagram showing details of the ADPCM encoder 2 and the decoder 3 shown in FIG. In the figure, the encoding unit 2 is configured to input a signal x _n at an arbitrary sampling time.
A prediction signal y _n and the difference d _n in an adder 21 for calculating the following Equation 1, the quantization width determination unit 22 for determining a quantization width delta _n
If, coded value L _n by this quantization width delta _n and the difference d _n
The obtained by the following equation 2, the number 3 and quantizer 23 to obtain quantized values q _n, encoded value from the output of the quantizer 23 L _n
And an encoder 24 for extracting the

[0020]

(Equation 1)

[0021]

(Equation 2)

[0022]

(Equation 3)

The output L _n of the encoder 24 is fed back to the quantization width determination unit 22 changes the quantization width when the next sampling is performed based on the following equation (4).

[0024]

(Equation 4)

In equation (4), the multiplier M (L _n ) is as shown in the following Table 1.
This is a numerical value determined based on (in the case of 4-bit encoding).

[0026]

[Table 1]

[0027] 25 adds the said prediction signal y _n and the output q _n of the quantizer 23, an adder for obtaining the w _n by the following equation (5), the w _n is following through the delay unit 26 It becomes a prediction signal y _{n + 1} at the time of sampling.

[0028]

(Equation 5)

[0029] In this way, the coded value L _n obtained after each at each sampling time is input to the decoding unit 3.

[0030] The decoding unit 3 by the input L _n Table 1
Quantization width determination unit 31 for determining a quantization width delta _n based on
When, the next few by using this quantization width delta _n and the input L _n 6
By 'a decoder 32 for calculating the _n, the quantization value q' quantized value q 'decoded values by adding the _n w' prediction signal y to _{n n}
And an adder 33 that obtains

[0031]

(Equation 6)

[0032] The decoded value w _'n prediction signal y at the next sampling via a delay unit 34' to obtain a _{n + 1.} Note that these operations are represented by Expression 7.

[0033]

(Equation 7)

By the way signal x _n to be input in FIG. 2 are those with a reduced variation range of the original signal by the integrator 1 of Figure 1, the difference i.e. the prediction error d _n obtained by the adder 21 is smaller Has become. Therefore the error of quantization values q _n that obtained <br/> in quantizer 23, that is, the quantization error is smaller coder-decoder unit obtained.

The S / N ratio between the input to the encoding unit 2 and the output signal from the decoding unit 3 is compared with the encoding and decoding performed by the conventional device without the integrator 1 and the differentiator 4.
It was found that the ratio was improved by about 5 to 6 dB, and that the quantization error was reduced audibly.

As described above, according to the present invention , the input signal
If the value (X _j −X _j-1 ) that fluctuates between unit samples is small
Expediently, the smaller the prediction error e _j, quantization width (normalized
(Coefficient ) Δ is reduced, so that the quantization error is reduced.
Can be. Furthermore, it is provided before ADPCM encoding.
Overflow in the integrator can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a signal encoding / decoding apparatus according to the present invention.

FIG. 2 is a block diagram showing one embodiment of an encoding unit and a decoding unit of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Integrator 2 ADPCM encoding part 3 ADPCM decoding part 4 Differentiator

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G10L 9/18 G10L 9/00 H03M 3/04

Claims (3)

(57) [Claims] An integrator (1) and an adaptive difference pulse code changer.
Tone encoder (2) and adaptive differential pulse modulation decoder (3)
And a signal encoding / decoding device including a differentiator (4).
The integrator (1) integrates an input signal to generate an integrated signal.
The adaptive differential pulse code modulation encoder (2)
The adaptive differential pulse modulation decoder (3) encodes the signal and outputs an encoded signal.
And outputs a decoded signal. The differentiator (4) outputs the decoded signal to the integrator (1).
It is characterized by applying an inverse filter characteristic and outputting.
A signal encoding / decoding device. 2. The integrator (1) includes a first multiplier (1).
1), an adder (12), and feedback means (1
3, 14), and the first multiplier (11) reduces the magnitude of the input signal by 1 /
2, the adder (12) is connected to the first multiplier (11)
The outputs of the feedback means (13, 14) are added and an integrated signal is obtained.
And the feedback means (13, 14) outputs the integrated signal
It is characterized by delaying and reducing the size by half.
The signal encoding / decoding device according to claim 1. 3. The first multiplier (11) or a filter (1)
The feedback means (13, 14) uses a bit shifter.
3. The signal according to claim 2, wherein
Encoding / decoding device.