JP2795585B2 - Filter circuit for selective paging receiver - Google Patents

Abstract

PURPOSE:To provide the non-adjustment filter circuit of a selection call receiver which can alter the cut-off frequency of a low pass filter removing RF noise from a base band signal which is IF-detected in the selection call receiver with considerable easiness and without the exchange of circuit parts. CONSTITUTION:The base band signal which is detected in an IF detection circuit 3 is quantized to one bit in a one-bit quantizer 5. The amplitude of a discrete value signal string inputted to a digital filter 6 always becomes '1'. Thus, the filter 6 saving the multiplier of an FIR filter executes filtering. The output of the filter 6 is reproduced to an NRZ code by a digital comparator 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter circuit for removing high-frequency noise from a received baseband signal in a selective calling receiver using a digital signal system. The present invention relates to a non-adjustable filter circuit of a selective call receiver capable of easily switching a cutoff frequency of a filter and extracting only a necessary information signal.

[0002]

2. Description of the Related Art A conventional selective call receiver has a configuration as shown in FIG. A radio wave obtained by FM-modulating a baseband signal is received by an antenna, and high-frequency amplified by an RF circuit. Further, the high-frequency amplified signal is converted into an intermediate frequency by an IF / detection circuit, detected, and demodulated to an original baseband signal. Then, the high frequency noise component is removed from the baseband signal by an analog filter to extract only the information signal component, and further, an NRZ code is obtained by an analog comparator. The original digital signal is decoded from the NRZ code.

[0003]

However, when the conventional selective paging receiver as described above is used in a system management area having a specification in which the code rate of the digital signal is different, the cutoff frequency of the analog filter is set to the code. Need to change according to the rate. This is because, when a selective paging receiver adapted to a low code rate is used in a system area having a high code rate, a necessary information signal is also cut due to a low cutoff frequency of a filter, and transmission errors are reduced. This is because there is a possibility of occurrence.
For example, when a selective call receiver having an analog filter circuit set for 512 bps is used in a digital signal transmission area of 1200 bps, the circuit constant for determining the cutoff frequency of the analog filter is set to 512b.
Unless the signal is changed from ps to 1200 bps, necessary information is removed by this analog filter. The value of the circuit constant of this analog filter is
Although the receiving sensitivity greatly affects the selection and management of this circuit constant, sufficient care must be taken.However, discrete components are susceptible to temperature changes and aging, and the circuit setting is very difficult. is there.

Therefore, if the circuit constant of this analog filter, that is, the cutoff frequency can be switched by a simple operation, as described above, a selective call receiver used in an area having a different code rate is newly added. Obviously, even when used in a region having a different code rate, replacement of components of the analog filter or complicated circuit adjustment can be omitted.

It is an object of the present invention to provide a selective call which can use a digital filter having a simple circuit configuration in place of the conventional analog filter and can eliminate troublesome maintenance such as replacement of parts which is a conventional problem. An unadjusted filter circuit for a receiver is provided.

[0006]

SUMMARY OF THE INVENTION The present invention provides a filter circuit of a selective call receiver for detecting a baseband signal from a received radio wave and decoding transmission information, and a 1-bit quantizer for quantizing the baseband signal by 1 bit. A moving average filter comprising an N-order 1-bit delay element, wherein the passband of the received baseband signal can be changed by changing the frequency of a clock input to the 1-bit delay element.

According to the above configuration, the baseband signal detected and detected is quantized by the 1-bit quantizer, whereby
Each delay element constituting the digital filter is a 1-bit shift register. Further, since the amplitude of the quantized signal is “1”, the coefficient of the multiplier of the filter becomes “1”. The cutoff frequency of the digital filter can be easily changed by changing the frequency of the clock signal input to each delay element.

[0008]

Next, an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram of one embodiment of the present invention, and FIG. 2 is a signal flowchart of a digital filter used in the present invention.

[0009] In FIG.
And amplified by the RF amplifier circuit 2 at a high frequency. Further, after the RF amplification signal is frequency-converted into an intermediate frequency band signal by the IF detection circuit 3, a baseband signal obtained by FM-modulating the carrier is detected. The detected baseband signal is input to the anti-aliasing filter 4, and a high-frequency component equal to or more than の of the sampling frequency f _S of the digital filter 6 described below is removed. The baseband signal from which the high-frequency component has been removed by the anti-aliasing filter 4 is converted to a 1-bit quantizer 5.
And is quantized to “0” and “1”. Further, the quantized data is input to the digital filter 6,
High frequency components are removed. The signal filtered by the filter 6 is reproduced by the digital comparator 7 as an NRZ signal after determining whether or not the number of pulses at 1 / code rate [time] is equal to or less than a predetermined value.

Since the digital filter 6 is a fixed amplitude signal having an input signal amplitude of "1", the filter coefficient of a non-recursive filter (hereinafter referred to as FIR) can be set to 1, and the N-order FIR filter can be used. The intuitive configuration of the filter is as shown in FIG. That is, each of the delay elements 10 ₁ to 10
The output sum of _n-1 is the output y (n) of the digital filter 6. In addition, since the quantized data is 1-bit data, each of the delay elements 10 ₁ to 10 _n−1 can be configured by a simple 1-bit shift register, and the output sum of each of the delay elements 10 ₁ to 10 _n−1 is simple. Required by a simple adder. In addition, a clock signal is input to each of the delay elements 10 ₁ to 10 _n−1 from a clock generator (not shown), and the delay time is adjusted.

The operation of the above configuration will be briefly described. The above-described RF amplification circuit 2 and IF detection circuit 3 perform the same circuit operations as in the conventional example. The baseband signal detected by the IF detection circuit 3 is a signal in which RF noise is superimposed. As described above, the anti-aliasing filter 4 removes a frequency component equal to or more than の of the sampling frequency f _S from the baseband signal detected by the IF detection circuit 3, and this removes the sampling frequency f _S /
This is because, when quantization and decoding are performed while two or more frequency components are included, aliasing distortion occurs due to the sampling theorem. The signal filtered by the anti-aliasing filter 4 is quantized by a 1-bit quantizer 5. This is shown in FIG. 3A shows the baseband signal 11 filtered by the anti-aliasing filter 4, and the interval T shown in the figure is a sampling interval. And FIG.
(B) shows the discrete value data x (n) quantized by the 1-bit quantizer 5. The data x (n) is filtered by the digital filter 6.

Here, _assuming that the discrete input / output signal sequences on the time axis are {x _n } and {y _n }, respectively, the input / output difference equation is as follows.

[0013]

(Equation 1)

A _i and b _j are real constants, and when n <0, x _n
= Y _n = 0, the acyclic digital filter has b _j = 0 for all j, and the z-transform of the above equation is

[0015]

(Equation 2)

## EQU1 ##

Therefore, based on the equation (2), an intuitive construction of the moving average filter when the input signal amplitude is "1" and the output signal amplitude is also "1" is as shown in FIG. According to FIG. 2, the transfer function representing the moving average at N points is given by the following equation (2).
As can be seen from FIG.

[0018]

(Equation 3)

Equation 3

[0020]

(Equation 4)

Substituting and organizing,

[0022]

(Equation 5)

## EQU1 ##

Equation 5 represents frequency characteristics. Furthermore, applying Euler's formula to this equation 5,

[0025]

(Equation 6)

Substituting and organizing,

[0027]

(Equation 7)

## EQU1 ## In this equation 7,

[0029]

(Equation 8)

Represents a frequency amplitude characteristic. This number 8 from ω = 2πf, T = 1 / f S (f S is the sampling frequency) by substituting, if obtaining the cut-off frequency f _C,

[0031]

(Equation 9)

Here,

[0033]

(Equation 10)

In other words,

[0035]

[Equation 11]

Further, when sinNα and sinα are expanded into an infinite series and arranged,

[0037]

(Equation 12)

## EQU4 ## When the root of the equation 12 is set as k, f
_C / f _S = k / Nπ, indicating that the cutoff frequency f _C is proportional to the sampling frequency f _S. That is,
By changing the clock signal (sampling frequency) input to each delay element in FIG. 2, the cutoff frequency of the digital filter 6 can be easily changed.

Then, the number of pulses per unit time 12 (see FIG. 3 (c)) of the output signal of the filter 6 is counted.
If the value is equal to or smaller than the predetermined value, the digital comparator 7 determines and substitutes the NRZ code of the negative voltage signal. The comparison of the predetermined value in the comparator 7 has a hysteresis characteristic. For example, the predetermined values for the determination are two threshold values β ₁ and β ₂ (β ₁ <β ₂ ), and after the output of the filter 6 is once determined to be information “1” (positive electrode voltage signal) by the digital comparator 7, , The number of subsequent pulses is compared with β ₁ as the comparison threshold. Then, the pulse number is newly set to the threshold value β ₁
When it becomes less, we continue to pulse number comparison by changing the threshold and beta _2. This is because the digital filter 6 removes high-frequency components and maintains the effect of removing low-frequency noise.

The NRZ code identified by the digital comparator 7 is decoded into original information by a decoder (not shown).

As described above, by performing 1-bit quantization on the detected baseband signal, a low-pass filter can be formed with a simple digital filter, and the cutoff frequency can be easily changed. For example, if the output of an oscillator having a different transmission frequency is switched by a switch under the control of a CPU or the like and input to each of the delay elements 10 ₁ to 10 _n-1 of the filter 6, the cutoff frequency can be changed. it can. Further, the sampling signal of the 1-bit quantizer 5 and the clock signal input to each of the delay elements 10 ₁ to 10 _{n -1} of the digital filter 6 can have the same clock frequency.

Although the digital filter 6 is an FIR filter in the above embodiment, it may be an IIR filter, and the configuration is not particularly limited in the present invention. Further, the digital filter 6 can be configured by software using a CPU having a storage program, a RAM, and the like.

[0043]

As described above, according to the present invention, the detected baseband signal is quantized by one bit, so that the number of multiplication bits of the digital filter can be reduced to one bit, and the circuit configuration of the filter is extremely reduced. Easy to do. Therefore, a dedicated IC (ASIC: Application specif.
ic integrated circuit), and a conventionally used CPU or NRZ code decoding IC
ASIC in combination with the above can further reduce the size of the entire selective call receiver. Also,
Since the code rate is relatively low, the digital filter can be processed by oversampling, so that the anti-aliasing filter can be composed of a simple first-order low-pass filter using a capacitor and a resistor. The degree can be increased.

Further, the cut-off frequency of the filter can be changed immediately by changing the sampling frequency input to the delay element, so that the work of replacing circuit parts can be omitted as in the prior art, and in the transmission areas having different code rates. When a selective call receiver using the present invention is used, the cut-off frequency of the filter can be easily switched by switching means or the like provided in the receiver body, so that a good radio wave reception state can be maintained.

[Brief description of the drawings]

FIG. 1 relates to an embodiment of the present invention and is a functional block configuration diagram thereof.

FIG. 2 is a signal flow chart of a digital filter used in the present invention.

FIG. 3 is an operation explanatory diagram of the present invention.

FIG. 4 is a diagram of a conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 antenna 2 RF amplification circuit 3 IF detection circuit 4 anti-aliasing filter 5 1-bit quantizer 6 digital filter 7 digital comparator 10 ₁ to 10 _n-1 delay element

Claims (1)

(57) [Claims] 1. A filter circuit for a selective call receiver for detecting a baseband signal from a received radio wave and decoding transmission information, comprising: a 1-bit quantizer for quantizing the baseband signal by 1 bit; A moving average filter comprising a bit delay element, wherein a passband of the received baseband signal can be changed by changing a frequency of a clock input to the one-bit delay element. circuit.