JP2793867B2 - Solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device having a two-dimensional filter function and capable of obtaining a video signal subjected to a filtering process in real time.

[Prior Art] Various techniques for electronically capturing and inputting a subject using a solid-state imaging device such as a CCD image sensor or a MOS image sensor have been developed, and various techniques have been realized as video cameras, electronic still cameras, and the like. .

This type of solid-state imaging device (image sensor) basically includes a plurality of photoelectric conversion units arranged in a matrix, and the signal charges generated and accumulated in each photoelectric conversion unit according to the amount of incident light are converted into a signal. It is configured to sequentially read out in time series via a charge transfer unit (transfer register). Note that the solid-state imaging device such as the MOS image sensor has a function of retaining the signal charges stored therein regardless of reading out the signal charges stored in the photoelectric conversion unit, and is provided separately. Upon receiving the reset signal, the signal charges stored therein are erased.

When a video signal obtained through such an image sensor is handled, as image signal processing, for example, a two-dimensional high-pass filtering process for obtaining a differential value between adjacent pixels to extract an edge component of the image, and an illumination process. Two-dimensional filtering processing for correcting unevenness is often performed. This two-dimensional filtering process is basically performed by executing a convolution integral operation between a target pixel and a plurality of pixels around the target pixel and a predetermined weighting coefficient. That is, in the two-dimensional filtering process, generally, pixel signals read out in time series from a solid-state image sensor are stored in shift registers for n lines, and pixel signals obtained from each of these shift registers are delayed. This is realized by obtaining signals of (n × m) pixels, multiplying each of these signals by a predetermined filter coefficient, and calculating the sum of the signals.

In a CCD image sensor, for example, signal charges respectively accumulated by a plurality of photoelectric conversion units are vertically transferred for each column, and the signal charges read out line by line at an output end thereof are horizontally transferred. The signal charges are read out in time series. The MOS type image sensor is configured so that the signal charges are read out in time series by sequentially designating the photoelectric conversion units in a matrix in the row direction and the column direction.

However, a two-dimensional filtering processing circuit for performing a two-dimensional filtering process on a video signal (signal charge) read out in time series from such an image sensor is constructed as a dedicated hardware circuit, and is provided at an output stage of the solid-state imaging device. It is unavoidable that the configuration of the image processing apparatus becomes considerably large in order to obtain a desired filtering output through connection. In addition, there is a problem that a filtering output cannot be obtained in real time.

[Problems to be Solved by the Invention] As described above, conventionally, when performing a two-dimensional filtering process on a video signal obtained from a solid-state imaging device, a dedicated two-dimensional filtering circuit is provided outside the solid-state imaging device. It has to be constructed as an attachment circuit, and the configuration of the image processing apparatus is unavoidably considerably large, and the filtering output cannot be obtained in real time.

The present invention has been made in view of such circumstances,
Its purpose is to provide a simple and real-time solid-state imaging device that can easily and in real time obtain a filtering output for a video signal required from a solid-state imaging device, particularly a MOS-type image sensor. Is to provide.

[Means for Solving the Problems] A solid-state imaging device according to the present invention includes a plurality of solid-state imaging devices that are arranged in a matrix to form a photoelectric conversion surface and have a function of retaining signal charges regardless of reading out the signal charges. With respect to the photoelectric conversion units, the row position is sequentially selected and designated by shifting one row at a time in units of n consecutive rows of the photoelectric conversion units, and the column is set in units of continuous m columns of the photoelectric conversion units. A photoelectric conversion unit designating means for selecting and specifying the position while sequentially shifting the position by one column is provided. The photoelectric conversion unit designating means corresponds to the signal charges respectively stored in the photoelectric conversion units of n rows and m columns designated by the photoelectric conversion unit designating means. Signal (n ×
m) The signals are read out in parallel through the signal readout lines, and n are read out through these signal readout lines.
The signals from the photoelectric conversion units in the row m and the column m are controlled to be switched in the order of arrangement according to the positional relationship of the photoelectric conversion units in the n rows m and the column m via a switch matrix.
Each of the signals in the column is multiplied by a predetermined coefficient using a plurality of multipliers, and the sum of the multiplied values by these multipliers is obtained through an adder. is there.

In particular, the photoelectric conversion unit, the photoelectric conversion unit designating means described above,
The signal readout line, the switch matrix, the multiplier, and the adder are simultaneously integrated on the same semiconductor substrate to constitute one solid-state imaging device.

[Operation] According to the present invention, a plurality of photoelectric conversion units arranged in a matrix are selected and designated while sequentially shifting their row positions row by row in units of n consecutive rows, and the photoelectric conversion units are designated. Are sequentially selected one row at a time in units of m consecutive columns, and the signal charges stored in the selected and specified photoelectric conversion units are read out by (n × m) signals. Read out in parallel via the line. When two-dimensional filtering is performed using these signal charges, the arrangement of the signal charges read in parallel on the signal read line via the switch matrix is determined by the positional relationship between the n-th row and m-column photoelectric conversion units described above. Therefore, the two-dimensional filtering processing can be performed very easily and efficiently because the data is rearranged in accordance with the filter coefficient and is subjected to the multiplication processing with the filter coefficient.

In addition, by realizing each of these circuit functional units together with the photoelectric conversion unit into a single solid-state imaging device by simultaneously forming an integrated circuit, a dedicated hardware-based two-dimensional filtering circuit can be configured as an external circuit. Thus, a desired filtering output can be obtained directly and in real time from the solid-state imaging device. As a result,
It is possible to sufficiently improve the handling.

Embodiment Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of a solid-state imaging device according to an embodiment, and 1 is a solid-state imaging device main body. The solid-state imaging device main body 1 is configured such that a plurality of photoelectric conversion units 2 mainly composed of photodiodes that generate signal charges according to the amount of incident light are used as pixels, and these photoelectric conversion units 2 are arranged in a matrix. . The plurality of photoelectric conversion units 2
Is a row selection line driven under the control of the vertical register 3.
The configuration is such that a signal corresponding to the signal charge stored and selected in units of rows via 3a is output to signal readout lines 3b arranged in the column direction.

That is, each of these photoelectric conversion units 2 is, for example, as shown in FIG. 2, a photodiode 2a that generates a signal charge according to the amount of incident light, and is connected in parallel to the photodiode 2a.
A MOS switch 2b for receiving a reset signal and erasing the signal charge stored in the photodiode 2a, an amplifier 2c for generating a signal corresponding to the signal charge stored in the photodiode 2a, and the row selection line 3a A MOS switch 2d that conducts upon receiving a signal read command via the switch 2b and outputs a signal charge from the amplifier 2c onto a signal read line 3b.
Respectively.

Thus, the vertical register 3 for selecting and specifying the photoelectric conversion units 2 on a row-by-row basis uses three consecutive rows of photoelectric conversion units 2 here.
It is configured such that the designated position is selected and designated while being sequentially shifted line by line. The output terminals from the photoelectric conversion units 2 selected and designated in row units in this manner are respectively cyclically connected to three signal readout lines 3d provided along the columns of the photoelectric conversion units 2 in the column direction. It is connected. As a result, the signal outputs from the photoelectric conversion units 2 in the three rows selected and designated as described above are read out in parallel to the three signal readout lines 3d described above for each column.

Note that the above-described selection designation of the photoelectric conversion unit 2 in units of three rows is performed on the assumption that the two-dimensional filtering process is performed in units of (3 rows × 3 columns) pixels as described later. Therefore, in general, when performing a two-dimensional filtering process in units of (n rows × m columns) pixels,
The vertical register 3 is driven and controlled so as to designate the photoelectric conversion unit 2 with n rows as one unit, and signal read lines arranged along the column direction of the photoelectric conversion unit 2 respectively.
3b will be provided n each. The signal outputs from the photoelectric conversion units 2 arranged in the column direction are connected to the n signal read lines 3b so as to be read cyclically.

Thus, three (generally, n) signal readout lines respectively arranged along the row of the photoelectric conversion unit 2 in the column direction.
A gate circuit 5 selectively turned on by the horizontal register 4 is provided at each output end of 3b.
The horizontal register 4 drives these gate circuits 5 on every three consecutive columns along the above-mentioned photoelectric conversion unit 2,
The signal on the signal read line 3b is selectively read. The ON drive of the gate circuit 5 using these three columns as one unit is shifted one column at a time as the target area to be subjected to the two-dimensional filtering process moves. Here, as described above, it is assumed that the two-dimensional filtering process is performed in units of (3 rows × 3 columns) pixels, so that the gate circuit 5 is turned on in units of 3 columns. However, when the two-dimensional filtering process is performed in units of (n rows × m columns) pixels, the gate control is performed using m columns as one unit.

The signal readout lines 3b from the respective columns of the photoelectric conversion unit 2 that are subjected to the gate control in this manner are integrated into every third column to be integrated into one. That is, the three signal read lines 3a arranged along each column of the photoelectric conversion unit 2 are connected in common except for the signal line 3b from which signals are simultaneously read via the gate circuit 5. Here, the signal lines are arranged in nine signal lines corresponding to (3 rows × 3 columns). In general, (n rows × m
(N × m) signal lines corresponding to each column.

The signal from the photoelectric conversion unit 2 in the row designated by the above-described vertical register 3 and the column in which the gate circuit 5 is turned on, via the signal readout line 3b collected via the gate circuit 5 in this manner. Charges, that is, signal charges from the photoelectric conversion units 2 in n rows and m columns (here, 3 rows and 3 columns) are read in parallel. Then, under the control of the vertical register 3 and the horizontal register 4, the photoelectric conversion units 2 in n rows and m columns from which signal charges are read out are sequentially shifted by one pixel. This shift control is, for example, a control in which the photoelectric conversion units 2 arranged in a matrix are sequentially shifted in the column direction, and a shift of one pixel is performed in the row direction when the shift processing of one row is completed. This is done by repeatedly executing over an area.

Thus, the signal charges from the photoelectric conversion units 2 in 3 rows and 3 columns read in parallel in this manner are input to the switch matrix 6 which forms a (9 × 9) switch circuit. Each switch element of this switch matrix 6
For example, as illustrated in FIG. 3, each of them is constituted by a MOS switch 6c for selectively connecting a row line 6a indicating a signal input line and a column line 6b indicating a signal output line. Due to such selective conduction of the MOS switch 6c, the aforementioned 9
The output destination of the signal read via the signal read line 3b is selected and determined. In the switch matrix 6 configured as described above, the signal charges from the photoelectric conversion units 2 in three rows and three columns read in parallel via the nine signal read lines 3b correspond to the positional relationship between the pixels. Are converted and output to the two-dimensional filter unit 7.

The operation (function) of the switch matrix 6 will now be described in more detail. The (3 rows × 3 columns) photoelectric conversion units which are read in parallel from the solid-state imaging device main body 1 via the nine signal read lines 3b described above. Which signal readout line from pixel 2 (pixel signal corresponding to the signal charge)
Whether the photoelectric conversion unit 2 is output on 3b depends on where (3 rows × 3 columns) the photoelectric conversion unit 2 is selected and designated by the vertical register 3 and the horizontal register 4.

For example, assuming that the nine signal read lines 3b described above are distinguished as A, B, to I, the signal output from the signal read lines 3b arranged along the photoelectric conversion unit 2 in the first column is a signal line. A, B, and C, the signal output from the signal readout line 3b disposed along the photoelectric conversion unit 2 in the second column is the signal line D, E,
The signal output from the signal readout line 3b disposed along the photoelectric conversion unit 2 in the third column is output to the signal lines G, H, and I, respectively. The signal output from the signal readout line 3b disposed along the photoelectric conversion unit 2 in the fourth column is again the signal line
A, B, and C, the signal output from the signal readout line 3b disposed along the photoelectric conversion unit 2 in the fifth column is again output to the signal line D,
It will be output to E and F. Therefore, depending on which column is selected and designated by the horizontal register 4, the signal lines A, B,.
I, the arrangement of the signals read out on the photoelectric conversion unit 2
Are displaced as a set corresponding to the column of the above, and the order is changed with respect to the arrangement of the columns.

The signals on the three signal readout lines 3b arranged along each column of the photoelectric conversion unit 2 also change cyclically depending on which row is selected and designated by the vertical register 3. Therefore, even on the three signal lines, the arrangement of the signals on those signal lines changes according to the row selected and designated by the vertical register 3.

The switch matrix 6 indicates the arrangement of signals that change in accordance with the position of the photoelectric conversion unit 2 selected and designated by the vertical register 3 and the horizontal register 4 in the output lines a, b, and
(I), (k) in three lines that are always continuous with respect to i, that is, (l-1) line, l line, and (l + 1) line.
The replacement processing is performed according to the positional relationship between the (−1) th, kth, and (k + 1) th photoelectric conversion units 2. As a result, signal charges (image signals corresponding to signal charges) from the photoelectric conversion unit 2 having the following pixel positional relationship are always obtained on the output lines a, b, to i of the switch matrix 6. Become.

Output line a; (1-1) line, (k-1) th output line b; (1-1) line, kth output line c; (1-1) line, (k + 1) th output line d; Line, (k-1) th output line e; l line, kth output line f; l line, (k + 1) th output line g; (l + 1) line, (k-1) th output line h; (l + 1) Line, k-th output line i; (l + 1) line, (k + 1) -th The control of the switch matrix 6 for exchanging such signal lines is selected and designated by, for example, the vertical register 3 and the horizontal register 4 described above. The selection drive may be performed as follows according to the position where the row position and the column position of the photoelectric conversion unit 2 are selected.

Thus, the two-dimensional filter unit 7 receives the signals of the rearranged signal arrangement (3 rows × 3 columns) via the switch matrix 6 and executes two-dimensional filtering. That is, the two-dimensional filter unit 7 includes a plurality (nine) of multipliers 7a, 7b, to 7i for inputting the above-mentioned (3 lines × 3 pixels) signal charges in parallel, and the respective multipliers 7a, It comprises a coefficient register 8 for giving predetermined filter coefficients to 7b and 7i, respectively, and an adder 9 for obtaining the sum of signals (multiplied values) from the multipliers 7a, 7b and 7i.

The multipliers 7a, 7b, to 7i of the two-dimensional filter unit 7 multiply (3 rows × 3 columns) signals given from the switch matrix 6 by filter coefficients set in the coefficient register 8, respectively. It is. These multipliers 7a, 7
The sum of the multiplied outputs (coefficient operation results) obtained by b and 7i is obtained by the adder 9, so that the two-dimensional filtering result for the signal obtained from the (3 rows × 3 columns) photoelectric conversion unit 2 is obtained. It is supposed to be. The filter coefficients set in the coefficient register 8 are preset in accordance with the contents of the two-dimensional filtering process. The output from the adder 9 as a result of the filtering process is externally output as a filtering output of the solid-state imaging device via an output buffer 10.

Here, the signal from the central pixel determined via the switch matrix 6 is output as it is via the output buffer 11 as a signal charge of the target pixel, that is, a normal signal output from the solid-state imaging device body 1. It has become.

With such two outputs, the solid-state imaging device body 1
The raw signal charge (video signal) imaged at and the two-dimensional filtered video signal described above are obtained in synchronization with each other. In other words, a two-dimensional filtered output is determined for the raw video signal in real time.

Thus, according to the solid-state imaging device in which such a circuit function unit (two-dimensional filtering function) is simultaneously integrated, the image signal subjected to the two-dimensional filtering as the device output is processed in real time together with the raw image signal. Can be obtained. Moreover, in the coefficient register 8,
By simply setting a filter coefficient according to the filtering specification in advance, a desired filtering output can be directly obtained as an element output. Therefore, it is not necessary to separately implement hardware as a part of the image processing apparatus as in the related art.
In addition, the real-time property of the filtered signal can be sufficiently ensured, and the usability can be greatly improved.

In addition, since it is relatively easy to integrate the above-described two-dimensional filtering function with the solid-state imaging device main body 1 simultaneously with the current semiconductor manufacturing technology, the configuration of the solid-state imaging device itself does not become so complicated. There are advantages. Therefore, the configuration of a video camera or an electronic still camera constructed using such a solid-state imaging device can be greatly simplified.

Note that the switch matrix 6 and the two-dimensional filter unit 7 described above can be configured as circuit elements independent of the solid-state imaging device body 1. Even in this case, the number of signal lines connecting the solid-state imaging device main body 1 and the switch matrix 6 only needs to be provided at most according to the number of pixels to be subjected to the two-dimensional filtering processing. Since the control of the signal reading for the unit 2 can be executed in exactly the same manner, the effect that the processing efficiency is very good and the form of the control for the filtering process is very simple can be obtained.

By the way, in the above-described embodiment, the switching of the signal lines is controlled by using the switch matrix 6 using the (9 × 9) switch elements. For example, the switch matrix 6 may be configured as shown in FIG. Is also possible. That is, the reading of the signal charge from the photoelectric conversion unit 2 is performed as follows.
As described above, the processing is performed in units of three rows and three columns. Therefore, as shown in FIG.
Are divided into a first switch matrix group 6a and a second switch matrix group 6b. The first switch matrix group 6a replaces the signal lines in units of three columns of nine signal readout lines 3b, and the second switch matrix group 6b replaces the signal lines in three rows. To do.

In this case, the first switch matrix group 6a is set according to the row selection mode of the vertical register 3 respectively. For the second switch matrix group 6b, according to the column selection mode of the horizontal register 4, It is only necessary to perform the on-control as follows.

By configuring the switch matrix 6 in this manner, the number of MOS switches required there can be reduced, which is very effective in simplifying the configuration. In addition, the switch matrix 6
By configuring as shown in the figure, for example, the first switch matrix group 6a is controlled according to the output of the vertical register 3, and the second switch matrix group 6b is controlled according to the output of the horizontal register 4. This makes it possible to easily construct the control system.

Note that the present invention is not limited to the above-described embodiment. In the embodiment, two (3 lines × 3 pixels) signal charges
Although it has been described that dimensional filtering is performed,
In general, it is of course possible to perform (n lines × m pixels) two-dimensional filtering processing. In addition, when filter specifications for performing the two-dimensional filtering process are fixedly set, it is also possible to set them in advance as ROM data or the like. It is also possible to reverse the input / output relationship in the switch matrix shown in FIG. In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[Effects of the Invention] As described above, according to the present invention, it is possible to easily and efficiently perform a two-dimensional filtering process on a signal charge (image signal) read from a photoelectric conversion unit (solid-state imaging device body), Control of signal readout from the photoelectric conversion unit for the filtering process is also very simple. Further, by simultaneously integrating the two-dimensional filtering function together with the photoelectric conversion unit, it is possible to realize a solid-state imaging device capable of obtaining its filtering output in real time. In addition, the solid-state imaging device can be configured to incorporate the two-dimensional filtering function very effectively and obtain a desired filtering output. As a result, it is possible to greatly simplify the configuration of a video camera or an electronic still camera constructed using this type of solid-state imaging device, and to achieve a great effect in practical use such as simplification of handling. Can be played.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a diagram illustrating a configuration example of a photoelectric conversion unit in the embodiment device, and FIG. FIG. 4 is a diagram showing an example of a switch element, and FIG. 4 is a diagram showing a configuration example of a switch matrix showing another embodiment of the present invention. 1. Solid-state image sensor main body 2. Photoelectric conversion unit 3. Vertical register 3a Row selection line 3b Signal readout line
4 ... horizontal register, 5 ... gate circuit, 6 ... switch matrix, 7a, 7b,-7i ... multiplier, 8 ... filter coefficient register, 9 ... adder, 10, 11 ... output buffer.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/30-5/335

Claims (2)

(57) [Claims] 1. A plurality of photoelectric conversion units which are arranged in a matrix to form a photoelectric conversion surface and have a function of retaining signal charges regardless of reading out the signal charges, and a series of these photoelectric conversion units. The row position is set to 1 in units of n rows.
A photoelectric conversion unit designating means for selecting and designating while shifting each row, and sequentially selecting and designating the column position by sequentially shifting one column at a time in units of m columns of the photoelectric conversion unit; (N × m) signal readout lines for reading out in parallel signals corresponding to the signal charges respectively stored in the photoelectric conversion units of n rows and m columns designated by A switch matrix for switching and controlling the readout and readout signals from the photoelectric conversion units in n rows and m columns in accordance with the positional relationship of the photoelectric conversion units in n rows and m columns, and a switch matrix for controlling the switch matrix. A plurality of multipliers for multiplying the respective signals of the n rows and m columns by predetermined coefficients, and an adder for obtaining a sum of respective multiplied values by the multipliers. A solid-state imaging device. 2. The method according to claim 1, wherein the photoelectric conversion unit, the photoelectric conversion unit designating means, the signal readout line, the switch matrix, the multiplier, and the adder are simultaneously integrated on the same semiconductor substrate. The solid-state imaging device according to (1).