JP4232485B2 - Read address control method and apparatus, semiconductor system, and imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method and apparatus for performing read address control on a semiconductor device comprising a basic cell in which unit elements are arranged and a decoder for selecting a unit element to be read, and the control device and the semiconductor device. And an imaging device as a semiconductor device. For example, the present invention relates to an address control technique suitable for application to a timing generator that performs readout control of an imaging device and an imaging system that includes a timing generator and an imaging device.
[0002]
[Prior art]
An amplification type solid-state imaging device (APS; also called Active Pixel Sensor / gain cell), which is a kind of XY address type solid-state imaging device, is an active device (MOS transistor) such as a MOS structure in order to give the pixel itself an amplification function. ) To form a pixel. That is, the signal charge accumulated in the photodiode which is a photoelectric conversion element is amplified by the active element and read out as image information.
[0003]
In this type of XY address type solid-state imaging device, for example, a large number of pixel transistors are arranged in a matrix, and accumulation of signal charges corresponding to incident light is started for each line (row) or for each pixel. A current or voltage signal based on the accumulated signal charge is sequentially read out from each pixel by addressing (see, for example, Patent Documents 1 to 4).
[0004]
[Patent Document 1]
JP 11-239299 A
[Patent Document 2]
Japanese Patent Laid-Open No. 2001-069408
[Patent Document 3]
JP 2001-298748 A
[Patent Document 4]
JP 2003-031785 A
[0005]
As described above, in the XY address type solid-state imaging device, a CCD can read out signals from pixels at arbitrary positions by addressing, and sequentially read out signal charges obtained from the pixels by selecting the pixels with a shift register. Unlike the (Charge Coupled Device) type image sensor, the pixel signal reading order can be set relatively freely.
[0006]
For example, in a still image imaging technique represented by a digital still camera, a multi-pixel CMOS solid-state image sensor is used as an imaging device, and a still image is obtained by independently reading out pixel information of all pixels. Is well known, but in addition to this mode, for example, a “decimation readout mode” that reads out several rows or columns at a time, for example, selects several rows or columns (not limited to adjacent pixels). Thus, an operation such as “addition read mode” in which the data is read out, added and output can be performed.
[0007]
In the thinning readout mode, for example, when the subject is being confirmed (monitoring mode), a rough image (low resolution image) corresponding to the number of pixels of the liquid crystal monitor is output, or pixel information is thinned out for moving images. This is used when the information amount is reduced and transmitted. The addition reading mode is used for the purpose of expanding the dynamic range by outputting signals from a plurality of rows (for example, two rows) and adding them.
[0008]
Even with a CCD type image sensor, a thinning readout mode and an addition readout mode can be used. However, the signal charges obtained from the pixels can be read out only in order by selecting the pixels with a shift register. After reading out pixel information from the image sensor for all pixels, the pixel information is thinned out or added by an external signal processing circuit. On the other hand, the XY address type image sensor has an advantage that pixel information thinning-out processing and addition processing can be substantially performed on the imaging device side, and an external signal processing circuit can be omitted.
[0009]
[Problems to be solved by the invention]
However, in order to actually have a large degree of freedom in the order of reading, a control mechanism that performs address designation according to each mode is required. For example, a row or column selection circuit uses a decoder instead of a shift register. This is because in the shift register, selection of rows and columns needs to be in a certain order, and arbitrary rows and columns cannot be freely selected.
[0010]
When a decoder is used, an arbitrary row or column can be selected by specifying an absolute address (actual address of the imaging unit). However, when there are a plurality of reading modes such as the thinning-out reading mode and the addition reading mode, it is necessary to generate an absolute address according to each reading mode, the setting is complicated, and a design error tends to occur in detail. There is a problem.
[0011]
Further, there is a case where a reverse reading mode for performing reverse reading is required for the purpose of preventing the image from being inverted on the monitor when the camera portion is rotated 180 degrees. The reverse direction reading mode is a mode in which scanning is performed in the reverse direction with respect to the order of address scanning in the forward direction reading mode. For example, in the forward reading mode, the row and column addresses are scanned in order from the smallest, and in the backward reading mode, the row and column addresses are scanned from the larger to the smaller.
[0012]
Here, in order to implement the thinning and addition reading modes in addition to the reverse direction reading mode, it is necessary to define inverted reading for each address generation method. That is, an up counter for incrementing the address is prepared in the forward reading mode, and a down counter for decrementing is prepared in the backward reading mode.
[0013]
In addition, there are various readout modes such as an addition readout mode that outputs signals from multiple lines and expands the dynamic range, and a mode that outputs only the central part of the screen. There is also the handling of dummy rows that output dummy signals. For this reason, mounting other operation modes with respect to the reverse direction reading mode is problematic in that the design is complicated, design errors are likely to occur, and the scale of the address generation circuit increases.
[0014]
The above-described problem can occur not only in a system using an imaging device but also in a semiconductor system including a semiconductor device having a certain degree of freedom in specifying a read address, such as a semiconductor memory.
[0015]
The present invention has been made in view of the above circumstances, and allows readout to be implemented in other operation modes such as the thinning readout mode with respect to the backward readout mode without increasing the circuit scale for addressing. An object is to provide an address control method and apparatus, a semiconductor system, and an imaging device.
[0016]
[Means for Solving the Problems]
  That is, a read address control method according to the present invention is a method for setting an address value to be read for a semiconductor device including a basic cell in which a plurality of unit elements are arranged and a decoder. In the direction reading mode, the address value system obtained by gradually changing the address value in the forward direction is supplied to the decoder, and in the backward reading mode, the address value obtained by gradually changing the address value in the forward direction. Is used to obtain an address value that is gradually changed in the reverse direction, and a system of the address value that is gradually changed in the reverse direction is supplied to the decoder.As described above, the control unit performs switching control of the address value system. At this time, each address value in the forward reading mode and the backward reading mode is taken into one input terminal of the control unit, and a specific address value is taken into the other input terminal of the control unit. The address value system switching control is executed by selecting and outputting the address value input to any one of the input terminals.
[0017]
In other words, in the reverse reading mode, while performing the address counting operation similar to that in the forward reading mode, using this count value, an address value that is gradually changed in the reverse direction is obtained, and this is supplied to the decoder. Supply. As a specific method of “substantial”, for example, a method of obtaining a difference between a count value obtained by performing a forward count operation and a predetermined initial value is simple. is there.
[0018]
“Supply the address value system to the decoder” means that the address value itself is not limited to being directly supplied to the decoder. For example, this address value is decoded and another address value is supplied, or an address value (for example, a fixed address value) different from this address value is temporarily supplied in combination with another mode. It also means to do.
[0019]
A read address control apparatus (for example, a timing generator) according to the present invention is an apparatus that implements the read address control method according to the present invention, and includes a forward address generation unit that gradually changes an address value in a forward direction, A reverse address generation unit that gradually changes the address value in the reverse direction using the address value generated by the address generation unit, and a system of address values generated by the forward address generation unit in the forward read mode is a decoder. And a control unit that performs switching control so that the system of address values generated by the reverse address generation unit is supplied to the decoder in the reverse read mode.
[0020]
A semiconductor system according to the present invention includes a read address control device according to the present invention and a semiconductor device that receives an address designation from the read address control device.
[0021]
The invention described in the dependent claims defines further advantageous specific examples of the read address control device and the semiconductor system according to the present invention.
[0022]
  Here, the control unitAn address value generated by the forward address generation unit or the reverse address generation unit is input to one input terminal, and a specific address value is input to the other input terminal. Selection of dummy rows (columns) and other arbitrary rows (columns) (including rows and columns that are not substantially read) by providing a switching selection unit that selects and outputs the address value input to the terminal Realize combination with modeTo do.
[0023]
In addition, when the forward address is generated, the address value obtained by the difference between the address value itself and the initial value does not correspond to the real address of the basic cell, and is supplied to the decoder. Alternatively, selection of a row (column) that is substantially not read out may be realized.
[0024]
In addition, an imaging device as a semiconductor device, which is a target for performing the read address control, and an imaging system using the imaging device can be extracted as an invention. In this case, regarding the arrangement of the light-receiving pixels and the light-shielding pixels in the imaging device and the arrangement of the color separation filters for color imaging, all of them should be symmetrical in the scanning direction (that is, the reading direction). Is desirable. As for the arrangement of the light receiving pixels and the light shielding pixels, the light shielding pixels are arranged only on either the front end side or the rear end side in the reading direction, and both the forward reading mode and the backward reading mode are You may make it read from the light-shielding pixel distribute | arranged only to one side.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case where the present invention is applied to a CMOS image sensor, which is an example of an XY address type solid-state imaging device, will be described as an example.
[0026]
<Configuration of solid-state imaging device>
FIG. 1 is a schematic configuration diagram of a CMOS solid-state imaging device according to an embodiment of the present invention. The solid-state imaging device 1 is adapted as an electronic still camera that can capture a color image. In the still image capturing mode, a mode for sequentially reading all pixels is set. In addition, as a special shooting mode different from the normal still image mode, a thinning readout mode that reads out several rows and columns while skipping several rows, an addition readout mode that selects and outputs several rows and columns, etc. A special readout mode is set in which the order of reading out pixel signals is different from that in the normal still image mode.
[0027]
When reverse reading is required for the purpose of preventing the image from being inverted on the liquid crystal monitor when the camera body is rotated 180 degrees, the reverse reading mode is used to reverse the normal order. Is also available. A mode in which the reverse reading mode is combined with the above-described thinning-out reading mode and addition reading mode can also be set.
[0028]
The solid-state imaging device 1 includes an imaging unit in which pixels including light receiving elements that output a signal corresponding to the amount of incident light are arranged in rows and columns (that is, in a two-dimensional matrix), and a signal output from each pixel is a voltage. It is a signal and is a column type in which a CDS (Correlated Double Sampling) processing function section is provided for each column. That is, as illustrated in FIG. 1A, the solid-state imaging device 1 includes an imaging unit (pixel unit) 10 in which a plurality of unit pixels 3 (an example of unit elements) are arranged in rows and columns, and an imaging unit 10. A drive control unit 7 provided outside and a CDS processing unit (column circuit) 26 are provided. As the drive control unit 7, for example, a horizontal scanning circuit 12 and a vertical scanning circuit 14 are provided.
[0029]
In FIG. 1A, some of the rows and columns are omitted for the sake of simplicity, but in reality, tens to thousands of pixels are arranged in each row and each column. In addition, a timing generator (an example of a read address control device) 20 that supplies a pulse signal at a predetermined timing to the horizontal scanning circuit 12, the vertical scanning circuit 14, and the CDS processing unit 26 is provided as another component of the drive control unit 7. It has been. Each element of the drive control unit 7 is integrally formed in a semiconductor region such as single crystal silicon together with the imaging unit 10 using a technique similar to the semiconductor integrated circuit manufacturing technique, and is a solid-state imaging that is an example of a semiconductor system. It is configured as an element (imaging device).
[0030]
Note that the timing generator 20 may be provided as another semiconductor integrated circuit independently of other functional elements such as the imaging unit 10 and the horizontal scanning circuit 12. In this case, an imaging device which is an example of a semiconductor system is constructed by the imaging device including the imaging unit 10 and the horizontal scanning circuit 12 and the timing generator 20. This imaging device may be provided as an imaging module in which peripheral signal processing circuits, power supply circuits, and the like are also incorporated.
[0031]
The unit pixel 3 is connected to a vertical scanning circuit 14 via a vertical control line 15 for selecting a vertical column and a CDS processing unit 26 via a vertical signal line 19. The horizontal scanning circuit 12 and the vertical scanning circuit 14 are configured to include, for example, a decoder, and start a shift operation (scanning) in response to a driving pulse supplied from the timing generator 20. The vertical control line 15 includes various pulse signals for driving the unit pixel 3.
[0032]
A CDS processing unit 26 as a column circuit is provided for each column, receives a signal of pixels for one row, and processes the signal. For example, on the basis of two sample pulses such as the sample pulse SHP and the sample pulse SHD given from the timing generator 20, the signal level immediately after the pixel reset is applied to the voltage mode pixel signal input via the vertical signal line 19 ( A noise signal component called fixed pattern noise (FPN) or reset noise is removed by performing a process of taking a difference between the noise level and the signal level. Note that an AGC (Auto Gain Control) circuit, an ADC (Analog Digital Converter) circuit, or the like may be provided in the same semiconductor region as the CDS processing unit 26 as necessary after the CDS processing unit 26.
[0033]
The horizontal scanning circuit 12 defines a horizontal readout column (selects an individual column circuit in the CDS processing unit 26), and a CDS processing unit 26 according to a readout address defined by the horizontal decoder 12a. And a horizontal drive circuit 12b for guiding each signal to the horizontal signal line 18. The vertical scanning circuit 14 defines a vertical readout row (selects a row of the imaging unit 10), and controls the unit pixel 3 on the readout address (row direction) defined by the vertical decoder 14a. And a vertical drive circuit 14b that drives the line by supplying pulses. Note that the vertical decoder 14a selects a row for electronic shutter, in addition to a row from which a signal is read. The timing generator 20 outputs a horizontal address signal to the horizontal decoder 12a and a vertical address signal to the vertical decoder 14a, and each decoder 12a, 14a receives it and selects a corresponding row or column.
[0034]
The voltage signal processed by the CDS processing unit 26 is transmitted to the horizontal signal line 18 through a horizontal selection switch (not shown) driven by a horizontal selection signal from the horizontal scanning circuit 12, and is input to the output buffer 28. The image signal S0 is supplied to the external circuit 100. That is, in the column-type solid-state imaging device 1, the output signal (voltage signal) from the unit pixel 3 is output in the order of the vertical signal line 19 → CDS processing unit 26 → horizontal signal line 18 → output buffer 28. The drive is such that the pixel output signals for one row are sent in parallel to the CDS processing unit 26 via the vertical signal line 19, and the signals after the CDS processing are serially output via the horizontal signal line 18. The vertical control line 15 controls selection of each row.
[0035]
As long as each vertical column or horizontal column can be driven, each pulse signal is arranged in the row direction or the column direction with respect to the unit pixel 3, that is, a driving clock line for applying the pulse signal. The physical wiring method is free.
[0036]
As the external circuit 100 of the solid-state imaging device 1, a circuit configuration corresponding to each photographing mode is adopted. For example, as shown in FIG. 1B, an A / D (Analog to Digital) conversion unit 110 that converts an analog imaging signal S0 output from the output buffer 28 into digital imaging data D0, and A / D conversion A digital signal processor (DSP) 130 that performs digital signal processing based on the imaging data D0 digitized by the unit 110. The digital signal processing unit 130 performs, for example, color separation processing to generate image data RGB representing each image of R (red), G (green), and B (blue), and outputs other signals to the image data RGB. Processing is performed to generate image data D2 for monitor output.
[0037]
The external circuit 100 also includes a D / A (Digital to Analog) converter 136 that converts the image data D2 digitally processed by the digital signal processor 130 into an analog image signal S1. The image signal S1 output from the D / A converter 136 is sent to a display device such as a liquid crystal monitor (not shown). The operator can perform various operations while viewing the display image of the display device.
[0038]
<Address control; first example>
FIG. 2 is a diagram illustrating a first embodiment of address control for the imaging unit 10 of the solid-state imaging device 1 illustrated in FIG. 1. Here, FIG. 2A shows an example of an address assigned to a row of the imaging unit 10. FIG. 2B shows an example of an extended address signal generation circuit 200 for implementing the address control method of the first embodiment. The extended address signal generation circuit 200 is incorporated in the timing generator 20.
[0039]
In each of the first to third embodiments described below, vertical address control for controlling row selection will be described. However, not limited to this, horizontal address control for controlling column selection is described. Is equally applicable.
[0040]
As shown in FIG. 2A, the real address means an address number on the imaging unit 10. The imaging unit 10 is assigned real addresses 0 to 554 as the effective image area 10a in the vertical direction.
[0041]
In addition, a dummy row (real address 555) for one row is assigned to a higher address of the real address 554 in the effective image area 10a, and the basic cell 10b of the imaging unit 10 is configured. The pixels in the dummy row are assigned as pixels that continue to be selected after the reading of the effective image area 10a is completed in both the forward reading mode and the backward reading mode. For example, in both the forward direction reading mode and the backward direction reading mode, the address 555 is set as a dummy row to be selected during one screen scan until returning to the first row of the next screen (so-called blanking period). Assign fixedly.
[0042]
Here, in the forward reading mode in which the relative addresses are sequentially read as 0, 1, 2,..., 554, the real addresses 0, 1, 2,. In addition, it is only necessary to read in ascending order of address numbers. After the reading of the effective image area 10a is completed, it is sufficient to continue selecting the next dummy row of the real address 555.
[0043]
On the other hand, in the reverse reading, the relative addresses are naturally the same as those in the forward reading as 0, 1, 2,... 554, but on the imaging unit 10, the real addresses 554, 553, and 552 are used. , ..., 0 must be read in ascending order. Further, after the reading of the effective image area 10a is completed, it is necessary to select a dummy row of the real address 555 to be continuously selected.
[0044]
The timing generator 20 outputs a vertical address signal, and the vertical decoder 14a receives it and selects a corresponding row, thereby controlling the reading order of the imaging unit 10 in the row direction. Here, the generation order of the vertical (row) address signal created by the timing generator 20 differs depending on the thinning, addition, and other read modes. Conventionally, an address signal generating circuit for inversion reading is further prepared for each. On the other hand, in the configuration of the first embodiment, the extended address signal generation circuit 200 generates an address signal as follows.
[0045]
How to generate the address signal in the timing generator 20 can be understood by the configuration of the extended address signal generation circuit 200 shown in FIG. The extended address signal generation circuit 200 includes a subtraction circuit 201 that is an example of a backward address generation unit, and a switching control circuit (an example of a control unit) 202 that controls an address system to be selected according to a mode. ing.
[0046]
The switching control circuit 202 includes an address (range 0 to 554 in this example) AD200 generated by a normal generation method in a forward address generation circuit (an example of a forward address generation unit) 21 in the timing generator 20. A switch 204 for selecting any one of the output addresses AD201 from the subtracting circuit 201, a switch 206 for selecting any one of the output address AD204 of the switch 204 and a dummy row address AD205 (555 in this example), A switch 208 for selecting either the output address AD206 of the switch 206 or the address AD207 not corresponding to the basic cell 10b is provided. The address AD207 not corresponding to the basic cell 10b may be “−; minus” or 556 or more in this example, and specifically, “1023” is set.
[0047]
The forward address generation circuit 21 incorporates an unillustrated up counter (increment counter) and gradually changes the address value in the forward direction (for example, as increment N) in both the forward read mode and the reverse read mode. Let For example, in the case of all-pixel reading, the increment value is incremented by “1” with increment N = 1. In addition, when thinning-out reading is performed every three rows, the increment value is incremented by “3” with an increment N = 3.
[0048]
The subtraction circuit 201, which is an example of the backward address generation unit, gradually changes the address value in the backward direction so as to correspond to the forward reading mode. For example, in the case of all pixel readout, the output address AD201 is decreased by “1”. In addition, when thinning-out reading is performed every three rows, the output address AD201 is decreased by “3”. At this time, the subtracting circuit 201 does not perform a simple decrement counting operation, and the address AD200 generated by the forward address generating circuit 21 and the most significant address ADmax (554 in this example) of the effective image area 10a. By taking the difference and outputting the difference (= ADmax−AD200) as the address AD201, the address value is gradually changed in the reverse direction. That is, the forward address generation circuit 21 and the subtraction circuit 201 constitute a substantial down counter.
[0049]
The extended address signal generation circuit 200 includes a register 210 that controls the selection operation of the switches 204, 206, and 208. The switches 204, 206, and 208 are all selected according to the register setting from the register 210, and the input terminal a side is selected in the normal mode (register setting; 1), and the input terminal b is selected in the special mode (register setting; 0). The side is to be selected.
[0050]
For example, according to the forward / reverse register setting from register 210, switch 204 selects address AD200 in the forward read mode (denoted F (1) in the figure), which is the normal mode, and in reverse read mode ( The address AD201 is selected for R (0) in the figure.
[0051]
In addition, the switches 206 and 208 functioning as an example of the switching selection unit of the present invention select the addresses AD204 and AD206 of the input terminal a according to a command from the register 210 during normal times (denoted as Nor (1) in the figure). However, when the specific address is set, the specified addresses AD205 and AD207 are selected.
[0052]
Specifically, the register 210 sets a register value 0 in the switch S206 during the blanking period for the purpose of setting a reading address in the blanking period after the reading of the effective image area 10a is completed. As a result, the address AD205 (555 in this example) is fixedly selected in both the forward reading mode and the backward reading mode, and a specific dummy row (real address 555 in this example) is selected by the vertical decoder 14a. To be.
[0053]
If no row is desired to be selected, the register 210 sets the register value 0 to the switch S208. As a result, the vertical decoder 14a selects the address value address AD207 (1023 in this example) that does not correspond to the real address of the basic cell 10b.
[0054]
Note that the address AD208 output from the switch 208 may pass through the buffer or be predecoded until it is transmitted to the vertical decoder 14a. Since they are irrelevant, their configuration is not shown.
[0055]
In such a configuration, the timing generator 20 (the forward address generation circuit 21) first creates a vertical address value in the forward direction in the order of address numbers 0 to 554 by a normal creation method. The vertical address in the forward direction passes through the subtraction circuit 201 and is selected (multiplexed) by the switch 204 depending on whether the read request is in the forward direction or in the reverse direction, as shown in FIG.
[0056]
Further, when a specific dummy row is to be selected or when no portion is to be selected (an address that does not exist such as 1023 suffices), switching can be performed by the switches 206 and 208.
[0057]
As described above, in the address control method of the first embodiment, in either the forward reading mode or the backward reading mode, only basic address generation corresponding to the forward reading mode is prepared, and the backward reading is performed. Only the special readout mode in the mode (inverted readout) is passed through the subtraction circuit 201. The address in the backward reading mode can be dealt with by switching the switch 204 by the forward / reverse register only by generating the forward address by a normal method. This is because the address designation according to the special readout mode such as the thinning readout mode or the addition readout mode may be performed by setting a common value for the forward address generation circuit 21 in both the forward and reverse directions.
[0058]
Therefore, by providing only one extended address signal generation circuit 200, various special read modes (for example, thinning read mode and addition read mode) can be handled even in the reverse read mode. For all the reading modes, if only the forward reading order address is generated by the forward address generating circuit 21, the address in the reverse direction is automatically output only by passing through the extended address signal generating circuit 200. Become so.
[0059]
As in the prior art, there is no need to make separate addresses for each forward / reverse, such as incrementing in the forward direction and decrementing in the backward direction, and all the operation modes can be handled at once. Therefore, a circuit for generating an address can be downsized, design load can be reduced, and design errors can be reduced. A compact and inexpensive address control circuit can be provided.
[0060]
Further, when a specific dummy row should be selected or where no selection should be made, a changeover switch (switches 206 and 208 in this example) can be provided to forcibly switch to those addresses. Become. Thus, it is easy to add a switching function to a specific address.
[0061]
<Address control; second example>
FIG. 3 is a diagram illustrating a second embodiment of address control for the imaging unit 10 of the solid-state imaging device 1 shown in FIG. Here, FIG. 3A shows an example of an address assigned to a row of the imaging unit 10. FIG. 3B shows an example of an extended address signal generation circuit 200 for implementing the address control method of the second embodiment. In the address control of the second embodiment, by providing the pixel array with inversion symmetry, it is possible to cope with the setting of the OPB (OPtical Black) level of the image pickup device and the image pickup unit 10 for color image pickup. It has a feature in that it can cope with the case. This will be specifically described below.
[0062]
As shown in FIG. 3 (A), the imaging unit 10 is assigned addresses 0 to 554 as the effective image area 10a in the vertical direction. The first feature is that a line (hereinafter referred to as OPB line) 10c for light-shielding pixels having insensitivity is assigned. In the illustrated example, two rows of lower addresses 0, 1 and upper addresses 553, 554 are assigned to the OPB line 10c, but in reality, more rows are assigned to the OPB line 10c. Good. The imaging unit 10 of the second embodiment is not provided with a readout line for dummy pixels.
[0063]
The light-shielding pixel of the OPB line 10c is provided with a light-shielding film on the upper surface (light-receiving surface side). By adjusting the OPB level of the image sensor to the reference level, there is a problem such as black floating or black sinking of the video signal. Is used to refer to the black level of the light-shielded pixel.
[0064]
Since the OPB level adjustment processing is normally performed on the top side in one screen, the lower OPB line 10c of the imaging unit 10 is used in the forward reading mode, and the upper OPB line 10c is used in the backward reading mode. It has come to be. In addition, as the second characteristic part of the present embodiment, the same number of light-shielding pixels on the top and bottom are prepared as the OPB line 10c, so that the positional relationship between the light-shielding pixels and the photosensitive pixels does not change in the forward direction or the reverse direction. .
[0065]
In the imaging unit 10, color separation filters for color imaging are arranged on the unit pixel 3 in the effective imaging area 10 d (range of addresses 2 to 552). In the illustrated arrangement, three kinds of colors are used, and they form a Bayer arrangement. That is, when attention is paid to pixels whose color is G (green), they are arranged in a checkered pattern every other pixel. When attention is paid to pixels whose color is R (red), they are arranged every other line. Similarly, when attention is paid to pixels whose color is B (blue), they are similarly arranged every other line.
[0066]
Note that the arrangement of the color separation filters is not limited to such a Bayer arrangement, and may be another arrangement. In addition, although a color separation filter is formed on the pixel to obtain a color image, as a third characteristic part of the present embodiment, the photosensitive pixels in the effective imaging area 10d are in odd rows, and the arrangement of the color separation filter is performed. Is vertically symmetrical.
[0067]
As shown in FIG. 3B, the extended address signal generation circuit 200 has a configuration in which the switch 206 is removed from the configuration of the first embodiment, and the output of the switch 204 is connected to one input terminal a side of the switch 208. ing. This is because the readout line for dummy pixels is omitted from the imaging unit 10. The basic operation of the extended address signal generation circuit 200 is the same as that of the first embodiment.
[0068]
In such a configuration, when reading in the forward direction, reading from the lower side in the direction of real addresses 0, 1, 2,... 552 (reading is not required for 553, 554) and reading in the reverse direction. Are read sequentially from the top in the direction of real addresses 554, 553, 552,..., 2 (1,0 is not required to be read).
[0069]
Note that the real addresses 553 and 554 are not required to be read in the forward read mode, and the real addresses 1 and 0 are not required to be read in the reverse read mode. The real addresses 553 and 554 and the real addresses 1 and 0 may be assigned to the readout line for the dummy pixel.
[0070]
Here, as described above, the imaging unit 10 of the second embodiment has the same number of light-shielding pixels at the top and bottom, and the relative positional relationship between the light-shielding pixels and the photosensitive pixels in the scanning scan changes in both the forward and reverse directions. I am trying not to. That is, the light receiving pixels and the light shielding pixels are arranged symmetrically in the reading direction so that they are relatively arranged at the same address in both the forward reading mode and the backward reading mode. For this reason, the signal acquired in the backward reading mode is simply passed through the signal processing circuit for forward reading without any change to the signal processing circuit for reading forward with respect to the black level of the solid-state imaging device. Thus, a reverse image can be obtained.
[0071]
In addition, the imaging unit 10 of the second embodiment forms a color image by forming a color separation filter on the unit pixel 3, but as described above, the total number of photosensitive pixels is an odd number, and color separation is performed. The arrangement of the filters is vertically symmetrical so that the relative positional relationship in readout scanning does not change. That is, the colors of the color filters on the light receiving pixels are arranged symmetrically in the readout direction so that the same color is arranged at the same relative address in both the forward readout mode and the backward readout mode. I am doing so. For this reason, in the color-related processing, the signal acquired in the backward reading mode is simply passed through the color processing circuit for forward reading without making any change to the color processing circuit for forward reading. Thus, a reverse color image can be obtained.
[0072]
FIG. 4 is a flowchart for explaining the address setting logic of the forward address generation circuit 21 in the address control of the second embodiment shown in FIG. Here, FIG. 4A shows the entire operation procedure and explains the significance of removing the switch 206. FIG. 4B explains the significance when the switch 208 is removed in addition to the operation in FIG.
[0073]
First, a description will be given based on the flowchart shown in FIG. When scanning the effective imaging area 10d, the forward address generation circuit 21 sequentially counts up the address value with the built-in up counter in both the forward reading mode and the backward reading mode (S100). As described in the address control of the first embodiment, the increment N is set to “1” in the case of all pixel readout, and is set to “1” in the case of performing thinning readout every three rows. 3 ”. The forward address generation circuit 21 repeats this counting operation until it detects a V start pulse that defines the scanning timing in the vertical direction (S104-NO, S106, S108).
[0074]
During this counting operation, if the count value AD200 is “554”, that is, the uppermost address ADmax of the effective image area 10a (S106—YES), this corresponds to the vertical blanking period. "554" is forcibly output to AD200. Once “554” is forcibly output to the count value AD200, the forward address generation circuit 21 maintains that state until a V start pulse is detected (S110, S100, S104-NO, S106-YES). When the V start pulse is detected (S104-YES), the forward address generation circuit 21 resets the count value AD200 to “0” (S112) and repeats the above operation.
[0075]
Therefore, during the vertical blanking period in the forward reading mode, the count value AD200 = 554 is selected by the switch 204 as it is, and is output as the address value AD208 via the switch 208, and the real address 554 on the imaging unit 10 is output. Will come to choose. Further, in the vertical blanking period in the reverse direction reading mode, the difference AD201 = 0 by the subtraction circuit 201 between the count value AD200 = 554 and the most significant address ADmax = 554 is selected by the switch 204, and is passed through the switch 208. Is output as the address value AD208, and the real address 0 on the imaging unit 10 is selected.
[0076]
That is, in the address control according to the second embodiment, unlike the address control according to the first embodiment, the dummy row selected during the period from scanning one screen to returning to the first row (vertical blanking period) is switched. A method of fixing by switching control (corresponding to 206 in FIG. 2) is not adopted. Instead, by using the counter value of the forward address generation circuit 21, the row of the real address 554 is selected in the forward read mode, and the row of the real address 0 is selected in the reverse read mode. .
[0077]
A similar method can be applied to “control when no row is selected”. For example, as in the flowchart shown in FIG. 4B, a determination step S102 for determining whether “no row is selected” is provided between steps S100 and S104. If no row is selected (S102-YES), the address value AD200 output from the forward address generation circuit 21 is forcibly set to the address value AD200α (S114).
[0078]
The address value AD200α is a value that does not correspond to the actual address of the basic cell 10b, and the value of the subtraction result AD201 by the subtraction circuit 201 using the address value AD200α also corresponds to the actual address of the basic cell 10b. It may be set to a value that does not. In the case of this example, if the forward address generation circuit 21 and the subtraction circuit 201 can handle at least 10 bits (1023), one of 555 and 1023 may be used.
[0079]
By doing so, the subtraction result by the subtraction circuit 201 becomes “negative; minus”, and the value is turned back to the range of 1023 to 555. In both the forward reading mode and the backward reading mode, the basic cell 10b An address value that does not correspond to a real address can be supplied to the vertical decoder 14a. That is, if the forward address generation circuit 21 outputs an address value that does not correspond to the basic cell 10b, whether or not it passes through the subtraction circuit 201, “switch control when no row is selected” is performed. The switch to be executed (208 in FIGS. 2 and 3) can be removed.
[0080]
As described above, according to the address control method of the second embodiment, in addition to obtaining the effects of the configuration of the first embodiment, the arrangement of the light-shielding pixels and the color separation filters can be arranged on the real address in the readout direction. Therefore, the signal processing circuit can be used as it is without having to correspond to the backward reading mode. That is, the OPB level adjusting circuit and the color signal processing circuit are only one system, and a compact and inexpensive imaging apparatus can be constructed. In addition, as shown in FIG. 4, by appropriately setting the counter value, a switching function to a specific address can be realized only by the forward address generation circuit 21 without providing a control switch, It is also possible to select a dummy output pixel and deal with the case where nothing is selected.
[0081]
<Address control; third example>
FIG. 5 is a diagram for explaining a third embodiment of address control for the imaging unit 10 of the solid-state imaging device 1 shown in FIG. Here, FIG. 5A shows an example of an address assigned to a row of the imaging unit 10. FIG. 5B shows an example of an extended address signal generation circuit 200 for implementing the address control method of the third embodiment.
[0082]
The address control of the third embodiment enables OPB level setting and color image capturing as well as the second embodiment, and the total number of lines in the effective imaging area 10d is the same as in the second embodiment. The image pickup unit 10 can be made smaller by reducing the total number of lines in the effective image area 10a including the OPB line 10c while maintaining it.
[0083]
In order to achieve such a configuration, first, the imaging unit 10 has a structure in which light-shielding pixels are arranged on either the front end side or the rear end side in the readout direction. The switching control circuit 202 uses the address value generated by either the forward address generation circuit 21 or the subtraction circuit 201 during the light-shielded pixel reading period in both the forward reading mode and the backward reading mode. Are commonly supplied to the vertical decoder 14a. Hereinafter, the description will focus on differences from the configuration of the second embodiment.
[0084]
The imaging unit 10 of the third embodiment assigns OPB lines 10c to any one of the upper and lower lines in the effective image area 10a, and only the light-shielded pixels are read in the same order in the forward direction and the reverse direction. Has characteristics. As described above, since the OPB level adjustment processing is normally performed at the head side in one screen, in the example shown in FIG. 5A, the OPB line 10c is at the head side in the forward reading mode. As shown, an OPB line 10c is provided on the lower side of the imaging unit 10 (for two lines of addresses 0 and 1 in the figure). The arrangement of the color separation filters is the same as in the second embodiment.
[0085]
As shown in FIG. 5B, the extended address signal generation circuit 200 includes a subtraction circuit 201, switches 204 and 208, and a register 210, in accordance with the extended address signal generation circuit 200 of the second embodiment. Here, the subtraction circuit 201 of the third embodiment is different from the subtraction circuit 201 of the first and second embodiments, and the address AD200 generated by the forward address generation circuit 21 and the “highest level of the effective image area 10a”. The side address ADmax + the number of OPB lines 10c (in this example, 556) "(hereinafter referred to as the subtraction initial value address ADpre) is taken and the difference (ADpre-AD200) is output as the address AD201.
[0086]
In the register 210, the set value (F (1) / R (0)) of the forward / reverse register for designating whether the scanning is the forward direction or the reverse direction, and the OPB period signal (OPB (1)) indicating the light-shielded pixel selection period. OR gate 212 is provided. The OR gate 212 has a function as a circuit for creating a forced forward scanning signal which is an example of a specific period signal.
[0087]
Here, the OPB period signal is “1; active” only when the output of the forward address generation circuit 21 corresponds to the OPB line 10c (that is, the row of light-shielded pixels) (in this example, addresses 0 and 1). Is a signal. The forward / reverse register is “1; active” in the forward reading mode and “0; inactive” in the backward reading mode.
[0088]
Thus, even in the reverse reading mode, the signal path can be forcibly switched to the side not passing through the subtracting circuit 201 during the period in which the OPB period signal is “1; active”. That is, in the OPB period in the reverse direction reading mode, a forced forward scanning signal, which is an example of a specific period signal, is read from the switch 248 so as to read out the light-shielded pixels of the OPB line 10c allocated below the effective image area 10a. Can be output.
[0089]
As described above, according to the address control method of the third embodiment, in addition to obtaining the effects of the configuration of the second embodiment, only the light-shielded pixels can be read in the same order in both the forward and reverse directions. With this configuration, it is not necessary to increase the number of light-shielded pixels, and as a result, the imaging unit 10 can be made smaller.
[0090]
In the description of the third embodiment, OPB lines 10c are provided for two lines of addresses 0 and 1 so that the OPB line 10c is arranged on the head side in the forward reading mode, and in the backward reading mode. In the OPB period (period in which the forced forward scanning signal is 1), a signal path that does not pass through the subtraction circuit 201 is forcibly selected, and the OPB line 10c assigned to the lower portion of the effective image area 10a is shielded. The pixel is read out, but this relationship may be reversed.
[0091]
That is, the OPB line 10c is provided for two lines of the addresses 554 and 553 so that the OPB line 10c is arranged on the head side in the backward reading mode, and the OPB period (the forced backward scanning signal is set in the forward reading mode). In the period 1), a signal path that does not pass through the subtraction circuit 201 is forcibly selected to read out the light-shielded pixels of the OPB line 10c allocated above the effective image area 10a.
[0092]
As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.
[0093]
Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily required for the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.
[0094]
For example, in each of the embodiments described above, the values on the subtracted side of the subtracting circuit 201 can be made variable as indicated by general codes such as ADmax and ADpre instead of fixed values. By doing so, it becomes possible to flexibly deal with various types of imaging devices such as the number of pixels (number of columns and rows) of the imaging unit 10 and the form of dummy pixels, and it becomes easy to apply and develop to various systems. .
[0095]
In the above-described embodiment, the case of reading address control in an XY address type imaging device in which a plurality of unit pixels are arranged two-dimensionally has been described. However, the technical idea of the present invention is X It is not limited to application to a Y address type imaging device. For example, the present invention can be similarly applied to a line sensor (one-line imaging device) in which a plurality of unit pixels (unit elements) are arranged in a one-dimensional manner. Of course, the present invention can be similarly applied to a line-shaped (elongated) imaging device having only a few rows.
[0096]
In the above embodiment, the column-type solid-state imaging device in which the signal output from the pixels arranged in rows and columns is a voltage signal and the CDS processing function unit is provided for each column has been described as an example. However, the solid-state imaging device is not limited to the column type. For example, a solid-state imaging device in which the signal output from the pixel is a current signal may be used. In short, as long as the signal obtained by the light receiving element can be read out by addressing like the XY address type, the technique described in the above embodiment can be applied, and the same effect can be obtained. be able to.
[0097]
Further, the present invention is not limited to the imaging device, and can be applied to read address control in a general semiconductor memory. That is, the technical idea of the present invention specifically shown in the above embodiment is based on a basic cell in which a plurality of unit elements are arranged in a one-dimensional shape or a two-dimensional shape, and a read target among the plurality of unit elements. The present invention can be applied to read address control for setting an address value indicating the position of a read target in any kind of semiconductor device having a decoder for selecting the same, and in these cases as well, as in the above embodiment You can enjoy the effects of For example, the image pickup signal read by the CCD image pickup device can be temporarily stored in a page memory (frame memory or field memory), and then applied to control when reading.
[0098]
【The invention's effect】
As described above, according to the present invention, even in the reverse read mode, the address value is gradually changed in the reverse direction using the address value generated by the forward address generation unit, so that the reverse read mode is The address value for was set. Accordingly, if only one address counter is prepared for the forward reading mode, 1 for various reading modes such as various special readings (for example, addition reading and thinning reading) in the reverse reading mode. The address counter circuit can be used.
[0099]
Further, if the arrangement of the light-shielding pixels and the color separation filter is made symmetric, the signal processing circuit for the forward reading mode can be used as it is without requiring the signal processing circuit to correspond to the backward reading mode. In addition, it is possible to add a switching function to a specific address, and it is possible to cope with a case where a dummy output pixel or nothing is selected.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining a first embodiment of address control for the imaging unit 10 of the solid-state imaging device 1 shown in FIG. 1;
FIG. 3 is a diagram illustrating a second embodiment of address control for the imaging unit 10 of the solid-state imaging device 1 shown in FIG. 1;
FIG. 4 is a flowchart illustrating address setting logic in address control according to the second embodiment.
FIG. 5 is a diagram for explaining a third embodiment of address control for the imaging unit 10 of the solid-state imaging device 1 shown in FIG. 1;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 3 ... Unit pixel, 7 ... Drive control part, 10 ... Imaging part, 10a ... Effective image area, 10b ... Basic cell, 10c ... OPB line, 10d ... Effective imaging area, 11 ... Horizontal control line, DESCRIPTION OF SYMBOLS 12 ... Horizontal scanning circuit, 12a ... Horizontal decoder, 12b ... Horizontal drive circuit, 13 ... Horizontal readout line, 13 ... Pixel signal line, 14 ... Vertical scanning circuit, 14a ... Vertical decoder, 14b ... Vertical drive circuit, 15 ... Vertical control Line 18, Horizontal signal line 19, Vertical signal line 20, Timing generator 21, Forward address generation circuit 26, CDS processing unit 28, Output buffer 100, External circuit, 110 A / D conversion unit , 130 ... digital signal processing unit, 136 ... D / A conversion unit, 200 ... extended address signal generation circuit, 201 ... subtraction circuit, 202 ... switching control circuit, 204, 206, 08 ... switch, 210 ... register, 212 ... OR gate (circuit for generating a specific period signal)

Claims (16)

For a semiconductor device comprising a basic cell in which a plurality of unit elements are arranged one-dimensionally or two-dimensionally and a decoder that selects a reading target among the plurality of unit elements. A method of setting an address value indicating a position to be read,
In the forward reading mode, an address value system obtained by gradually changing the address value in the forward direction is supplied to the decoder, and in the substantially backward reading mode, the address value is gradually changed in the forward direction. using the resulting address value, substantially to obtain a graduated address value in the opposite direction, the substantially strains graduated address value in the opposite direction so supplied to the decoder, address value When executing the switching control of the system by the control unit,
Each address value in the forward reading mode and the backward reading mode is taken into one input terminal of the control unit, a specific address value is taken into the other input terminal of the control unit, and the one and the other The address value system switching control is executed by selecting and outputting the address value input to any one of the input terminals.
Read address control method. By taking the difference between the address value obtained by gradually changing the address value in the forward direction and a predetermined initial value, the address value gradually changed in the reverse direction is obtained.
The read address control method according to claim 1. For a semiconductor device comprising a basic cell in which a plurality of unit elements are arranged one-dimensionally or two-dimensionally and a decoder that selects a reading target among the plurality of unit elements. A read address control device for setting an address value indicating a position to be read,
A forward address generator for gradually changing the address value in the forward direction;
Using the address value generated by the forward address generation unit, a reverse address generation unit that gradually changes the address value in the reverse direction;
In the forward read mode, the address value system generated by the forward address generator is supplied to the decoder. In the reverse read mode, the address value system generated by the backward address generator is supplied to the decoder. as a control unit for performing switching control is,
Equipped with a,
In the control unit, an address value generated by the forward address generation unit or the reverse address generation unit is input to one input terminal, and a specific address value is input to the other input terminal. A switching selection unit for selecting and outputting an address value input to any one of the other input terminals;
Read address control device. The backward address generation unit includes a subtraction processing unit that takes a difference between a predetermined initial value and an address value generated by the forward address generation unit.
The read address control device according to claim 3. The reverse address generation unit is configured to be able to arbitrarily set the initial value.
The read address control device according to claim 4. The control unit performs switching control so that an address value not corresponding to the real address of the basic cell is supplied to the decoder as the specific address value.
The read address control device according to claim 3. The forward address generation unit is configured such that both the address value generated by the forward address generation unit and the address value generated by the reverse address generation unit based on the address value are real addresses of the basic cells. Configured to generate address values that do not correspond to
The read address control device according to claim 3. In either the forward reading mode or the backward reading mode, the control unit commonly uses either the forward address generation unit or the backward address generation unit for a predetermined period. The address value generated by one of the two is controlled to be supplied to the decoder
The read address control device according to claim 3. The control unit includes a circuit that generates a specific period signal that defines the predetermined specific period.
The read address control device according to claim 8 . A semiconductor device comprising: a basic cell in which a plurality of unit elements are arranged in a one-dimensional or two-dimensional manner; and a decoder that selects a read target among the plurality of unit elements;
A forward address generator for gradually changing the address value in the forward direction;
Using the address value generated by the forward address generation unit, a reverse address generation unit that gradually changes the address value in the reverse direction;
In the forward read mode, the address value system generated by the forward address generator is supplied to the decoder. In the reverse read mode, the address value system generated by the backward address generator is supplied to the decoder. as a control unit for performing switching control is,
With
In the control unit, an address value generated by the forward address generation unit or the reverse address generation unit is input to one input terminal, and a specific address value is input to the other input terminal. A switching selection unit for selecting and outputting an address value input to any one of the other input terminals;
Semiconductor system. The semiconductor device includes a light receiving pixel that outputs a signal corresponding to an incident light amount as the unit element.
The semiconductor system according to claim 10 . The semiconductor device includes:
A light-shielding pixel having insensitivity to incident light is included as the unit element,
The light-receiving pixels and the light-shielding pixels are arranged symmetrically in the readout direction so that they are relatively arranged at the same address in both the forward readout mode and the backward readout mode.
The semiconductor system according to claim 11 . The semiconductor device includes a light-shielding pixel having insensitivity to incident light as the unit element, and the light-shielding pixel is arranged on one of a front end side and a rear end side in the readout direction. Has been
The control unit is generated by either the forward address generation unit or the reverse address generation unit during the reading period of the light-shielded pixels in both the forward direction readout mode and the backward direction readout mode. The address value is commonly supplied to the decoder.
The semiconductor system according to claim 11 . The semiconductor device includes:
Any color filter constituting a color separation filter for color image capturing is provided on each light receiving surface of the light receiving pixel,
The colors of the color filters on the light receiving pixels are arranged symmetrically in the readout direction so that the same color is arranged at the same relative address in both the forward readout mode and the backward readout mode. Has been
14. The semiconductor system according to any one of claims 11 to 13 . A basic cell that includes a light receiving pixel that outputs a signal corresponding to the amount of incident light and a light shielding pixel that is insensitive to incident light as unit elements, and the unit elements are arranged in a one-dimensional or two-dimensional array. ,
A decoder for selecting one of the plurality of unit elements to be read; and
In each of the forward reading mode and the backward reading mode, an address value system corresponding to each mode is taken into one input terminal, a specific address value is taken into the other input terminal, the one and the other A control unit configured to select and output an address value input to any one of the input terminals;
Comprising
The light receiving pixels and the light shielding pixels are arranged symmetrically on the real address in the reading direction ,
The decoder fetches the address value system for the forward read mode in the forward read mode from the control unit, and fetches the address value system for the reverse read mode in the backward read mode.
Imaging device. A basic cell including a light receiving pixel that outputs a signal corresponding to the amount of incident light as a unit element, the unit elements being arranged in a one-dimensional or two-dimensional manner ,
A decoder for selecting one of the plurality of unit elements to be read; and
In each of the forward reading mode and the backward reading mode, an address value system corresponding to each mode is taken into one input terminal, a specific address value is taken into the other input terminal, the one and the other A control unit configured to select and output an address value input to any one of the input terminals;
Comprising
Any color filter constituting a color separation filter for color image capturing is provided on each light receiving surface of the light receiving pixel,
The colors of the color filters on the light receiving pixels are arranged symmetrically on the real address in the reading direction so that the same color is arranged at the same relative address ,
The decoder fetches the address value system for the forward read mode in the forward read mode from the control unit, and fetches the address value system for the reverse read mode in the backward read mode.
Imaging device.

Images