JP2780718B2 - Data processing system that buffers data cyclically - Google Patents

Description

The present invention relates to a data processing system comprising a memory that buffers sequential data units for a cyclically recurring delay length period.

The invention also relates to a selection means suitable for use in such a system, for generating a periodic sequence of time slots having a length for a delay length for each one of at least two memory locations. A data processing system of the kind described above is described in "Efficient Code Generation for Horizontal Architectures: Compiler Techniques and Architecture Support" by Lau et al., 9th Annual Computer Architecture Symposium, Austin, pp. 131-139.
It is more known. This document also details the field of application, parallel and interactive data processing.
In this type of data processing, the new stream is
Generated from various parallel streams of sequential data units. Before the data units of the new stream are processed again, these data units are delayed with respect to each other so that they are in a position to be combined with one another in a suitable manner at a suitable time. Since the sequence of operations is cyclically repeated, the delay of the data unit is effected by temporarily storing it in memory for a cyclic recursive delay time. The buffering of data units in prior art data processing systems is performed with the aid of compression means. These compression means allow the remaining stored data units after data has been read from one of the memory locations to be relocated to logically linked memory locations as needed. When a new data unit is written, it is written to an unoccupied memory location having an address as close as possible to the address of the occupied memory location.
This relocation of data units and updating of the nearest unoccupied memory location will certainly utilize available memory locations, but will require extensive hardware.

Accordingly, it is an object of the present invention to provide a data processing system that utilizes available memory locations with substantially the same efficiency as the prior art while using less hardware. For this purpose, the data processing system of the invention is provided with a selection means for generating a periodic sequence of time slots having a length corresponding to the delay length for each one of the at least two memory locations, Each time slot starts with a write phase for the relevant data unit and ends with a read phase where the relevant data unit is read last, in which sequence period has a length corresponding to a cyclically recurring delay length. In which the read phase of the preceding time slot is followed by the next possible write phase as another sequence of time slots, and the mutual shift between the sequence in a series of memory locations. Is for a single cycle, and the period is the sum of And wherein the Shii.

According to the data occupation obtained by the selecting means, an efficient use of a memory location which does not require relocation and also does not require hardware required for relocation. No more memory locations are required than the number of consecutive cycles in which the duration of the sequence of time slots matches. The period itself consists of a reordering of the slots corresponding to the delay lengths organized by the first-fit algorithm and assigned per cycle. As a result of the mutual shift between the various occupied memory locations, the connected memory locations have a time slot occupancy per cycle corresponding to the time slot occupancy of the period.

In one embodiment of the data processing system of the present invention, the selection means includes reference means for generating a next reference value at the start of each of the next cycles of the delay length, wherein the sequence of reference values comprises a time slot sequence. The selection means is recursive during a series period, and further comprises the first increment and the second increment, each of which recursively recursively, respectively, linearly combined with the current reference value, thereby forming the memory read address and the memory write address. It has a first combination means and a second combination means for respectively generating addresses. The read address and the write address are determined on a cycle-by-cycle basis relative to the reference value. Since the reference value jumps at the start of the next cycle, the read address and the write address also jump from the address of the previous cycle. After several cycles covering the period, the read and write addresses are repeated again.

Another embodiment of the data processing system according to the invention is characterized in that the reference means comprises a modulo counter having a count value representing the current reference value, whereby a periodic reference value is generated in a simple manner. You. A further embodiment of the data processing system according to the invention is characterized in that the jump between successive reference values is adjustable and the increment is adjustable. Because the reference value and the increment are adjustable, the system can be suitable for multiple applications.

In another embodiment of the data processing system according to the present invention, the selecting means sequentially and linearly recursively returns the third increment and the fourth increment to the preceding first address and first address, respectively. And a fourth combination means for sequentially generating a first address and a second address for the memory by combining the first address and the second address. The first address and the second address are a write address and a read address. Or a read address and a write address. In this configuration, by appropriately selecting the increment to be supplied to the combination means, the modulo counter is omitted as compared with the above embodiment.

FIG. 1 is a block diagram of an example of a data processing system of the type described above. This example shows a data processing element 10 in which data outputs 11 and 12 are connected to data inputs 17 and 18 by data output lines 13 and 14 and data input lines 15 and 16. This connection is made by an interconnection network 19 in which connection elements 20, 21, 22 and 23 are provided at the connection points of the data output lines and the data input lines. These connecting elements are means for distributing data units from the various streams provided via output lines 13 and 14 to the input lines before the data undergoes new processing at element 10. A connection element for combining data units not simultaneously available on the data output line has a memory location for buffering the data units for a predetermined period. Since the data unit undergoes a cyclic processing sequence, these periods also recur cyclically.

FIG. 2 shows an example of how data occupancy is generated at a memory location in a prior art data processing system.
The data unit consists of phases 0, 1, 2, 3 and 4
Buffered in a memory location having addresses 0, 1, 2, and 3 in a phase cycle. Phases (ph) are plotted horizontally and addresses (ma) of memory locations are plotted vertically. In phases 0, 1, 3, and 4 of the cycle, data units that are buffered for 6, 1, 2, and 5 phases, respectively, are written. These data units are then read in phase 1 of the next cycle, phase 2 of the same cycle, phase 0 of the next cycle, and phase 4 of the next cycle. Data units having write phases 0, 1 and 4 are all written to the memory location at address 3. The data units of the write phase are written to memory locations. As soon as the memory location at the lower address is emptied, the data unit at the memory location at the higher address is transferred to the lower address.
While this certainly makes use of the available memory locations, it does provide a large-scale approach to monitoring the logically closest unoccupied memory locations and relocating data units to memory locations. Logic is required.

FIG. 3 shows an example of how data occupancy is generated on a memory location in the data processing system of the present invention. FIG. 3 also uses the cycle used in FIG. In FIG. 3, for each memory location, there is a data occupation having a period of four cycles in each one of the time slots corresponding to a periodic, cycle-specific delay length. Memory location 0 is occupied by the first data unit for six consecutive phases. After this memory location has been read, the next second data unit is written to the same memory location in a write phase with a delay length not initially included in the period following the read phase of the first data unit. Be included. This is thus a data unit with write phase 3 and read phase 0 of the next cycle. The same selection criteria apply to data units having write phases 1 and 4. The illustrated rearrangement of the time slots realizes the shortest period length. Corresponding data occupation takes place in memory locations 1, 2 and 3. The data occupations in the memory locations are shifted one cycle from each other. The data occupancy in this example requires the same number of memory locations as the data occupancy described in conjunction with FIG. 2, but requires significantly less hardware because data units do not have to be relocated on the memory locations. For clarity, the above example has been limited to four different delay length cycles. The advantages of the data processing system of the present invention are significant when three data units are buffered in one cycle, so it is clear that more (eg, twenty) data units are buffered in one cycle.

FIG. 4 shows a first configuration example of a memory having a selection means in the data processing system of the present invention. Memory 30 has a memory location for buffering sequential data units. The incoming data stream is referenced 32 and the outgoing data stream is referenced 34. The write and read addresses of the memory are addressed via inputs 36 and 38, respectively. The periodicity of each memory location and the mutual shift in sequence are realized by a modulo counter 40 whose contents jump by a predetermined amount every cycle by a trigger pulse to the input terminal 42 preceding the next cycle. The fixed jump value is added to the current count value for each cycle. Thus, the output signal at output terminal 46 represents a reference value that jumps at a fixed step every cycle. This reference value is supplied to adders 48 and 50. The adding circuit 48 performs a cyclic first increment, the adding circuit 50 performs a cyclic second increment,
It is supplied via terminals 52 and 54, respectively. These circuits obtain the current write address and the actual read address of the memory location by adding the increment to a current reference value. As can be readily appreciated, in the example described with reference to FIG. 3, a modulo counter having counts 0, 1, 2, and 3 is appropriate, and a fixed step equal to the number 1 per cycle is currently present. Is subtracted from the current count value representing the reference value of.

FIG. 5 shows a second configuration example of the memory having the selection means in the data processing system of the present invention. Elements corresponding to elements in FIG. 4 are indicated by the same reference numerals.
In FIG. 5, the selecting means includes first and second adding circuits.
60 and 62, and a memory element 64 inserted between the output 66 of the adder circuit 60 and the first input 68. A second input 70 of the adder circuit 60 is supplied with a third increment which is sequential and recursive. The current third increment is added to the contents of memory element 64. The sum represents the next write address. The sum is also provided to a first input of a second summing circuit 62. A second input 72 of the second adder circuit 62 is supplied with a fourth increment which is sequentially and recursively recursive. The sum output from the second adder circuit represents the next read address.

The selection means, some of which are shown in FIGS. 4 and 5,
It can be limited to embodiments where a single signal address is provided to the memory each time. However, in that case, means are provided for verifying whether the given address is a read address or a write address. The disadvantage that reading and writing exclude each other is offset by the advantage of using relatively slow memory.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data processing system of the type described at the beginning of the Detailed Description of the Invention, FIG. 2 is an example of how data occupancy is generated on a memory location in a prior art data processing system. FIG. 3 is a diagram showing an example of a mode in which data occupancy is generated on a memory location in the data processing system of the present invention. FIG. 4 is a diagram showing a memory having selection means in the data processing system of the present invention. FIG. 5 is a diagram showing a second configuration example of a memory having a selection means in the data processing system of the present invention. 10 …… Data processing element, 11,12 …… Data output, 13,14…
… Data output line, 15,16 …… Data input line, 17,
18 …… Data entry, 19 …… Interconnect network, 20,2
1,22,23 ... Connection element, 30 ... Memory, 32,34 ... Data stream, 36,38 ... Input, 40 ... Modulo counter, 42,46,52,54 ... Terminal, 48,50 , 60,62 …… Addition circuit,
64 …… Memory element.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 5/06 G06F 12/02

Claims (9)

(57) [Claims] 1. A data processing system comprising a memory for buffering sequential data units during periods of a delay length that recurs in successive cycles, wherein each of at least two memory locations has a delay length. Selection means are provided for generating a periodic sequence of time slots having a corresponding length, wherein each time slot for a memory location starts with a write phase for the associated data unit and the read for which the associated data unit is read last. Ending with a phase, wherein the sequence period in the sequence includes a permutation of time slots corresponding to the delay length that recurs cyclically, and a reading phase of a preceding time slot in the permutation includes another possibly following sequence. Time slot write phase follows And wherein the mutual shift between the series of consecutive memory locations is a single cycle, and wherein said period is equal to the sum of said mutual shifts. 2. The apparatus according to claim 1, wherein said selecting means includes a reference means for generating a next reference value at the start of each next cycle of the delay length, wherein the reference value sequence is recursive at a period of a time slot sequence. The selecting means comprises a first combination means for respectively generating a read address and a write address for the memory by linearly combining the first increment and the second increment which are cyclically recursive with the current reference value, respectively. 2. The data processing system according to claim 1, further comprising a second combination unit. 3. The data processing system according to claim 2, wherein said reference means comprises a modulo counter having a count value representing a current reference value. 4. The data processing system according to claim 2, wherein the transition between the sequential reference values is adjustable. 5. The memory according to claim 1, wherein the selecting means sequentially and linearly combines the third and fourth increments that are cyclically recursive with the preceding first and first addresses, respectively. A third combination means and a fourth combination means for respectively generating a first address and a second address, wherein the first address and the second address are a write address and a read address, or 2. The data processing system according to claim 1, wherein the data processing system comprises a read address and a write address. 6. A first input of said third combination means is supplied with said third increment, an output is fed back to a second input via a memory element, and a first input of said fourth combination means is provided. 6. The data processing system according to claim 5, wherein an input of the third combination means is supplied with the fourth increment, and a second input is connected to the output of the third combination means. 7. A different stream of sequential data units is provided to a memory, and different pairs of said combining means are provided for said stream, each pair of another stream of said cyclically recurring increment. The data processing system according to any one of claims 2 to 6, wherein is supplied to each of the pairs of the combination means. 8. In addition to the first stream of sequential data units, another stream of sequential data units is provided to the memory, and for said another stream said selection means comprises another one of another combination means. Two associated inputs of said further combination means are connected to the outputs of said third combination means, the associated first inputs being supplied with another cyclically recurring increment. 7. The data processing system according to claim 6, wherein: 9. The data processing system according to claim 2, wherein said increment is adjustable.