JP2778109B2 - Electronics - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an electronic device capable of identifying types of a plurality of peripheral devices connected to a main device.

[Summary of the Invention]

In the present invention, in an electronic device such as a word processor configured by connecting a plurality of types of peripheral devices to a main device, a setting unit that sets a code indicating the type of the peripheral device in advance in each peripheral device is provided. The type codes of these peripheral devices are sequentially generated from the type code generation means provided in the main unit and sent to each peripheral device, and in each peripheral device, the output from the type code generation means is converted to the type code of the internal setting means. By detecting the match, the result is transmitted to the main unit, and the control program of the peripheral corresponding to the type code is made operable in the main unit, whereby the type of the peripheral connected to the main unit is determined. It is automatically determined and used.

[Conventional technology]

For example, main units of electronic devices such as word processors and computers include input devices such as keyboards, scanners, joysticks and mice, output devices such as display devices and printers, and input / output devices such as disk devices and communication devices. In many cases, various peripheral devices are connected and used. By connecting such various peripheral devices to the main unit, the functions of electronic devices such as a word processor and a computer are expanded, and the peripheral devices can be used for various purposes.

[Problems to be solved by the invention]

By the way, when various peripheral devices are connected to the main unit as described above, software (control program) for controlling the operation of these peripheral devices is required. Therefore, the user needs to perform a troublesome operation such as confirming the connected peripheral device, calling a corresponding control program from a built-in memory such as a ROM in the main device, and setting the control program to an operable state. .

The present invention has been made in order to solve such a disadvantage, and an electronic device that can automatically determine the type of peripheral device connected to the main unit by the main unit and eliminate troublesome operation on the user side. The purpose is to provide equipment.

[Means for solving the problem]

As shown in FIG. 1, the electronic device according to the present invention includes a setting unit (for example, an address decoder 21) for setting a type code indicating the type of the peripheral device 20 in the peripheral device 20 connected to the main device 10 in advance. The type code of the peripheral device connectable to the main unit 10 is sequentially generated by the CPU 11 serving as a type code generating unit provided in the main unit 10 and set by the setting unit (address decoder 21). Detecting that the type code matches the output from the type code generating means, transmitting the result to the main unit 10, and in the main unit 10, the peripheral device 20 corresponding to the type code
Is in an operable state.

(Operation)

When the type code sequentially generated by the type code generating means (CPU 11) in the main unit 10 matches the type code set by the setting means (address decoder 21) in each peripheral device 20, the peripheral device 20 is activated. Main unit 10
The main device 10 can determine the type of the connected peripheral device, and can put the control program of the determined type of peripheral device into an operable state.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of an electronic apparatus according to the present invention.

In FIG. 1, the main unit 10 is assumed to be, for example, a word processor.
For example, various peripheral devices 20 such as input devices such as a keyboard, a scanner, a mouse, and a joystick, output devices such as a display device and a printer, and input / output devices such as a disk device and a communication device are connected. I have.

At least a read (read) control signal transmission line 33 and a reset signal transmission line 34 of the address bus 31, the data bus 32, and the control bus are provided and connected between the main device 10 and the peripheral device 20. ing. Here, the read control signal and the reset signal are all low active.

The main unit 10 includes the address bus 31 and the data bus.
32 and a CPU (Central Processing Unit) 11 to which a control bus is connected. The CPU 11 has a ROM (Read Only Memory) 1 in which programs and data are stored.
2 and RAM (random access memory) are connected.

In the peripheral device 20, an address decoder 21 connected to the address bus 31 and a data transceiver 22 connected to the data bus 32 are provided. The address decoder 21 is also used as setting means for setting a type code indicating the type of the peripheral device 20 (printer, mouse, disk device, etc.) as described later. The address decoder 21 and the data transceiver 22 are connected to a peripheral device control element 23 for performing data processing, operation control, and the like in the peripheral device 20. The peripheral device control element 23 is provided with at least a chip select terminal (or enable terminal) CS, a data input / output terminal DIO, and a reset terminal RST, and an output from the address decoder 21 is supplied to the chip select terminal CS. And
Data is transmitted and received between the data transceiver 22 and the data input / output terminal DIO. Here, the chip select terminal CS and the reset terminal RST are all low active. The above address decoder 21
(Low active) are supplied to a negative input NAND gate (OR gate) 24 having two negative inputs and a negative input AND gate 25 having three negative inputs, respectively. A reset signal (low active) from the reset signal transmission line 34 is supplied to the NOT input AND gate 24 via an inverter (NOT circuit) 26.
The output from the ND gate 24 is supplied to a low-active gate terminal G of the data transceiver 22. The negative input AND gate 25 is supplied with the low active read control signal and the reset signal.
The output from the AND gate 25 is sent one bit line in the data bus 32 via a diode 27 (e.g., 8-bit bus), for example, the least significant bit of the (so-called LSB) D ₀ line.

Here, when transmitting / receiving data to or from an arbitrary k-th peripheral device among a plurality of (n is assumed) peripheral devices connectable to the main device 10, the CPU 11 in the main device 10
Is, as shown in the peripheral device allocation memory map of FIG.
Data read (read) / write (write) is performed in the same manner as read / write to the memory while designating the address AD (k). In this case, the address value set in the address decoder 21 in the embodiment of the present invention is determined in advance corresponding to the type of the peripheral device, and also corresponds to the type code indicating the type of the peripheral device described above. . This is because in the peripheral device allocation memory map shown in FIG.
(N) means that the type of peripheral device assigned to each is determined in advance, for example, the address AD
The peripheral device of (1) is fixedly associated with a printer, and the peripheral device of address AD (2) is fixedly associated with a mouse or the like.
At the time of type identification of the peripheral device connected to the main unit, the address AD (1) to AD the least significant bit D ₀ of the data to be read by specifying (n) are flags for the type determination of the peripheral device (Identification flag). A plurality of peripheral device designated addresses may correspond to the same type of peripheral device.
Peripheral devices of (3) and AD (4) may be associated with a disk device. Also, the amount of memory allocated to one peripheral device is not limited to one byte. For example, a total of two bytes, one byte for read and one for write, may be used, or one for each function of one peripheral device.
Bytes may be allocated. In this case, there are a plurality of addresses for specifying one peripheral device for each function or the like, but only one address for reading the identification flag of the peripheral device is required for each peripheral device.

In the above configuration, when a predetermined peripheral device 20 is designated by the CPU 11 in the main device 10, the peripheral device 20 is designated.
Output from the address decoder 21 in the (low active)
Becomes "L" (low level, that is, active state), which is the above-mentioned negative input NAND gate 24 and negative input AND.
Each is sent to the gate 25. During normal operation, the low-active reset signal is "H" (high level), which is inverted by the inverter 26 and supplied to the negative input NAND gate 24. Is sent to the low-active gate terminal G of the data transceiver 22. That is, the assigned address of the peripheral device 20 is designated by the CPU 11 and the address decoder 21 in the peripheral device 20 is designated.
When the output from the device becomes "L", the data transceiver 22 is in the active state, and performs data transmission / reception between the data bus 32 and the peripheral device control element 23.

On the other hand, at the time of a reset operation such as at power-on, the low active reset signal becomes “L”, the peripheral device control element 23 is reset, and the output from the inverter 26 becomes “H”. The output from the NAND gate 24 is “H” regardless of the output from the address decoder 21, and the output from the NAND gate 24 is “H”.
The data transceiver 22 does not transmit / receive data.

At the time of this reset operation, when a predetermined peripheral device 20 is designated by the CPU 11 and data is read, the reset signal, the output from the address decoder 21 and the read control signal all become "L". , the output from the negative input aND gate 25 is sent as to "H", which is the data "1" of the identification flag to the line of the least significant bit D ₀ of the data bus 32 through the diode 27.

Therefore, the CPU 11 of the main unit 10 controls the reading of data while designating the assigned addresses corresponding to the types of the various peripheral devices as, for example, AD (1), AD (2),. The presence or absence of the peripheral device (whether or not it is connected) can be determined by looking at the value of the least significant bit D ₀ (identification flag) of the data. For example, when reading the data by specifying an arbitrary k-th peripheral assigned address AD (k), the value of the least significant bit D ₀ is "1" if it the k-th type of peripheral device is "Yes , That is, connected to the main unit 10, and if “0”, the k-th type peripheral device is “none” (not connected)
Becomes After this is performed up to the nth number of devices that can be connected to the main device 10, the software (control program for controlling the peripheral device) corresponding to the type of the peripheral device determined to be “present” is transmitted to the main device 10. It is called from ROM12 etc. in the inside and executed.

Such an operation of automatically identifying peripheral devices will be described with reference to FIG.

In FIG. 3, when the automatic identification of the peripheral device is started at the time of power-on or the like, first, as shown in step S1, the low-active reset signal becomes "L", and the loop control variable k (the type of the peripheral device) is set. (Corresponding to the order of the assigned addresses) is cleared to 0. This loop control variable k is incremented (k = k + 1) in step S2, and it is determined in the next step S3 whether or not the number of connectable peripheral devices is equal to or less than n (k ≦ n). Variable k is n or less (YE
In the case of S), the process proceeds to step S4 to read the data, particularly the identification flag (least significant bit D ₀ ), while specifying the k-th peripheral device by the address AD (k). In the next step S5, whether or not this data least significant bit D ₀ is the identification flag "1" (i.e., the output from the negative input AND gate 25 is "H") is discriminated, YES
In step S6, the process proceeds to step S6, where the k-th type of peripheral device is identified as "present" (connected to the main unit 10), and the process returns to step S2. The type of peripheral device is identified as “absent” (not connected to the main device 10), and the process returns to step S2. After this is repeated n times, which is the number of peripheral devices connectable to the main device 10 (that is, until it is determined as NO in step S3), the process proceeds to step S8. In step S8, the low-active reset signal is returned from "L" to "H" (non-active), and in the next step S9, software (peripheral device) corresponding to the type of peripheral device determined to be "present". The control program is called from the internal memory of the main body such as the ROM, and the operation state is set to an operable state.

According to the embodiment of the present invention described above, the address decoder is used as the type code setting means, and the output from the address decoder is used to read one bit (the least significant bit D _{0) of the} data bus during the read operation in the reset state. ) Enables identification of whether or not a peripheral device of the type is connected. Therefore, 3
By simply adding the negative input AND 25 and the diode 27 of the input, the automatic identification of the peripheral device can be easily realized, and the labor of the user can be greatly reduced.

Note that the present invention is not limited to only the above-described embodiment. For example, a type code setting unit different from the address decoder may be provided. In addition, it goes without saying that various changes can be made without departing from the spirit of the present invention.

〔The invention's effect〕

According to the electronic apparatus of the present invention, when the type code generated by the type code generation unit of the main unit matches the type code of the setting unit in the peripheral device connected to the main unit, the result is displayed in the main unit. Is transmitted to the main unit, the type of peripheral device currently connected can be identified on the main unit side,
The control program corresponding to the type of the peripheral device can be made operable. Thus, it is possible to omit a troublesome operation on the user side such as calling the control program while confirming the connected peripheral device as in the related art, which is convenient for use.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an electronic device according to the present invention, FIG. 2 is a diagram showing a peripheral device allocation memory map in the embodiment, and FIG. It is a flowchart for explaining. 10 Main unit 11 CPU (Central processing unit) 12 ROM (Read-only memory) 13 RAM (Random access memory) 20 Peripheral equipment 21 Address decoder 22 Data transceiver 23 … Peripheral device control element 24 …… Negative input NAND gate 25 …… Negative input AND gate

Claims (1)

(57) [Claims] 1. A setting device for setting a type code indicating the type of a peripheral device in advance in a peripheral device connected to the main device, wherein the type code of a peripheral device connectable to the main device is set in the main device. The peripheral device detects that the type code set by the setting unit matches the output from the type code generating unit, and the result is sent to the main unit. An electronic device, wherein the electronic device transmits a control program of a peripheral device corresponding to the type code in which the coincidence is detected in the main device to be operable.